Merge branch 'release/v1.4.11' into develop

a4637f37 · Federico Vaga · 3cd3234e · 1b803764 · a4637f37
Commit a4637f37 authored May 20, 2020 by Federico Vaga
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CHANGELOG.rst CHANGELOG.rst +9 -2

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 Change Log
 ==========

+[1.4.11] 2020-05-20
+===================
+Added
+-----
+- [hdl] export DDMTD clock output
+
 [1.4.10] 2020-05-12
-==================
+===================
 Added
 -----
 - [hdl] metadata source-id automatic assignment
@@ -46,7 +52,8 @@ Fixed
 -----
 - [hdl] DDR constraints
 - [hdl] DDR controller generic values are now properly capitalised
- [sw] Update svec-flasher to work with new type of flash memory used in newer SVEC boards
+- [sw] Update svec-flasher to work with new type of flash memory used in
+  newer SVEC boards

 [1.4.6] 2019-12-16
 ==================