Skip to content

S
Simple VME FMC Carrier SVEC
Commit e2ebda1e authored by Matthieu Cattin's avatar Matthieu Cattin
Browse files
Options

Cleanup circuit_board sir, add VME P2 tester design. 

 - Rename SVEC dir into EDA-02530-V0-0_SVEC.
 - Remove SVFC dir.
 - Add VME P2 tester Altium design (P2_tester).
parent dd8a66b5
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 5026 additions and 3342 deletions
circuit_board/P2_tester/P2_tester.OutJob 0 → 100644
View file @ e2ebda1e
This diff is collapsed.
circuit_board/P2_tester/P2_tester.PrjPCB 0 → 100644
View file @ e2ebda1e
This diff is collapsed.
circuit_board/P2_tester/P2_tester.PrjPCBStructure 0 → 100644
View file @ e2ebda1e
Record=TopLevelDocument|FileName=P2_tester.SchDoc
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.EXTREP 0 → 100644
View file @ e2ebda1e
------------------------------------------------------------------------------------------
Gerber File Extension Report For: P2_tester.GBR 30/08/2012 08:58:59
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GBL Bottom Layer
.GTO Top Overlay
.GTS Top Solder
.GBS Bottom Solder
.GBO Bottom Overlay
.GM1 Mechanical 1
------------------------------------------------------------------------------------------
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.GBL 0 → 100644
View file @ e2ebda1e
%FSLAX25Y25*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Physical_Order=2*
G04 Layer_Color=16711680*
%ADD10C,0.11811*%
%ADD11C,0.18110*%
%ADD12C,0.05906*%
%ADD13R,0.03937X0.03543*%
%ADD14C,0.01000*%
D10*
X98425Y175000D02*
D03*
Y0D02*
D03*
Y350000D02*
D03*
D11*
X0Y350000D02*
D03*
Y0D02*
D03*
D12*
X10000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X20000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X30000Y90000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X0D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X40000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
D13*
X58500Y47150D02*
D03*
Y40850D02*
D03*
Y79650D02*
D03*
Y73350D02*
D03*
Y93350D02*
D03*
Y99650D02*
D03*
Y117150D02*
D03*
Y110850D02*
D03*
Y123350D02*
D03*
Y129650D02*
D03*
Y147150D02*
D03*
Y140850D02*
D03*
Y153350D02*
D03*
Y159650D02*
D03*
Y177150D02*
D03*
Y170850D02*
D03*
Y183350D02*
D03*
Y189650D02*
D03*
Y207150D02*
D03*
Y200850D02*
D03*
Y213350D02*
D03*
Y219650D02*
D03*
Y237150D02*
D03*
Y230850D02*
D03*
Y243350D02*
D03*
Y249650D02*
D03*
Y267150D02*
D03*
Y260850D02*
D03*
Y273350D02*
D03*
Y279650D02*
D03*
Y297150D02*
D03*
Y290850D02*
D03*
Y303350D02*
D03*
Y309650D02*
D03*
Y327150D02*
D03*
Y320850D02*
D03*
D14*
X25000Y45000D02*
X30000Y40000D01*
X15000Y45000D02*
X25000D01*
X10000Y40000D02*
X15000Y45000D01*
X57650Y40000D02*
X58500Y40850D01*
X40000Y40000D02*
X57650D01*
X58500Y47150D02*
Y63500D01*
X52000Y70000D02*
X58500Y63500D01*
X40000Y70000D02*
X52000D01*
X35000Y55000D02*
X40000Y50000D01*
X35000Y55000D02*
Y72500D01*
X37000Y74500D01*
X57350D01*
X58500Y73350D01*
X40000Y80000D02*
X58150D01*
X10000Y110000D02*
X15000Y115000D01*
X45500D01*
X47650Y117150D01*
X58500D01*
X40000Y110000D02*
X57650D01*
X58500Y110850D01*
X10000Y100000D02*
X15000Y95000D01*
X46000D01*
X47650Y93350D01*
X58500D01*
X40000Y100000D02*
X58150D01*
X58500Y99650D01*
X10000Y140000D02*
X15000Y145000D01*
X45500D01*
X47650Y147150D01*
X58500D01*
X40000Y140000D02*
X57650D01*
X58500Y140850D01*
X10000Y130000D02*
X15000Y125000D01*
X46000D01*
X47650Y123350D01*
X58500D01*
X40000Y130000D02*
X58150D01*
X58500Y129650D01*
X10000Y170000D02*
X15000Y175000D01*
X45500D01*
X47650Y177150D01*
X58500D01*
X40000Y170000D02*
X57650D01*
X58500Y170850D01*
X10000Y160000D02*
X15000Y155000D01*
X46000D01*
X47650Y153350D01*
X58500D01*
X40000Y160000D02*
X58150D01*
X58500Y159650D01*
X10000Y290000D02*
X15000Y295000D01*
X45500D01*
X47650Y297150D01*
X58500D01*
X40000Y290000D02*
X57650D01*
X58500Y290850D01*
X10000Y280000D02*
X15000Y275000D01*
X46000D01*
X47650Y273350D01*
X58500D01*
X40000Y280000D02*
X58150D01*
X58500Y279650D01*
X10000Y260000D02*
X15000Y265000D01*
X45500D01*
X47650Y267150D01*
X58500D01*
X40000Y260000D02*
X57650D01*
X58500Y260850D01*
X10000Y250000D02*
X15000Y245000D01*
X46000D01*
X47650Y243350D01*
X58500D01*
X40000Y250000D02*
X58150D01*
X58500Y249650D01*
X10000Y230000D02*
X15000Y235000D01*
X45500D01*
X47650Y237150D01*
X58500D01*
X40000Y230000D02*
X57650D01*
X58500Y230850D01*
X10000Y220000D02*
X15000Y215000D01*
X46000D01*
X47650Y213350D01*
X58500D01*
X40000Y220000D02*
X58150D01*
X58500Y219650D01*
X10000Y200000D02*
X15000Y205000D01*
X45500D01*
X47650Y207150D01*
X58500D01*
X40000Y200000D02*
X57650D01*
X58500Y200850D01*
X10000Y190000D02*
X15000Y185000D01*
X46000D01*
X47650Y183350D01*
X58500D01*
X40000Y190000D02*
X58150D01*
X58500Y189650D01*
X58150Y310000D02*
X58500Y309650D01*
X40000Y310000D02*
X58150D01*
X47650Y303350D02*
X58500D01*
X46000Y305000D02*
X47650Y303350D01*
X15000Y305000D02*
X46000D01*
X10000Y310000D02*
X15000Y305000D01*
X57650Y320000D02*
X58500Y320850D01*
X40000Y320000D02*
X57650D01*
X47650Y327150D02*
X58500D01*
X45500Y325000D02*
X47650Y327150D01*
X15000Y325000D02*
X45500D01*
X10000Y320000D02*
X15000Y325000D01*
X10000Y80000D02*
X15000Y85000D01*
X25000D01*
X30000Y90000D01*
X25000Y75000D02*
X30000Y80000D01*
X15000Y75000D02*
X25000D01*
X10000Y70000D02*
X15000Y75000D01*
X10000Y50000D02*
X15000Y55000D01*
X25000D01*
X30000Y50000D01*
M02*
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.GBS 0 → 100644
View file @ e2ebda1e
%FSLAX25Y25*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Color=16711935*
%ADD10C,0.11811*%
%ADD11C,0.18110*%
%ADD12C,0.05906*%
%ADD13R,0.03937X0.03543*%
%ADD14C,0.01000*%
%ADD15C,0.00787*%
%ADD16C,0.00700*%
%ADD17C,0.12611*%
%ADD18C,0.18910*%
%ADD19C,0.06706*%
%ADD20R,0.04737X0.04343*%
D17*
X98425Y175000D02*
D03*
Y0D02*
D03*
Y350000D02*
D03*
D18*
X0Y350000D02*
D03*
Y0D02*
D03*
D19*
X10000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X20000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X30000Y90000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X0D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X40000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
D20*
X58500Y47150D02*
D03*
Y40850D02*
D03*
Y79650D02*
D03*
Y73350D02*
D03*
Y93350D02*
D03*
Y99650D02*
D03*
Y117150D02*
D03*
Y110850D02*
D03*
Y123350D02*
D03*
Y129650D02*
D03*
Y147150D02*
D03*
Y140850D02*
D03*
Y153350D02*
D03*
Y159650D02*
D03*
Y177150D02*
D03*
Y170850D02*
D03*
Y183350D02*
D03*
Y189650D02*
D03*
Y207150D02*
D03*
Y200850D02*
D03*
Y213350D02*
D03*
Y219650D02*
D03*
Y237150D02*
D03*
Y230850D02*
D03*
Y243350D02*
D03*
Y249650D02*
D03*
Y267150D02*
D03*
Y260850D02*
D03*
Y273350D02*
D03*
Y279650D02*
D03*
Y297150D02*
D03*
Y290850D02*
D03*
Y303350D02*
D03*
Y309650D02*
D03*
Y327150D02*
D03*
Y320850D02*
D03*
M02*
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.GM1 0 → 100644
View file @ e2ebda1e
%FSLAX25Y25*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Color=13278208*
%ADD10C,0.11811*%
%ADD11C,0.18110*%
%ADD12C,0.05906*%
%ADD13R,0.03937X0.03543*%
%ADD14C,0.01000*%
%ADD15C,0.00787*%
%ADD16C,0.00700*%
%ADD17C,0.12611*%
%ADD18C,0.18910*%
%ADD19C,0.06706*%
%ADD20R,0.04737X0.04343*%
D14*
X-11000Y360000D02*
X110000D01*
Y-10000D02*
Y360000D01*
X-11000Y-10000D02*
X110000D01*
X-11000D02*
Y360000D01*
D15*
X39351Y6372D02*
Y11095D01*
X41713D01*
X42500Y10308D01*
Y8734D01*
X41713Y7947D01*
X39351D01*
X1378Y11667D02*
X-1771D01*
X1378Y14816D01*
X-1771D01*
X10713Y11667D02*
X9139D01*
X8351Y12454D01*
Y14816D01*
X10713D01*
X11500Y14029D01*
X10713Y13241D01*
X8351D01*
X21500Y10093D02*
Y14816D01*
X19139D01*
X18351Y14029D01*
Y13241D01*
Y12454D01*
X19139Y11667D01*
X21500D01*
X28851Y7947D02*
X31213D01*
X32000Y8734D01*
Y10308D01*
X31213Y11095D01*
X28851D01*
M02*
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.GTL 0 → 100644
View file @ e2ebda1e
%FSLAX25Y25*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Physical_Order=1*
G04 Layer_Color=255*
%ADD10C,0.11811*%
%ADD11C,0.18110*%
%ADD12C,0.05906*%
D10*
X98425Y175000D02*
D03*
Y0D02*
D03*
Y350000D02*
D03*
D11*
X0Y350000D02*
D03*
Y0D02*
D03*
D12*
X10000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X20000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X30000Y90000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X0D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X40000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
M02*
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.GTS 0 → 100644
View file @ e2ebda1e
%FSLAX25Y25*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Color=8388736*
%ADD10C,0.11811*%
%ADD11C,0.18110*%
%ADD12C,0.05906*%
%ADD13R,0.03937X0.03543*%
%ADD14C,0.01000*%
%ADD15C,0.00787*%
%ADD16C,0.00700*%
%ADD17C,0.12611*%
%ADD18C,0.18910*%
%ADD19C,0.06706*%
D17*
X98425Y175000D02*
D03*
Y0D02*
D03*
Y350000D02*
D03*
D18*
X0Y350000D02*
D03*
Y0D02*
D03*
D19*
X10000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X20000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X30000Y90000D02*
D03*
Y80000D02*
D03*
Y70000D02*
D03*
Y60000D02*
D03*
Y50000D02*
D03*
Y40000D02*
D03*
Y30000D02*
D03*
Y20000D02*
D03*
Y170000D02*
D03*
Y160000D02*
D03*
Y150000D02*
D03*
Y140000D02*
D03*
Y130000D02*
D03*
Y120000D02*
D03*
Y110000D02*
D03*
Y100000D02*
D03*
Y250000D02*
D03*
Y240000D02*
D03*
Y230000D02*
D03*
Y220000D02*
D03*
Y210000D02*
D03*
Y200000D02*
D03*
Y190000D02*
D03*
Y180000D02*
D03*
Y260000D02*
D03*
Y270000D02*
D03*
Y280000D02*
D03*
Y290000D02*
D03*
Y300000D02*
D03*
Y310000D02*
D03*
Y320000D02*
D03*
Y330000D02*
D03*
X0D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
X40000Y330000D02*
D03*
Y320000D02*
D03*
Y310000D02*
D03*
Y300000D02*
D03*
Y290000D02*
D03*
Y280000D02*
D03*
Y270000D02*
D03*
Y260000D02*
D03*
Y180000D02*
D03*
Y190000D02*
D03*
Y200000D02*
D03*
Y210000D02*
D03*
Y220000D02*
D03*
Y230000D02*
D03*
Y240000D02*
D03*
Y250000D02*
D03*
Y100000D02*
D03*
Y110000D02*
D03*
Y120000D02*
D03*
Y130000D02*
D03*
Y140000D02*
D03*
Y150000D02*
D03*
Y160000D02*
D03*
Y170000D02*
D03*
Y20000D02*
D03*
Y30000D02*
D03*
Y40000D02*
D03*
Y50000D02*
D03*
Y60000D02*
D03*
Y70000D02*
D03*
Y80000D02*
D03*
Y90000D02*
D03*
M02*
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.REP 0 → 100644
View file @ e2ebda1e
*************************************************************
FileName = P2_tester.GBR
AutoAperture = True
*************************************************************
Generating : Top Layer
File : P2_tester.GTL
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
*************************************************************
*************************************************************
Generating : Bottom Layer
File : P2_tester.GBL
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D13
D14
*************************************************************
*************************************************************
Generating : Top Overlay
File : P2_tester.GTO
Adding Layer : Top Overlay
Used DCodes :
D14
D15
D16
*************************************************************
*************************************************************
Generating : Top Solder
File : P2_tester.GTS
Adding Layer : Top Solder
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D17
D18
D19
*************************************************************
*************************************************************
Generating : Bottom Solder
File : P2_tester.GBS
Adding Layer : Bottom Solder
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D17
D18
D19
D20
*************************************************************
*************************************************************
Generating : Bottom Overlay
File : P2_tester.GBO
Adding Layer : Bottom Overlay
Used DCodes :
D15
D16
*************************************************************
*************************************************************
Generating : Mechanical 1
File : P2_tester.GM1
Adding Layer : Mechanical 1
Used DCodes :
D14
D15
*************************************************************
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.RUL 0 → 100644
View file @ e2ebda1e
DRC Rules Export File for PCB: C:\mcattin\ohwr_projects\svec\trunk\circuit_board\P2_tester\P2_tester.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=6.00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=5.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
circuit_board/P2_tester/Project Outputs for P2_tester/Gerber/P2_tester.apr 0 → 100644
View file @ e2ebda1e
D10 ROUNDED 118.110 118.110 0.000 FLASH 0.000
D11 ROUNDED 181.102 181.102 0.000 FLASH 0.000
D12 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D13 RECTANGULAR 35.433 39.370 0.000 FLASH 270.000
D14 ROUNDED 10.000 10.000 0.000 LINE 0.000
D15 ROUNDED 7.874 7.874 0.000 LINE 0.000
D16 ROUNDED 7.000 7.000 0.000 LINE 0.000
D17 ROUNDED 126.110 126.110 0.000 FLASH 0.000
D18 ROUNDED 189.102 189.102 0.000 FLASH 0.000
D19 ROUNDED 67.055 67.055 0.000 FLASH 0.000
D20 RECTANGULAR 43.433 47.370 0.000 FLASH 270.000
circuit_board/P2_tester/Project Outputs for P2_tester/NC Drill/P2_tester.DRL 0 → 100644
View file @ e2ebda1e
TT#v 2 s k #v 2 s k #v 2 s k # 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 8 8 7 8 8 7 8 8 7 8 8 8 7 8 8 7 8 7 7 8 7 8 8 7 8 8 7 8 8 8 7 8 8 7 8 8 7 8 8 8 7 8 8 7 8 8 7 8 7 7 7 8 7 8 7 8 8 8 7 8 8 7 8 8 7 8 8 8 7 8 8 7 8 7 7 8 7 8 7 8 8 7 8 7 8 7 8 8 7 8 8 7 8 7 7 8 7 8 8 7 8 8 8 8 7 8 8 7 8 8 7 8 8 8 8 7 8 7 8 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 7 8 7 7 7 8 7 # 7 8 8 # 7 8 8 8 T
\ No newline at end of file
circuit_board/P2_tester/Project Outputs for P2_tester/NC Drill/P2_tester.DRR 0 → 100644
View file @ e2ebda1e
---------------------------------------------------------------------------
NCDrill File Report For: P2_tester.PcbDoc 30/08/2012 08:59:00
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : P2_tester.TXT
EIA File : P2_tester.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 39.37mil (1mm) Round 160 21.31 Inch (541.33 mm)
T2 110.24mil (2.8001mm) Round 2 3.50 Inch (88.90 mm)
T3 118.11mil (2.99999mm) Round 3 3.50 Inch (88.90 mm)
---------------------------------------------------------------------------
Totals 165 28.31 Inch (719.13 mm)
Total Processing Time (hh:mm:ss) : 00:00:00
circuit_board/P2_tester/Project Outputs for P2_tester/NC Drill/P2_tester.LDP 0 → 100644
View file @ e2ebda1e
Layer Pairs Export File for PCB: C:\mcattin\ohwr_projects\svec\trunk\circuit_board\P2_tester\P2_tester.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=p2_tester.txt|LayerPairs=gtl,gbl
circuit_board/P2_tester/Project Outputs for P2_tester/Status Report.Txt 0 → 100644
View file @ e2ebda1e
Output: NC Drill Files
Type : NC Drill
From : PCB Document [P2_tester.PcbDoc]
Generated File[P2_tester.TXT]
Generated File[P2_tester.DRL]
Generated File[P2_tester.LDP]
Generated File[P2_tester.DRR]
Files Generated : 4
Documents Printed : 0
Finished Output Generation At 08:59:01 On 30/08/2012
circuit_board/P2_tester/Status Report.Txt 0 → 100644
View file @ e2ebda1e
Output: NC Drill Files
Type : NC Drill
From : PCB Document [P2_tester.PcbDoc]
Generated File[P2_tester.TXT]
Generated File[P2_tester.DRL]
Generated File[P2_tester.LDP]
Generated File[P2_tester.DRR]
Files Generated : 4
Documents Printed : 0
Finished Output Generation At 08:59:54 On 29/08/2012
circuit_board/SVFC/PCB-Layout/SVFC.pcbdocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/SVFC.OutJob deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/SVFC.PrjPcb deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/SVFC.PrjPcbStructure deleted 100644 → 0
View file @ dd8a66b5
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=ClkGeneration.SchDoc|SymbolType=Normal|RawFileName=ClkGeneration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FmcConnector.SchDoc|SymbolType=Normal|RawFileName=FmcConnector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_FrontPannel|SchDesignator=U_FrontPannel|FileName=FrontPannel.SchDoc|SymbolType=Normal|RawFileName=FrontPannel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=VMEFMC.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=UTYDQHRM|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=ASWFUJMY|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=YBGBHHKV|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=HBHDXTNI|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG&CONFIG.SchDoc|SubPartUniqueId6=CQRRUQEQ|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=YPGBLSCB|SubPartDocPath7=SFPGA_power.SchDoc
circuit_board/SVFC/Schematics/AFPGA.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/AFPGA_power.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/ClkGeneration.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/DDR3.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/DDR3_2.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/FmcConnector.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/JTAG&CONFIG.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/PowerSupplies SCH ECO 2012-01-11 02-14-11.LOG deleted 100644 → 0
View file @ dd8a66b5
Change Component Designator: Old Designator=C5 New Designator=C?
Change Component Designator: Old Designator=C38 New Designator=C?
Change Component Designator: Old Designator=C67 New Designator=C?
Change Component Designator: Old Designator=C71 New Designator=C?
Change Component Designator: Old Designator=C72 New Designator=C?
Change Component Designator: Old Designator=C77 New Designator=C?
Change Component Designator: Old Designator=C84 New Designator=C?
Change Component Designator: Old Designator=C84 New Designator=C?
Change Component Designator: Old Designator=C84 New Designator=C?
Change Component Designator: Old Designator=C84 New Designator=C?
Change Component Designator: Old Designator=C84 New Designator=C?
Change Component Designator: Old Designator=C105 New Designator=C?
Change Component Designator: Old Designator=C105 New Designator=C?
Change Component Designator: Old Designator=C105 New Designator=C?
Change Component Designator: Old Designator=C105 New Designator=C?
Change Component Designator: Old Designator=C119 New Designator=C?
Change Component Designator: Old Designator=C128 New Designator=C?
Change Component Designator: Old Designator=C135 New Designator=C?
Change Component Designator: Old Designator=C136 New Designator=C?
Change Component Designator: Old Designator=C137 New Designator=C?
Change Component Designator: Old Designator=C138 New Designator=C?
Change Component Designator: Old Designator=C139 New Designator=C?
Change Component Designator: Old Designator=C148 New Designator=C?
Change Component Designator: Old Designator=C173 New Designator=C?
Change Component Designator: Old Designator=C175 New Designator=C?
Change Component Designator: Old Designator=C176 New Designator=C?
Change Component Designator: Old Designator=C179 New Designator=C?
Change Component Designator: Old Designator=C180 New Designator=C?
Change Component Designator: Old Designator=C181 New Designator=C?
Change Component Designator: Old Designator=C182 New Designator=C?
Change Component Designator: Old Designator=C185 New Designator=C?
Change Component Designator: Old Designator=C185 New Designator=C?
Change Component Designator: Old Designator=C185 New Designator=C?
Change Component Designator: Old Designator=C185 New Designator=C?
Change Component Designator: Old Designator=C206 New Designator=C?
Change Component Designator: Old Designator=C207 New Designator=C?
Change Component Designator: Old Designator=C208 New Designator=C?
Change Component Designator: Old Designator=C209 New Designator=C?
Change Component Designator: Old Designator=C210 New Designator=C?
Change Component Designator: Old Designator=C213 New Designator=C?
Change Component Designator: Old Designator=C214 New Designator=C?
Change Component Designator: Old Designator=C218 New Designator=C?
Change Component Designator: Old Designator=C263 New Designator=C?
Change Component Designator: Old Designator=C280 New Designator=C?
Change Component Designator: Old Designator=C386 New Designator=C?
Change Component Designator: Old Designator=C392 New Designator=C?
Change Component Designator: Old Designator=IC9 New Designator=IC?
Change Component Designator: Old Designator=IC11 New Designator=IC?
Change Component Designator: Old Designator=L12 New Designator=L?
Change Component Designator: Old Designator=L13 New Designator=L?
Change Component Designator: Old Designator=L15 New Designator=L?
Change Component Designator: Old Designator=L16 New Designator=L?
Change Component Designator: Old Designator=LD13 New Designator=LD?
Change Component Designator: Old Designator=LD13 New Designator=LD?
Change Component Designator: Old Designator=R15 New Designator=R?
Change Component Designator: Old Designator=R15 New Designator=R?
Change Component Designator: Old Designator=R187 New Designator=R?
Change Component Designator: Old Designator=R194 New Designator=R?
Change Component Designator: Old Designator=R197 New Designator=R?
Change Component Designator: Old Designator=R246 New Designator=R?
Change Component Designator: Old Designator=R247 New Designator=R?
Change Component Designator: Old Designator=T3 New Designator=T?
Change Component Designator: Old Designator=T3 New Designator=T?
Change Component Designator: Old Designator=T4 New Designator=T?
Change Component Designator: Old Designator=T4 New Designator=T?
Change Component Designator: Old Designator=T5 New Designator=T?
Change Component Designator: Old Designator=T5 New Designator=T?
Change Component Designator: Old Designator=T6 New Designator=T?
Change Component Designator: Old Designator=T6 New Designator=T?
Change Component Designator: Old Designator=T6 New Designator=T?
Change Component Designator: Old Designator=T6 New Designator=T?
circuit_board/SVFC/Schematics/PowerSupplies.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/SFPGA.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/SRAM.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This source diff could not be displayed because it is too large. You can view the blob instead.
circuit_board/SVFC/Schematics/USB.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/Schematics/VMEFMC.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/Schematics/VMEP0.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/Schematics/fpga_gtp.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/Schematics/fpga_power.SchDoc deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
circuit_board/SVFC/Schematics/fpga_power.SchDocPreview deleted 100644 → 0
View file @ dd8a66b5
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment