Skip to content

S
Simple VME FMC Carrier SVEC
Commit e98cf145 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

sfpga_bootloader: removed unused VME pins from top level entity, referenced… 

sfpga_bootloader: removed unused VME pins from top level entity, referenced general-cores repo as a submodule
parent 8d1fe311
Hide whitespace changes
Inline Side-by-side
Showing with 643 additions and 999 deletions
.gitmodules 0 → 100644
View file @ e98cf145
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
general-cores @ 4a5d41f1
Subproject commit 4a5d41f12798215521bf69900605d0fc8f6e4bf6
hdl/syn/sfpga_bootloader/Manifest.py
View file @ e98cf145
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
fetchto = "../../../ip_cores" fetchto = "../../ip_cores"
syn_device = "xc6slx9" syn_device = "xc6slx9"
syn_grade = "-2" syn_grade = "-2"
......
hdl/syn/sfpga_bootloader/svec_sfpga.xise
View file @ e98cf145
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/sfpga_bootloader/svec_sfpga_top.ucf
View file @ e98cf145
...@@ -7,29 +7,29 @@ ...@@ -7,29 +7,29 @@
#---------------------------------------- #----------------------------------------
NET "vme_write_n_i" LOC = B1; NET "vme_write_n_i" LOC = B1;
NET "vme_rst_n_i" LOC = G6; NET "vme_rst_n_i" LOC = G6;
NET "vme_retry_oe_o" LOC = D3; #NET "vme_retry_oe_o" LOC = D3;
NET "vme_retry_n_o" LOC = D1; #NET "vme_retry_n_o" LOC = D1;
NET "vme_lword_n_b" LOC = B3; NET "vme_lword_n_b" LOC = B3;
NET "vme_iackout_n_o" LOC = E4; #NET "vme_iackout_n_o" LOC = E4;
NET "vme_iackin_n_i" LOC = F6; #NET "vme_iackin_n_i" LOC = F6;
NET "vme_iack_n_i" LOC = E3; #NET "vme_iack_n_i" LOC = E3;
NET "vme_dtack_oe_o" LOC = C3; NET "vme_dtack_oe_o" LOC = C3;
NET "vme_dtack_n_o" LOC = C2; NET "vme_dtack_n_o" LOC = C2;
NET "vme_ds_n_i[1]" LOC = N9; NET "vme_ds_n_i[1]" LOC = N9;
NET "vme_ds_n_i[0]" LOC = P9; NET "vme_ds_n_i[0]" LOC = P9;
NET "vme_data_oe_n_o" LOC = K6; NET "vme_data_oe_n_o" LOC = K6;
NET "vme_data_dir_o" LOC = F4; NET "vme_data_dir_o" LOC = F4;
NET "vme_berr_o" LOC = C1; #NET "vme_berr_o" LOC = C1;
NET "vme_as_n_i" LOC = F5; NET "vme_as_n_i" LOC = F5;
NET "vme_addr_oe_n_o" LOC = K5; NET "vme_addr_oe_n_o" LOC = K5;
NET "vme_addr_dir_o" LOC = B2; NET "vme_addr_dir_o" LOC = B2;
NET "vme_irq_n_o[6]" LOC = C11; #NET "vme_irq_n_o[6]" LOC = C11;
NET "vme_irq_n_o[5]" LOC = C8; #NET "vme_irq_n_o[5]" LOC = C8;
NET "vme_irq_n_o[4]" LOC = D8; #NET "vme_irq_n_o[4]" LOC = D8;
NET "vme_irq_n_o[3]" LOC = C10; #NET "vme_irq_n_o[3]" LOC = C10;
NET "vme_irq_n_o[2]" LOC = E10; #NET "vme_irq_n_o[2]" LOC = E10;
NET "vme_irq_n_o[1]" LOC = E8; #NET "vme_irq_n_o[1]" LOC = E8;
NET "vme_irq_n_o[0]" LOC = E7; #NET "vme_irq_n_o[0]" LOC = E7;
NET "vme_ga_i[5]" LOC = A3; NET "vme_ga_i[5]" LOC = A3;
NET "vme_ga_i[4]" LOC = A10; NET "vme_ga_i[4]" LOC = A10;
NET "vme_ga_i[3]" LOC = B10; NET "vme_ga_i[3]" LOC = B10;
...@@ -122,29 +122,29 @@ NET "debugled_o[1]" LOC = L16; ...@@ -122,29 +122,29 @@ NET "debugled_o[1]" LOC = L16;
NET "vme_write_n_i" IOSTANDARD="LVCMOS33"; NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD="LVCMOS33"; NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33"; #NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD="LVCMOS33"; #NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33"; NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33"; #NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33"; #NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD="LVCMOS33"; #NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33"; NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33"; NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33"; NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33"; NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33"; NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD="LVCMOS33"; NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_berr_o" IOSTANDARD="LVCMOS33"; #NET "vme_berr_o" IOSTANDARD="LVCMOS33";
NET "vme_as_n_i" IOSTANDARD="LVCMOS33"; NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33"; NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33"; NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33"; #NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33"; NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
......
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
View file @ e98cf145
...@@ -30,7 +30,6 @@ entity svec_sfpga_top is ...@@ -30,7 +30,6 @@ entity svec_sfpga_top is
VME_AM_i : in std_logic_vector(5 downto 0); VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0); VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0); VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : inout std_logic := 'Z';
VME_DTACK_n_o : inout std_logic; VME_DTACK_n_o : inout std_logic;
VME_LWORD_n_b : inout std_logic; VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1); VME_ADDR_b : inout std_logic_vector(31 downto 1);
...@@ -44,14 +43,8 @@ entity svec_sfpga_top is ...@@ -44,14 +43,8 @@ entity svec_sfpga_top is
VME_ADDR_DIR_o : inout std_logic := 'Z'; VME_ADDR_DIR_o : inout std_logic := 'Z';
VME_ADDR_OE_N_o : inout std_logic := 'Z'; VME_ADDR_OE_N_o : inout std_logic := 'Z';
VME_RETRY_n_o : out std_logic := 'Z';
VME_RETRY_OE_o : out std_logic := 'Z';
VME_BBSY_n_i : in std_logic; VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0) := "ZZZZZZZ";
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic := 'Z';
------------------------------------------------------------------------- -------------------------------------------------------------------------
-- AFPGA boot signals -- AFPGA boot signals
------------------------------------------------------------------------- -------------------------------------------------------------------------
...@@ -319,7 +312,6 @@ begin ...@@ -319,7 +312,6 @@ begin
VME_DATA_b <= VME_DATA_o_int when (passive = '0' and VME_DATA_OE_N_int = '0' and vme_data_dir_int = '1') else (others => 'Z'); VME_DATA_b <= VME_DATA_o_int when (passive = '0' and VME_DATA_OE_N_int = '0' and vme_data_dir_int = '1') else (others => 'Z');
VME_ADDR_OE_N_o <= '0' when passive = '0' else 'Z'; VME_ADDR_OE_N_o <= '0' when passive = '0' else 'Z';
VME_ADDR_DIR_o <= '0' when passive = '0' else 'Z'; VME_ADDR_DIR_o <= '0' when passive = '0' else 'Z';
VME_BERR_o <= 'Z';
VME_LWORD_n_b <= 'Z'; VME_LWORD_n_b <= 'Z';
debugled_o(1) <= gpio(0); debugled_o(1) <= gpio(0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment