intitial commit (SVEC application FPGA bootloader)

f95e8aa0 · Tomasz Wlostowski · d74b6b17 · f95e8aa0 · f95e8aa0 · f95e8aa0
Commit f95e8aa0 authored Jun 19, 2012 by Tomasz Wlostowski
22 changed files
--- a/hdl/.gitignore
+++ b/hdl/.gitignore
+*~
+*#
+fifo_generator_v6_1
+testbench/svec_sfpga_top/sample_bitstream/
+*.*\#
+\#*
+.\#*
+*.*~
+syn/
+work
+*.wlf
+modelsim.ini
+transcript
+*.vstf
+*.bak
+*.vcd
+*.h
+doc/
+*.o
+*.bin
+*.elf
+Makefile
\ No newline at end of file
--- a/hdl/platform/Manifest.py
+++ b/hdl/platform/Manifest.py
+files =["chipscope_icon.ngc",  "chipscope_ila.ngc" ]
--- a/hdl/platform/chipscope_icon.ngc
+++ b/hdl/platform/chipscope_icon.ngc
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$0af5=6:2.Yi{g|inl9$4(5=8*/=6>;;12351=7898?7=>?459345>339::<95?0327?5638=1;<5>;;13341=799;?7=<?05930563392;<<5>4:33452<9?;;=6<;;32341=599::;6=9:HLLQQ<DGG^YCA>33483:4=3<2>;<=??;7qo|437|oml::8"209;0>>789;;75>?1923456799:;<h5MSBCM[VVFZ]KE:95MUGE;?GSTW@DMC<5L7:ABTQSUM;1HI<<4CIG@OZJNKLDXIRZVPD08GL2<KEA;:6MCK0:32>EKC;=;96MCK3Z;?FJL:Q;3<85LLJ;31>EKCH;<7NBDA0F13>EKCH;O8:5LLJC2@=3<KEAI=85LLJA21>EKCM;>7NBDDWa8GIMC^VNBZDJJ5:AOOC^?3JF@JU?7029@HW?<KFGFEYZJDc9@KKRUGE:7<3m4CNLWVJJ748:5o6M@NUPLH5:697i0OB@[RNN38449k2IDBY\@L1>27;e<KFD_^BB?<06=g>EHF]XD@=2>5?a8GJHSZFF;0<81c:ALJQTHD96:;3m4CNLWVJJ74825o6M@NUPLH5:617h0OB@[RNN3848d3JEEX_AC0=03:f=DGG^YCA>320<`?FII\[EG<1<=>b9@KKRUGE:7>>0l;BMMPWIK858?2n5LOOVQKI6;:<4h7NAATSMO49416j1HCCZ]OM2?628d3JEEX_AC0=0;:f=DGG^YCA>328<a?FII\[EG<1<1c:ALJQTHD968<3m4CNLWVJJ74:;5o6M@NUPLH5:4:7i0OB@[RNN38659k2IDBY\@L1>00;c<KFD_^BB?<2794;e<KFD_^BB?<27=f>EHF]XD@=2<>c9@KKRUGE:783l4CNLWVJJ74<4i7NAATSMO4909j2IDBY\@L1>4:g=DGG^YCA>38?`8GJHSZFF;040>4:ALV@Y@MGOYMYG@N^KMBJ1<K[OJXHJ>;E68@466:2NB86J]CJa8@WELWEEHMAQFc:FQGNYKGJKGSB=4FEA7?CBDM:1MHH=4FEP7?CBUM8h0J_AB #F\GIM%(]E+.GQLLJ #PLA6j2LYC@.-J^AOO'&SG)(OSNBD"!VJC7g<N[EF,/[PCMI!$QI'*CUH@F,/14234+6789:;<=>/pR0b?CTHE)(^SNBD"!VL$'SXKEA),<;?01,3456789:;,}]7;GPLIZHDN81L?6IAD09J6>O7:2C:>6G=2:K06>O3:2C>56GAIUQWEQC43@D]m6D[AF]@LDOI12@_MJQ[ERV6?OYDDB80@D<4LN48HJGCMM<0@BMDEE58HJANKHF?7A[[159OQQ433E__895CUU44?HS_KPUG96CZXG76?HS_N?i0Ald`rWgqwliik2Gbbb|Yesqjkk4<F9=0BHZXOSI5?KIDD@Z<7CABESEF5>I03F$?<iQC1:R7?UGU\;l0\H\FOE"!NZEKC+*8<=>?.123456'xZ*CEJF/51,345678)/j7]GA_CWPMA^e3YCESO[\N@OF=>VLWAF^XCC9;QQGKKC63X;0^85]ERGW3>TRF]OXX<5\3:QFH0=T@@L_:6]@USAF2>USI]_X?6ZLK29W@L5<\ME37YK]MHLBH6=SAN20XDCJSQG@7>RJ[>1_B@QAEU;8PVYCW]ETF55[S^H\GIM>3]YTFRZ@_E;8PVYRW]ETF45[S^W\PJYR<2^R\H=k;T2,QZODGG%BSTK\_CQ@EK(RWKY$ER]9.HQZJ+OX]ZOT_BH[BRABJZCV8'_TN^;k;T2,QZODGG%BSTK\_CQ@EK(RWKY$ER[\E^QLBQDTKHDTI\>!I^WPAZ^T\V^HGRY@RJCQKPHCWL[:"XQFCNL\FVEFFVH^JJ<9;T2,QZODGG%BSTK\_CQ@EK(RWKY$eI\LK^NLGDJ5j2_;#XQFCNL,QZEJL&MTXL\HEUY24X(NWGO;"XQ[ASEFP7d<]9%^SDM@N.W\GHB(OV^J^JK[[03^*LYIM9$^SYO]GDV1f>S7'\UBOB@ U^AN@*AX\HXLIYU>2\,J[KC7&\U_M_IJT3`8Q5)RW@IDB"[PCLF,CZRFZNO_W<=R.H]MA5(RW]KYKHZ=b:W3+PYNKFD$YRMBD.E\PDT@M]Q:8P F_OG3*PYSI[MNX?l4U1-V[LEHF&_TO@J G^VBVBCSS8?V"DQJQ1,V[QGUOL^9m6[?/T]JGJH(]VIFH"IPT@PDAQ]1U'CTBH>!U^VBVBCS:h1^<"[PIBMM+PYDEM%LSYO]GDVX3X(NWGO;"XQ[ASEFP7g<]9%^SDM@N.W\GHB(OV^J^JK[[9_-MZHB8'_TXL\HEU0b?P6(]VCHCC!Z_BOG+BYSI[MNXV7R.H]MA5(RW]KYKHZ=c:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^6Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_46Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_47Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_44Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_45Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_42Z&\UGYY<k;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_43Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_4[)]VF^X?m4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX6X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMNIDHCWZOG#D:!FHY0Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ6^*PYK]]8h7X> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[4_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@MLCM@ZUBD&C?"KGT6\,V[ISS:j1^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU8]/W\HPR5k2_;#XQFCNL,QZEJL&_TOBCBAOF\W@J(A=$MEV6R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC@CNNE]PAI)N<'LBW4S!U^NVP7e<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP<P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:<P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:=P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:>P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:?P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:8P Z_MWW6a=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:9P Z_MWW6f=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR8V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS:W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\<T$^SA[[2b9V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]2U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJTBW@NT_HB I5,EM^0Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KWCXAMUXIA!F4/DJ_2[)]VF^X?m4U1-V[LEHF&_TO@J U^ALV@YNLVYN@"G;.GKX<X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMQAZOCWZOG#D:!FHY:Y+SXD\^:;6[?/T]JGJH(]VIFH"[PSDN\j4d<]9%^SDM@N.W\GHB(]V^J^JK[_BG22>S7'\UBOB@ U^AN@*oTMEUe=o5Z0.W\MFII'\UHAI!fT@PDAQ:687;i7X> U^K@KK)RWJGO#dZNRFGW84799h1^<"[PIBMM+PYDEM%bXL\HEU>;:4g<]9%^SDM@N.W\GHB(a]KYKHZ39?3b?P6(]VCHCC!Z_BOG+lRFZNO_SNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^6Z&\UCOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_5[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX55[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX55[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX54[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX54[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX57[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX57[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX56[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX56[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX51[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX51[)]VFHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX50[)]VBHI?j4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX50[)]VFHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX5X(RWAIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY2Y+SXDJO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ0^*PYOKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[3_-QZJDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT3\,V[MEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU<]/W\HFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV:R.T]KG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW9S!U^N@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP9P Z_IAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ>Q#[PLBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR<V"XQGCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS?W%YRBLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\?T$^SEMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]0U'_T@NK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^>Z&\UCOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_=[)]VFHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX=X(RWAIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY:Y+SXDJO:i6[?/T]JGJH(]VI_^AQ@UU-V[FKCO[Z;=h5Z0.W\MFII'\UHX_BPOTV,QZEJLNX[=??4U1-V[LEHF&_TOY\C_NWW+PYCI]KTZLBFD3:8Q5)RW@IDB"[PCUPO[JSS'`IDA@OAD^EQTZUBD5:5>55Z0.W\MFII'\UHX_BPOTV,mFIJEHDOSJ\__RGO848582_;#XQFCNL,QZESZEUDYY!fD@VB[SGKAM8:7X> U^K@KK)RWZ^JX"HPSUCW_5[)]VY_MY<>;T2,QZODGG%^S^ZNT.D\WQGSS8W%YR][AU02?P6(]VCHCC!Z_RVBP*@X[]K_W?S!U^QWEQ463\:$YRGLOO-V[VRF\&LT_YO[[2_-QZUSI];j7X> U^K@KK)RWZ^JX"[PCLFDVU66l2_;#XQFCNL,QZUSI]%^SIO[A^TBHLB6i2_;#XQFCNL,QZUSI]%^S^ZNTBOG5f=R8&_TENAA/T]PPDR(]VY_MYMBD^l15>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.AJ848592_;#XQFCNL,QZUSI]%^S^ZNT^AMP*EN4;49=6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&IB0>0=1:W3+PYNKFD$YR][AU-V[VRF\VIEX"MF<5<15>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.AJ808582_;#XQFCNL,QZUSI]%^S^ZNT^AMP*B;878;7X> U^K@KK)RWZ^JX"[PSUCW[FHS'M6:2?>4U1-V[LEHF&_T_YO[/T]PPDRXKG^$H1<1219V4*SXAJEE#XQ\T@V,QZUSI]UHBY!K<2<14>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.F?0;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+A:26;i0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR:V"J`G.T]NQ]E^:>1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S9W%YRHKRD05?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY3Y+SXD\^946[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP<P Z_YMQG\4d3\:$YRGLOO-V[VRF\&_T_YO[_BLW+B]6U'MeD#[PMTZ@]71<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^7Z&\UMH_K=6:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT1\,V[ISS:11^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S8W%YRV@RB[1g>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.EX6X(@fA$^S@[WCX04?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY1Y+SXNMXN>;5Z0.W\MFII'\UXXLZ U^QWEQYDF]%LW?S!U^NVP7><]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^4Z&\USC_MV2b9V4*SXAJEE#XQ\T@V,QZUSI]UHBY!H[2_-CkN)]VG^TNW=7:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT3\,V[CBUM;<0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR9V"XQCUU0;?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY0Y+SXPFXHU?m4U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV:R.FlK*PYJ]QIR>:5Z0.W\MFII'\UXXLZ U^QWEQYDF]%LW9S!U^DGV@413\:$YRGLOO-V[VRF\&_T_YO[_BLW+B]3U'_T@XZ=8:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT4\,V[]IUKP8<7X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ>Q#[PFEPF63=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_0[)]VF^X?64U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV;R.T][KWE^:91^<"[PIBMM+PYT\H^$YR][AU]@JQ)T4949<6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&Y7=3<?;T2,QZODGG%^S^ZNT.W\WQGSWJD_#^2=>328Q5)RW@IDB"[PSUCW+PYT\H^TOCZ S=1=65=R8&_TENAA/T]PPDR(]VY_MYQLNU-P818582_;#XQFCNL,QZUSI]%^S^ZNT^AMP*U;=7;h7X> U^K@KK)RWZ^JX"[PSUCW[MO@@8h0Y=!Z_HALJ*SX[]K_#XQ\T@V\HJQ6>2_;#XQFCNL,QZUSI]%^SYJ@1c9V4*SXAJEE#XQ\T@V,QZRCGVdnty?j;T2,QZODGG%^S^ZNT.k@IAY@ZY:T_HB>c:W3+PYNKFD$YR][AU-j@DRFW_KGEI?6;T2,QZODGG%^S^ZNT.kPPDR;87;27X> U^K@KK)RWZ^JX"g\T@V?5;7>3\:$YRGLOO-V[VRF\&cXXLZ32?3:?P6(]VCHCC!Z_RVBP*oT\H^7?3?l;T2,QZODGG%^S^ZNT.kPPDRDEMUHI<k4U1-V[LEHF&_T_YO[/hQWEQEJLVINSc?k;T2,QZODGG%^S^ZNT.kPPDRXKG^7<3?k;T2,QZODGG%^S^ZNT.kPPDRXKG^7=3?k;T2,QZODGG%^S^ZNT.kPPDRXKG^7>3?k;T2,QZODGG%^S^ZNT.kPPDRXKG^7?3?k;T2,QZODGG%^S^ZNT.kPPDRXKG^783?k;T2,QZODGG%^S^ZNT.kPPDRXKG^793?m;T2,QZODGG%^S^ZNT.kPPDRX@@MC=l5Z0.W\MFII'\UXXLZ iRVBPZJH_8k0Y=!Z_HALJ*SX[]K_#dZKO^lf|q4e3\:$YRGLOO-V[V_IK&MT_T@L_VMQ@^6Z&@UEI= Z_GFQ6g=R8&_TENAA/T]P]KE(OVYRBNQXOSFX5X(NWGO;"XQIDS0a?P6(]VCHCC!Z_R[MG*AX[PDHSZA]DZ0^*LYIM9$^SKJ]2c9V4*SXAJEE#XQ\YOA,CZU^FJU\C_JT3\,J[KC7&\UMH_<m;T2,QZODGG%^S^WAC.E\W\HDW^EYHV:R.H]MA5(RWONY>o5Z0.W\MFII'\UXUCM G^QZJFYPG[NP9P F_OG3*PYAL[8i7X> U^K@KK)RWZSEO"IPSXL@[RIULR<V"DQJQ1,V[CBU9k1^<"[PIBMM+PYTQGI$YRI@T^QZJF7c3\:$YRGLOO-V[V_IK&_TKBZPSXL@[M7c3\:$YRGLOO-V[V_IK&_TKBZPSXL@[I703\:$YRGLOO-V[V_IK&_T_T@L1d9V4*SXAJEE#XQ\YOA,QZoCI]KTO@JPn0a8Q5)RW@IDB"[PSXL@+lBF\HUHAIQa1`9V4*SXAJEE#XQ\YOA,mBISWZSEO<h4U1-V[LEHF&_T_T@L/hELPZU^FJUCEJF>e:W3+PYNKFD$YR]VNB-jCJRX[PDHSAAX1d9V4*SXAJEE#XQ\YOA,mV_IKV]D^I2?>0g8Q5)RW@IDB"[PSXL@+lU^FJU\C_J31?3f?P6(]VCHCC!Z_R[MG*oTQGIT[B\K<3<2a>S7'\UBOB@ U^QZJF)n[PDHSZA]D=1=5`=R8&_TENAA/T]P]KE(aZSEORY@RE>7:4c<]9%^SDM@N.W\W\HD'`YRBNQXOSF?1;7b3\:$YRGLOO-V[V_IK&cXUCMPWNPG8386;2_;#XQFCNL,QZRCAVxnk>>4U1-V[LEHF&_TXIAPMTZ,QZETWD_S#D:!U^OV\40(EdsSB?>129V4*SXAJEE#XQ[DN]qab723\:$YRGLOO-V[lBF\HUHAI?8;T2,QZODGG%^SdJNT@]@IAYi9;1^<"[PIBMM+PYn[LFTb<74U1-V[LEHF&cHC@CNNE]DVU:76830Y=!Z_HALJ*oDGDGJBIQHRQ>2:4?<]9%^SDM@N.k@KHKFFMUXIA2?>0c8Q5)RW@IDB"gLOLOBJAYTME6:<3?n;T2,QZODGG%bOBCBAOF\W@J;984:m6[?/T]JGJH(aJEFAL@K_RGO84499h1^<"[PIBMM+lEHEDKEHR]JL=30:4g<]9%^SDM@N.k@KHKFFMUXIA2>4?3b?P6(]VCHCC!fCNONEKBX[LF7=80>9:W3+PYNKFD$eNABM@LG[VCK484:56[?/T]JGJH(aJEFAL@K_RGO878612_;#XQFCNL,mFIJEHDOS^KC<2<2=>S7'\UBOB@ iBMNIDHCWZOG090>9:W3+PYNKFD$eNABM@LG[VCK4<4:56[?/T]JGJH(aJEFAL@K_RGO838612_;#XQFCNL,mFIJEHDOS^KC<6<2=>S7'\UBOB@ iBMNIDHCWZOG050>9:W3+PYNKFD$eNABM@LG[VCK404:96[?/T]JGJH(aJEYIRGK<1<21>S7'\UBOB@ iBMQAZOC484:96[?/T]JGJH(aJEYIRGK<3<21>S7'\UBOB@ iBMQAZOC4:4:56[?/T]JGJH(aJEYIRGK_RGO8586i2_;#XQFCNL,mFIUMVCOS^KC<07=56=R8&_TENAA/hFBPDYDEM;>7X> U^K@KK)nLH^JSNCK_od8Q5)RW@IDB"gKRBIf?P6(]VCHCC!fSDN24>S7'\UBOB@ iRGO[k`<]9%^SDM@N.kP]KEb3\:$YRGLOO-jPAOb3\:$YRGLOO-jPAI6>2_;#XQFCNL,mQBHW_OH0<;1129V4*SXAJEE#dZKO^lf|qb<]9%b_EGIT^MVP`=R8&c^\IO[E^MVP3=RXMK_In5ZSDP\RLUNJEO=7XQMUGE6?PYDDB90ZNM6;WKFSZR^XL;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@?0TB\LY79[WQJNJ>1S_YQHNE58\VRX^JIi7UQLOSG\MK@H>2RonRGkf:ZglZVuad\n~~g`n028\akXEh`d~[k}shmm55=_ldUFeca}Vdppmjh43Qy?o5P_^ZOJHYXW9UTSX> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[06^*PYK]]9h7RQPXMLN[ZY68VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT13_-QZJDM:i0SRQWLOO\[Z76WVU^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU>3\,V[IEB;j1TSRVCNL]\[44XWV_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV?;]/W\HFC4k2UTSUBAM^]\56YXW\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW<;R.T]OG@5e3VUTTA@B_^]20ZYX]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP=P Z_MAF7g=XWVRGB@QP_07\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR8V"XQCCD1a?ZYXPEDFSRQ>6^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\;T$^SAMJ3c9\[Z^KFDUTS<9P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^2Z&\UGOH=m;^]\\IHJWVU:4RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX1X(RWEIN?o5P_^ZOJHYXW83TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ4^*PYKKL9i7RQPXMLN[ZY6WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU>2\,V[ISS;k1TSRVCNL]\[76XWV_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV9R.T]OG@5e3VUTTA@B_^]15ZYX]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP4P Z_MAF7g=XWVRGB@QP_30\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR3V"XQCCD0g?ZYXPEDFSRQ=3^]\Q5)RW@IDB"[PCUPO[JSS'\UHAII]P113?ZYXPEDFSRQ=4^]\Q5)RW@IDB"[PCUPO[JSS'\UOMYOPV@NJ@7g<WVUS@CCP_^06[ZYR8&_TENAA/T]P]KE(]VMDXR]VNB1a?ZYXPEDFSRQ=_^]V4*SXAJEE#XQLME-V[FIJEHDOS^KC/H6-BL]68T$^SA[[3`9\[Z^KFDUTS>QP_T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_=[)]VF^X>o4_^][HKKXWV>TSR[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ4^*PYK]]9j7RQPXMLN[ZY2WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU;]/W\HPR4i2UTSUBAM^]\2ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP>P Z_MWW7d=XWVRGB@QP_6]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS9W%YRBLE2`8[ZY_DGGTSR6P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^77U'_T@NK<b:]\[]JIEVUT5RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX54[)]VFHIi5nsxl`[acdgmoy56o|yoa\ip~b3jbb|~m`pd]jgjh5n2ice}}loqg\mfii$jbb|~m`pd]jgjhX~8U;9Ro#NNLF(KIIM:>m7nffpralt`Ynkfd'oegsbmsaZodggU}=R>:_`.xgZstmVdn{R~nrrgq95*dWqidSag|t<LvigcuWJeexac_Qmqpv;63\ynSHv{_Cq`ek;aieyn7X}jr^Q`ekYD`hce1X]JR09FjddkmV@mjQMuge>pwsb3\ynSX`zsdf\Fveff4lj`~k4Urg\Wj`sjzijb0hnlrg/gZ~cmchikobim{>wugu|hd= nQlosg\p|vb58&hS`oeos]uawungg7:?!mPmhllvZpbzzcdb0?#c^`vmibXzl|bdaa=1.`[fiumVgjfb|Pvdp>5)eXkfxnS`gaos]uaw;5$jUhckPmhllvZgkxakTzh|296.`[h``W`n6=!mPurg\fp`u59&hSx}j_rkn95*dW|ynS~aitcq`ek;7$jU{mzPieal``Yumncxxh|20-a\qvcXb}klSo{ig<3/gZhreVidby|`l^rlvqu:9%iTy~kPcnlwvjj758&hSx}j_bmmpwik94:'oR{|e^aljqthd;7; nQzsd]`kkruge96<!mPurg\gjhszff?1="l_tqf[fii|{eg90>#c^wpaZehf}xd`;3?,b]vw`Ydgg~yca920-a\qvcXkfd~bb7=1.`[pubWjeexac9<2/gZstmVidby|`l02>4)eX}zoTob`{rnn2586+kVxiRm`nuplh44:8%iTy~kPcnlwvjj6;4:'oR{|e^aljqthd8>6<!mPurg\a}rXjzijb0>#c^wpaZsi}zooSo}lao?3(fYr{lUsyQ{cj]tkwmfzfeh0?#c^g{ehvkmVnndia=gcow`*dW|yn~R}lao]`ldoi58&v=o5lhhrpgjvbW`idbRZFMDQSAFYIKO997nffpralt`YnkfdTz<Q?5^c/$]okagr+OB\J Fgmawgsg{*:?#?8;bmvjqcu>2ixS`{w8:ap[hs9?k0enaa_cq`ek`<ajeeSo}lao]aqca6k2chccQmsbcm[gsaoV^BAH]_EB][WQ`<ajeeSnck_eg`kac>3`idbRm`rdf8mfiiWj~y`Raztc9jgjhX{}ky~74ibmm[vik11eknlzimf~DEv39<1KLu?md;D90?7|[<o1=l>5918277bc9;09=?78{o3:a?7<f83m6;5+18a95<0<uZ9<6<o?:829564cl881><<68:Q4b?7dl3;1=><kd009644f82Y8;7?ld;39564cl881><<n3:f2fa<7280:w^;j:0c3><6=9:8oh<<5200:3>pS1o0;6<4>:6dxW0c=9h:15=4>33fg57<59;3<7)?65;:2?S7>l38py5751:w;e?6<u-396<74b0`g>5<5<3226:htH0;2?!gb28ho7W?i:0y22?{#90h1=n?4$3195gc<,<n1=oh4+4494?">=3??7c7;:328?.32290/584:4:l:0?6<3"?86=4+94860>h><3;07&;=:18'=0<2<2d287<4;*72>5<#1<0>86`64;18?.37290/584:4:l:0?2<3">m6=4+94860>h><3?07&:k:18'=0<2<2d28784;*6`>5<#1<0>86`64;58?.2e290/584:4:l:0?><3">j6=4+94860>h><3307&:6:18'=0<2<2d287o4;*6;>5<#1<0>86`64;`8?.20290/584:4:l:0?e<3">=6=4+94860>h><3n07&:::18'=0<2<2d287k4;*67>5<#1<0>86`64;d8?.25290/584:4:l:0?7732!?=7>5$87911=i1=0:=65$4183>!?22<>0b4:51398/6`=83.297;;;o;7>45<3"9n6=4+94860>h><3;?76%<d;29 <3===1e594>5:9(7f<72-3>68:4n86953=<#:h1<7*65;77?k?328=07&=n:18'=0<2<2d287?7;:)0=?6=,0?1995a9582=>=,=j0;6)7::468j<2=9h10'8l50;&:1?333g3?6<l4;*7b>5<#1<0>86`64;3`?>-213:1(4;5559m=1<6l21 954?:%;6>02<f0>1=h54+4594?">=3??7c7;:0d8?.2b290/584:4:l:0?4632!??7>5$87911=i1=09>65$3983>!?22<>0b4:52298f4?f290:6=4?{%cf>4?33A;246F>909l=4<722wi=4750;394?6|,ho1;=5G18:8L4?63f<m6=44}cce>5<e290;w)oj:0f8L4??3A;2=6`8a;38j2d=82e2i7>5;nc1>5<<g0h1<75`a083>>i6190;66a6a;29?j?c2900el=50;9l64<722ej;7>5;n41>5<<ukh;6=4=:381M7>92.ji7?l6:k57?6=3f<?6=44b0;1>5<5290;w)oj:0g8L4??3A;2=6g81;29?j>a2900qo?l7;294?6=8rB:5<5+ad8b2>Jf>3;p(lo5929~yv042909wS8<;<3:6?163ty=87>52z\50>;61;03j6srb04b>5<5290;w)oj:6;8L4??3A;2=6g81;29?j>a2900qo?9b;296?6=8r.ji796;I3:<>N6181b;<4?::m;b?6=3th::54?:583>5}#il0=;6F>999K5<7<,>21>6g=0;29?l452900e8h50;9l==<722wi=;850;694?6|,ho1::5G18:8L4?63-=36?5f2183>>o5:3:17d;i:188k<>=831vn<86:187>5<7s-kn6;;4H0;;?M7>92.<47<4i3294?=n;?0;66g:f;29?j??2900qojl:181>5<7s-kn6:74H0;;?M7>92c<=7>5;n:e>5<<ukno6=4<:183!gb2190D<77;I3:5>"003;<7)79:0`1?l152900e:=50;9l<c<722win54?:483>5}#il0=:6F>999K5<7<,>21>6g=0;29?l452900e>850;9j1c<722e247>5;|`a=?6==3:1<v*ne;45?M7>02B:5<5+7981?l472900e?<50;9j73<722c>j7>5;n;;>5<<ukhj6=4::183!gb2?<0D<77;I3:5>"00380e?>50;9j67<722c8:7>5;h7e>5<<g021<75rbc`94?3=83:p(lk5679K5<><@83:7)97:39j65<722c9>7>5;h15>5<<a<l1<75`9983>>{ej;0;684?:1y'e`<1>2B:555G1838 2>=:2c9<7>5;h01>5<<a:<1<75f5g83>>i>03:17plm3;291?6=8r.ji789;I3:<>N6181/;54=;h03>5<<a;81<75f3783>>o2n3:17b77:188ygd3290>6=4?{%cf>30<@8337E?61:&4<?4<a;:1<75f2383>>o4>3:17d;i:188k<>=831vno;50;794?6|,ho1:;5G18:8L4?63-=36?5f2183>>o5:3:17d=9:188m0`=831d554?::af3<72<0;6=u+ad852>N6111C=4?4$6:96>o583:17d<=:188m60=831b9k4?::m:<?6=3thi;7>55;294~"fm3<=7E?68:J2=4=#?1097d<?:188m74=831b?;4?::k6b?6=3f336=44}ca1>5<2290;w)oj:968L4??3A;2=6*88;3a?!?128k:7d9=:188m25=831b;94?::k41?6=3f2m6=44}ca2>5<2290;w)oj:968L4??3A;2=6*88;3;?!?128k:7d9=:188m25=831b;94?::k41?6=3f2m6=44}ca3>5<2290;w)oj:968L4??3A;2=6*88;37?!?128kh7d9=:188m25=831b;94?::k41?6=3f2m6=44}c`e>5<2290;w)oj:968L4??3A;2=6*88;32?!?128kh7d9=:188m25=831b;94?::k41?6=3f2m6=44}c`f>5<2290;w)oj:968L4??3A;2=6*88;d8 <0=9k90e:<50;9j36<722c<87>5;h56>5<<g1l1<75rbcf94?3=83:p(lk5859K5<><@83:7)97:d9'=3<6j:1b;?4?::k47?6=3`=?6=44i6794?=h0o0;66smcc83>0<729q/mh474:J2===O90;0(:65d:&:2?7e<2c<>7>5;h50>5<<a>>1<75f7483>>i?n3:17plla;291?6=8r.ji76;;I3:<>N6181/;54m;%;5>4d33`=96=44i6194?=n?=0;66g85;29?j>a2900qom6:186>5<7s-kn65:4H0;;?M7>92.<47o4$8495g3<a>81<75f7283>>o0<3:17d9::188k=`=831vnn650;794?6|,ho1495G18:8L4?63-=3645+9782f0=n?;0;66g83;29?l132900e:;50;9l<c<722wio:4?:483>5}#il0386F>999K5<7<,>2146*66;3a2>o0:3:17d9<:188m22=831b;84?::m;b?6=3thh:7>55;294~"fm32?7E?68:J2=4=#?10<7)79:0`5?l152900e:=50;9j31<722c<97>5;n:e>5<<uki>6=4::183!gb21>0D<77;I3:5>"003<0(4851c58m24=831b;>4?::k40?6=3`=>6=44o9d94?=zjj>1<7;50;2x dc=0=1C=464H0;2?!1?2<1/5;4>b69j37<722c<?7>5;h57>5<<a>?1<75`8g83>>{ek:0;684?:1y'e`<?<2B:555G1838 2>=<2c<>7>5;h50>5<<a>>1<75f7483>>i?n3:17plmc;291?6=8r.ji76;;I3:<>N6181/;54<;h51>5<<a>91<75f7583>>o0=3:17b6i:188ygb5290>6=4?{%cf>=2<@8337E?61:&4<?7e3`=96=44i6194?=n?=0;66g85;29?j>a2900qoj>:186>5<7s-kn65:4H0;;?M7>92.<47?7;h51>5<<a>91<75f7583>>o0=3:17b6i:188ygb7290>6=4?{%cf>=2<@8337E?61:&4<?733`=96=44i6194?=n?=0;66g85;29?j>a2900qomi:186>5<7s-kn65:4H0;;?M7>92.<47?>;h51>5<<a>91<75f7583>>o0=3:17b6i:188ygeb290>6=4?{%cf>=2<@8337E?61:&4<?`<a>81<75f7283>>o0<3:17d9::188k=`=831vnnj50;794?6|,ho1495G18:8L4?63-=36h5f7383>>o0;3:17d9;:188m23=831d4k4?::a`g<72<0;6=u+ad8;0>N6111C=4?4$6:9`>o0:3:17d9<:188m22=831b;84?::m;b?6=3thom7>55;294~"fm32?7E?68:J2=4=#?10i7d9=:188m25=831b;94?::k41?6=3f2m6=44}cf:>5<2290;w)oj:968L4??3A;2=6*88;c8m24=831b;>4?::k40?6=3`=>6=44o9d94?=zjm21<7;50;2x dc=0=1C=464H0;2?!1?201b;?4?::k47?6=3`=?6=44i6794?=h0o0;66smd683>0<729q/mh474:J2===O90;0(:658:k46?6=3`=86=44i6694?=n?<0;66a7f;29?xdc>3:197>50z&ba?>33A;246F>909'3=<03`=96=44i6194?=n?=0;66g85;29?j>a2900qoj::186>5<7s-kn65:4H0;;?M7>92.<4784i6094?=n?:0;66g84;29?l122900c5h50;9~fa2=83?1<7>t$`g9<1=O9020D<7>;%5;>0=n?;0;66g83;29?l132900e:;50;9l<c<722wih>4?:483>5}#il0386F>999K5<7<,>2186g82;29?l142900e::50;9j30<722e3j7>5;|``g?6==3:1<v*ne;:7?M7>02B:5<5+7980?l152900e:=50;9j31<722c<97>5;n:e>5<<uko?6=4::183!gb21>0D<77;I3:5>"003;i7)79:0`;?l152900e:=50;9j31<722c<97>5;n:e>5<<uko>6=4::183!gb21>0D<77;I3:5>"003;i7)79:0`;?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl96=4::183!gb21>0D<77;I3:5>"003;i7)79:0c5?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl86=4::183!gb21>0D<77;I3:5>"003;i7)79:0c5?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl?6=4::183!gb21>0D<77;I3:5>"003;i7)79:0c4?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl>6=4::183!gb21>0D<77;I3:5>"003;i7)79:0c4?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl=6=4::183!gb21>0D<77;I3:5>"003;i7)79:0c;?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl<6=4::183!gb21>0D<77;I3:5>"003;i7)79:0c;?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl36=4::183!gb21>0D<77;I3:5>"003;i7)79:0c:?l152900e:=50;9j31<722c<97>5;n:e>5<<ukl26=4::183!gb21>0D<77;I3:5>"003;i7)79:0c:?l152900e:=50;9j31<722c<97>5;n:e>5<<uklj6=4::183!gb21>0D<77;I3:5>"003;i7)79:0cb?l152900e:=50;9j31<722c<97>5;n:e>5<<ukli6=4::183!gb21>0D<77;I3:5>"003;i7)79:0cb?l152900e:=50;9j31<722c<97>5;n:e>5<<uklh6=4::183!gb21>0D<77;I3:5>"003;i7)79:0ca?l152900e:=50;9j31<722c<97>5;n:e>5<<uklo6=4::183!gb21>0D<77;I3:5>"003;i7)79:0ca?l152900e:=50;9j31<722c<97>5;n:e>5<<ukln6=4::183!gb21>0D<77;I3:5>"003;i7)79:0cg?l152900e:=50;9j31<722c<97>5;n:e>5<<uklm6=4::183!gb21>0D<77;I3:5>"003;i7)79:0cg?l152900e:=50;9j31<722c<97>5;n:e>5<<uk;;<7>55;294~"fm32?7E?68:J2=4=#?10:n6*66;3ba>o0:3:17d9<:188m22=831b;84?::m;b?6=3th:<<4?:483>5}#il0386F>999K5<7<,>21=o5+9782e`=n?;0;66g83;29?l132900e:;50;9l<c<722wi==<50;794?6|,ho1495G18:8L4?63-=36<l4$8495d`<a>81<75f7283>>o0<3:17d9::188k=`=831vn<><:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4ga3`=96=44i6194?=n?=0;66g85;29?j>a2900qok9:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4d>3`=96=44i6194?=n?=0;66g85;29?j>a2900qok8:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4d>3`=96=44i6194?=n?=0;66g85;29?j>a2900qok7:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4df3`=96=44i6194?=n?=0;66g85;29?j>a2900qok6:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4df3`=96=44i6194?=n?=0;66g85;29?j>a2900qokn:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g53`=96=44i6194?=n?=0;66g85;29?j>a2900qokm:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g53`=96=44i6194?=n?=0;66g85;29?j>a2900qokl:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g43`=96=44i6194?=n?=0;66g85;29?j>a2900qokk:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g43`=96=44i6194?=n?=0;66g85;29?j>a2900qokj:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g33`=96=44i6194?=n?=0;66g85;29?j>a2900qoki:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g33`=96=44i6194?=n?=0;66g85;29?j>a2900qoh?:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g23`=96=44i6194?=n?=0;66g85;29?j>a2900qoh>:186>5<7s-kn65:4H0;;?M7>92.<47?m;%;5>4g23`=96=44i6194?=n?=0;66g85;29?j>a2900qo??5;297?6=8r.ji76<;I3:<>N6181/;54>3:&:2?7e82c<>7>5;h50>5<<g1l1<75rb027>5<4290;w)oj:918L4??3A;2=6*88;33?!?128h;7d9=:188m25=831d4k4?::a550=8391<7>t$`g9<6=O9020D<7>;%5;>4g<,0<1=o?4i6094?=n?:0;66a7f;29?xd6;m0;694?:1y'e`<?02B:555G1838m24=831b;>4?::k:g?6=3f2m6=44}c30f?6=<3:1<v*ne;:4?M7>02B:5<5f7383>>o0;3:17d7l:188k=`=831vn<=n:187>5<7s-kn6594H0;;?M7>92c<>7>5;h50>5<<a0i1<75`8g83>>{e99k1<7;50;2x dc=0=1C=464H0;2?!1?2j1b;?4?::k47?6=3`=?6=44i6794?=h0o0;66sm11`94?3=83:p(lk5859K5<><@83:7)97:728m24=831b;>4?::k40?6=3`=>6=44o9d94?=zj8:h6=4::183!gb21>0D<77;I3:5>"003;>7d9=:188m25=831b;94?::k41?6=3f2m6=44}c33`?6==3:1<v*ne;:7?M7>02B:5<5+79826>o0:3:17d9<:188m22=831b;84?::m;b?6=3th:=<4?:383>5}#il0<56F>999K5<7<a>;1<75`8g83>>{e99o1<7=50;2x dc=0:1C=464H0;2?!1?28:0e:<50;9j36<722e3j7>5;|`255<72<0;6=u+ad8;0>N6111C=4?4$6:95g=n?;0;66g83;29?l132900e:;50;9l<c<722wi==h50;194?6|,ho14>5G18:8L4?63-=36<o4$8495g7<a>81<75f7283>>i?n3:17pl>3b83>1<729q/mh497:J2===O90;0(:652:k14?6=3`896=44i4d94?=h110;66sm13294?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f47c290?6=4?{%cf>=0<@8337E?61:k10?6=3`<:6=44i8a94?=h?l0;66sm13694?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f446290?6=4?{%cf>=0<@8337E?61:k10?6=3`<:6=44i8a94?=h?l0;66sm13:94?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f442290?6=4?{%cf>=0<@8337E?61:k10?6=3`<:6=44i8a94?=h?l0;66sm13a94?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f44>290?6=4?{%cf>=0<@8337E?61:k10?6=3`<:6=44i8a94?=h?l0;66sm12294?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f44c290?6=4?{%cf>=0<@8337E?61:k10?6=3`<:6=44i8a94?=h?l0;66sm12194?5=83:p(lk51858L4??3A;2=6g=4;29?l1c2900c5h50;9~f47a29096=4?{%cf>=4<@8337E?61:&4<?743`=96=44o9d94?=zj8886=4=:183!gb2180D<77;I3:5>"003;87d9=:188k=`=831vn<<8:181>5<7s-kn65<4H0;;?M7>92.<47?<;h51>5<<g1l1<75rb00a>5<5290;w)oj:908L4??3A;2=6*88;30?l152900c5h50;9~f44a29096=4?{%cf>=4<@8337E?61:&4<?743`=96=44o9d94?=zj8996=4=:183!gb2180D<77;I3:5>"003;87d9=:188k=`=831vn<?j:186>5<7s-kn6;74H0;;?M7>92.<47<4i3294?=n:;0;66g:f;29?l?>2900c4650;9~f445290>6=4?{%cf>3?<@8337E?61:&4<?4<a;:1<75f2383>>o2n3:17d76:188k<>=831vn<<9:186>5<7s-kn6;74H0;;?M7>92.<47<4i3294?=n:;0;66g:f;29?l?>2900c4650;9~f44f290>6=4?{%cf>3?<@8337E?61:&4<?4<a;:1<75f2383>>o2n3:17d76:188k<>=831vn<<j:186>5<7s-kn6;74H0;;?M7>92.<47<4i3294?=n:;0;66g:f;29?l?>2900c4650;9~f456290>6=4?{%cf>3?<@8337E?61:&4<?4<a;:1<75f2383>>o2n3:17d76:188k<>=831vn<;7:186>5<7s-kn65:4H0;;?M7>92.<47j4i6094?=n?:0;66g84;29?l122900c5h50;9~f43129086=4?{%cf>=5<@8337E?61:&4<?7f3-3=6<l=;h51>5<<a>91<75`8g83>>{e9<k1<7<50;2x dc=?01C=464H0;2?l162900c5h50;9~f430290>6=4?{%cf>=2<@8337E?61:&4<?c<a>81<75f7283>>o0<3:17d9::188k=`=831vn<;6:186>5<7s-kn6;74H0;;?M7>92.<47<4i3294?=n:;0;66g:f;29?l?>2900c4650;9~f42a290?6=4?{%cf>3><@8337E?61:&4<?4<a;:1<75f5g83>>o>13:17b77:188yg7283:187>50z&ba?0?3A;246F>909'3=<53`8;6=44i4d94?=n100;66a68;29?xd6=80;694?:1y'e`<102B:555G1838 2>=:2c9<7>5;h7e>5<<a031<75`9983>>{e9<81<7:50;2x dc=>11C=464H0;2?!1?2;1b>=4?::k6b?6=3`326=44o8:94?=zj8?86=4;:183!gb2?20D<77;I3:5>"00380e?>50;9j1c<722c257>5;n;;>5<<uk;>87>54;294~"fm3<37E?68:J2=4=#?1097d<?:188m0`=831b544?::m:<?6=3th:984?:583>5}#il0=46F>999K5<7<,>21>6g=0;29?l3a2900e4750;9l==<722wi=;950;594?6|,ho1485G18:8L4?63-=36<m4i6094?=n?:0;66g84;29?l122900e:850;9j32<722e3j7>5;|`2g5<7290;6=u+ad8b2>Nf<2Fj:7:t$`a92f=#im0=h6*nb;4a?!g>2?k0qp}:6;296~X2>27:::486:p10<72;qU9852f18;b>{t=:0;6?uQ529>a`<?n2wx9?4?:3y]17=:mj03j6s|5083>7}Y=816il47f:p15<72;qU9=52e98;b>{t<o0;6?uQ4g9>a3<?n2wx8i4?:3y]0a=:99814k5rs5a94?4|V=i01<>?:9d8yv2e2909wS:m;<df>=`<uz>j6=4={_6b?8`d21l0q~:6:181[2>34lj65h4}r6;>5<5sW>370h7:9d8yv202909wS:8;<d5>=`<uz>=6=4={_65?8`321l0q~:::181[2234l965h4}r67>5<5sW>?70k;:9d8yv252909wS:=;<d2>=`<uz>:6=4={_62?8ca21l0q~:?:181[2734oo65h4}r1e>5<5sW9m70km:9d8yv5b2909wS=j;<g:>=`<uz9o6=4={_1g?8c021l0q~=l:181[5d34;;?76i;|q0f?6=:rT8n63>008;b>{t;h0;6?uQ3`9>bc<?n2wx?44?:3y]7<=:nm03j6s|5b83>7}Y=j16jo47f:p1g<72;qU9o52f88;b>{t=h0;6?uQ5`9>b2<?n2wx944?:3y]1<=:n<03j6s|5983>7}Y=116j>47f:p12<72;qU9:52e48;b>{t<:0;68uQ429>530=1116n:4:f:?210<2n27:9:485:p5=0=83;owS=7;<`3>32<58<=6?>4=04;>76<5k=1>=52b7814>;e=38;70l;:3289g5=:916n?4=0:?af?4734hj6?>4=c;965=:j109<63>3b814>;6;809<63>2d814>;6:h09<63>27814>;6:;09<63>1d814>;6=<09<63>55814>;6=:09<63>53814>;6=809<63>51814>;6<o09<63>58814>{t0k0;6iu218c9=4=:9?<1>?5217:967=:9:i1>?52123967=:9;o1>?5213c967=:9;<1>?52130967=:98o1>?5210f961=:9;:1>95214;91c=z{=o1<79t=0;:>3`<V=o01<<k:738944>2?;01<<::73894462?;01<?k:738yv7?n3:1>v3>68814>;fn3;2<6s|19g94?2|5mn1;>52114936=:99l1;>52ag8:a>{tj80;6?u2b1857>;fn3<97p}>8483>7}:9?319k5217c9<c=z{8236=4={<35=?5134;=n76i;|q2<<<72:q6==85739>55`=?;16=875999~w4>e2909w0?98;;;?8ga2h90q~?7c;296~;6;j02463>66843>{t9?o1<7:t=ca9<c=:m<0<?63j4;50?87683=87p}>7483>6}:k:03j63i3;50?8`52>90q~?86;297~;d<32m70h::6189c2=?:1v<98:1808e221l01k95729>b3<0;2wx=:650;1x9f0=0o16j4483:?e<?143ty:;44?:2y>g2<?n27mn79<;<db>25<uz;<m7>53z?`<?>a34lo6:=4=ga936=z{8=i6=4<{<a:>=`<5ol1;>52fd847>{t9>i1<7=t=bc9<c=:99;1;>52112936=z{8=o6=4<{<aa>=`<58:86:=4=021>25<uz;=j7>53z?a`?>a34o<6:=4=d4936=z{8=;6=4<{<`f>=`<5l31;>52e9847>{t9>;1<7=t=cd9<c=:mk0<?63ja;50?xu6?;0;6>u2c18;b>;bl3=870kl:618yv70;3:1?v3l1;:e?8ca2>901hk5729~w4132908w0m=:9d89c7=?:16j=483:p5=4=838:w0ml:9d89c7=?=16j=484:?fb?1334on6::4=df931=:mj0<863jb;57?8cf2>>01h75759>a=<0<27n;79;;<g5>22<58:86::4=021>22<58::6::4=023>22<5ol1;952fd840>;al3=?70hl:6689cd=?=16jl484:?e=?1334l36::4=g5931=:n?0<863i5;57?8`32>>01k=5759>b7<0<27n979;;<g7>22<uz;3?7>52z?g6?>a34;:<79;;|q23`<7289p1o:5999>f6<2n27ho79=;<f0>24<5m>1;?52d4846>;c>3=970j8:6089a>=?;16h4482:?ge?1534ni6:<4=bf937=:kl0<>63lf;51?8b72>801i?5739>`7<0:27:::485:p52`=83;8w0l::8:89g2==o16on483:?g7?1434n?6:=4=e7936=:l?0<?63k7;50?8b?2>901i75729>`d<0;27on79<;<ag>25<5jo1;>52cg847>;c83=870j>:6189a4=?:16=;95759~w4>7290:?v3m6;;;?8d22<l01nm5759>`6<0<27o879;;<f6>22<5m<1;952d6840>;c03=?70j6:6689ag=?=16ho484:?``?1334in6::4=bd931=:l90<863k1;57?8b52>>01<88:618yv7?93:1=>u2b68:<>;e>3?m70ml:6789a5=?<16h9485:?g1?1234n=6:;4=e5930=:l10<963k9;56?8bf2>?01il5749>ga<0=27hi79:;<ae>23<5m:1;852d0841>;c:3=>70?97;51?xu6>j0;69u2b98:<>;68=0<>63>04846>;68l0<>6s|17f94?3|5k315552b986b>;68=0<?63>04847>;68l0<?6s|19694?2|58<26464=04b>27<5mn1;?5214c934=z{82o6=4={<35<?3a34;=;76i;|q2<2<72:q6=;l5709>ec<>l27oo79>;|q2<d<72;q6=;855g9>ec<f:2wxhh4?:cy>f2<4>27i:7=9;<`6>60<5k>1?;52b2802>;e:39=70lm:2489gg=;?16n44<6:?a<?5134nh65h4}rg0>5<es4h<6?<4=c4967=:j<09>63m4;01?8d42;801o<5239>fg<5:27im7<=;<`:>74<5k21>?52de8;b>{tm80;6<<t=cc9===:j00>j63mc;51?8e42>801n:5739>g0<0:27h:79=;<a4>24<5j21;?52c8846>;di3=970mm:6089gb=?;16nh482:?ab?1534i;6:<4=b3937=:k;0<>6s|e383>44|5kh15552b`86b>;ek3=870m<:6189f2=?:16o8483:?`2?1434i<6:=4=b:936=:k00<?63la;50?8ee2>901oj5729>f`<0;27ij79<;<a3>25<5j;1;>52c3847>{tlo0;6<<t=c09===:jk0>j63mc;57?8e42>>01n:5759>g0<0<27h:79;;<a4>22<5j21;952c8840>;di3=?70mm:6689gb=?=16nh484:?ab?1334i;6::4=b3931=:k;0<86s|e183>44|5k915552b386b>;ek3=>70m<:6789f2=?<16o8485:?`2?1234i<6:;4=b:930=:k00<963la;56?8ee2>?01oj5749>f`<0=27ij79:;<a3>23<5j;1;852c3841>{t9921<7?>{<331?>a34l;6:;4=dg930=:mj0<963ja;56?8c?2>?01h85749>554=?<16==>5749>b`<0=27mo79:;<db>23<5o21;852f7841>;a<3=>70h=:6789`2=?<1v<>8:1825~;68=03j63i1;56?8ca2>?01hj5749>ag<0=27n579:;<g4>23<58:86:;4=022>23<5ol1;852fe841>;aj3=>70h6:6789c1=?<16j8485:?e7?1234o>6:;4}r33=?6=:8q6==858g9>b4<0:27m<79=;<ge>24<5lo1;?52ee846>;bk3=970km:6089`g=?;16i4482:?f<?1534o<6:<4=d4937=:9991;?52110937=:99;1;?52112937=:no0<>63ie;51?8`c2>801km5739>bg<0:27mm79=;<d:>24<5o21;?52f6846>;a>3=970h::6089c2=?;16j>482:?e6?1534o>6:<4=d6937=z{8>n6=4={<30g?3a34;8h76i;|q20a<72;q6=>l58g9>56b=?;1v<:l:181874i32m70?<d;50?xu6<90;6?u211c9<c=:9:h1;?5rs062>5<5s4;;n76i;<30f?143ty:8?4?:3y>55e=0o16=>o5739~w4242909w0??d;:e?874i3=87p}>4483>2}:98;14k521239=<=:9;o1545213c9=<=:9;<154521309=<=:98o1545rs01f>5<5s4;:<79:;<33a?>a3ty:894?:3y>546=0o16=<?5709~w45a2909w0??f;:e?87683=97p}>4c83>6}:9:n15n521239===:9:81;?5rs06b>5<3s4;8m77l;<30f??d34;9i777;<31b?153ty:844?:7y>55b=?<16==m5749>55d=?<16==o5749>57g=1116=?l5739~w42?290=w0??d;57?877k3=?70??b;57?877i3=?70?=6;;;?875?3=97p}>4683>3}:99n1;>5211a936=:99h1;>5211c936=:9;815552131937=z{8>=6=49{<33`?1534;;o79=;<33f?1534;;m79=;<32a???34;:j79=;|q252<72;q6=<k55g9>576=0o1v<?=:180875938?70?=4;07?876l3=n7p}>1983>7}:9;819k521369<c=z{8;86=4<{<311?4334;947<;;<315?1b3ty:=44?:3y>570==o16=?658g9~w4732908w0?=9;07?875k38?70?=5;5f?xu69h0;6?u213c91c=:9;i14k5rs036>5<4s4;9h7<;;<304?4334;9579j;|q25g<72;q6=?k55g9>566=0o1v<?9:181874;38?70?=d;5f?xu69j0;6?u212391c=:9:914k5rs017>5<4s4;:j76i;<32`??d34;9<79k;|q270<72:q6=?=58g9>577=1j16=?:57e9~w4512908w0?=7;:e?875=33h70?=8;5g?xu6;>0;6>u213`9<c=:9;315n5213a93a=z{8936=4<{<31b?>a34;9h77l;<304?1c3ty:?44?:3y>564=0o16=>=57e9~w43b2909w0?:6;51?872032m7p}>5b83>7}:9<31>?521449<c=z{8?i6=46{<361??>34;>8776;<367??>34;>>776;<365??>34;><776;<37b??>34;>5776;<36e?>a3ty:9k4?:3y>51`=1116=865739~w4072908w0?:0;;;?873n3?m70?:8;50?xu6>80;6>u21439===:9<:19k5214:931=z{8<96=4<{<366???34;>=7;i;<36<?123ty::>4?:2y>505=1116=8<55g9>501=?;1v<8;:180872<33370?:3;7e?872?3=87p}>5e83>7}:9<=14k52144936=z{8<>6=4<{<361???34;>87;i;<363?133twe?<950;3xL4?63td8=54?:0yK5<7<ug9:57>51zJ2=4=zf:;j6=4>{I3:5>{i;8h1<7?tH0;2?xh49j0;6<uG1838yk56l3:1=vF>909~j67b290:wE?61:m74`=83;pD<7>;|l065<728qC=4?4}o115?6=9rB:5<5rn201>5<6sA;2=6sa33194?7|@83:7p`<2583>4}O90;0qc==5;295~N6181vb><9:182M7>92we??950;3xL4?63td8>54?:0yK5<7<ug9957>51zJ2=4=zf:8j6=4>{I3:5>{i;;h1<7?tH0;2?xh4:j0;6<uG1838yk55l3:1=vF>909~j64b290:wE?61:m77`=83;pD<7>;|l075<728qC=4?4}o105?6=9rB:5<5rn211>5<6sA;2=6sa32194?7|@83:7p`<3583>4}O90;0qc=<5;295~N6181vb>=9:182M7>92we?>950;3xL4?63td8?54?:0yK5<7<ug9857>52zJ;a>N?l2B:5<5Ua9822e=utd8?l4?:0yK5<7<ug98n7>51zJ2=4=zf:9h6=4>{I:f?M>c3A;2=6Tn8;3x5<5=uS<n6<un8;~j65c290:wE6j;I:g?M7>92Pj97?t0;~j65b2909wE?61:m76`=83;pD<7>;|l005<728qC=4?4}o175?6=9rB:5<5rn261>5<6sA;2=6sa35194?7|@83:7p`<4583>4}O90;0qc=;5;295~N6181vb>:9:182M7>92we?9950;3xL4?63td8854?:0yK5<7<ug9?57>51zJ2=4=zf:>j6=4>{I3:5>{i;=h1<7?tH0;2?xh4<j0;6<uG1838yk53l3:1=vF>909~j62b290:wE?61:m71`=83;pD<7>;|l015<728qC=4?4}o165?6=9rB:5<5rn271>5<6sA;2=6sa34194?7|@83:7p`<5583>4}O90;0qc=:5;295~N6181vb>;9:182M7>92we?8950;3xL4?63td8954?:0yK5<7<ug9>57>51zJ2=4=zf:?j6=4>{I3:5>{i;<h1<7?tH0;2?xh4=j0;6<uG1838yk52l3:1=vF>909~j63b290:wE?61:m70`=83;pD<7>;|l025<728qC=4?4}o155?6=9rB:5<5rn241>5<6sA;2=6sa37194?7|@83:7p`<6583>4}O90;0qc=95;295~N6181vb>89:182M7>92we?;950;3xL4?63td8:54?:0yK5<7<ug9=57>51zJ2=4=zf:<j6=4>{I3:5>{i;?h1<7?tH0;2?xh4>j0;6<uG1838yk51l3:1=vF>909~j60b290:wE?61:m73`=83;pD<7>;|l035<728qC=4?4}o145?6=9rB:5<5rn251>5<6sA;2=6sa36194?7|@83:7p`<7583>4}O90;0qc=85;295~N6181vb>99:182M7>92we?:950;3xL4?63td8;54?:0yK5<7<ug9<57>51zJ2=4=zf:=j6=4>{I3:5>{i;>h1<7?tH0;2?xh4?j0;6<uG1838yk50l3:1=vF>909~j61b290:wE?61:m72`=83;pD<7>;|l0<5<728qC=4?4}o1;5?6=9rB:5<5rn2:1>5<6sA;2=6sa39194?7|@83:7p`<8583>4}O90;0qc=75;295~N6181vb>69:182M7>92we?5950;3xL4?63td8454?:0yK5<7<ug9357>51zJ2=4=zf:2j6=4>{I3:5>{i;1h1<7?tH0;2?xh40j0;6<uG1838yk5?l3:1=vF>909~j6>b290:wE?61:m7=`=83;pD<7>;|l0=5<728qC=4?4}o1:5?6=9rB:5<5rn2;1>5<6sA;2=6sa38194?7|@83:7p`<9583>4}O90;0qc=65;295~N6181vqpsO@By750<2k<:9<;or@A@x4xFGXrwKL
\ No newline at end of file
--- a/hdl/platform/chipscope_ila.ngc
+++ b/hdl/platform/chipscope_ila.ngc
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+files = ["mini_vme.vhd"];
--- a/hdl/rtl/mini_vme.vhd
+++ b/hdl/rtl/mini_vme.vhd
+-- minimalistic VME core providing only CR/CSR accesses. For SVEC AFPGA bootup
+-- purposes.
+
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xmini_vme is
+  generic (
+    g_user_csr_start : unsigned(20 downto 0);
+    g_user_csr_end   : unsigned(20 downto 0));
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- "Passive" mode enable: when '1', the core never touches the bus
+    passive_i : in std_logic;
+
+    -- stripped-down VME I/O
+    VME_RST_n_i    : in  std_logic;
+    VME_AS_n_i     : in  std_logic;
+    VME_LWORD_n_i  : in  std_logic;
+    VME_WRITE_n_i  : in  std_logic;
+    VME_DS_n_i     : in  std_logic_vector(1 downto 0);
+    VME_GA_i       : in  std_logic_vector(5 downto 0);  -- Geographical Address and GA parity
+    VME_DTACK_n_o  : out std_logic;
+    VME_DTACK_OE_o : out std_logic;
+
+    VME_AM_i   : in std_logic_vector(5 downto 0);
+    VME_ADDR_i : in std_logic_vector(31 downto 1);
+
+    VME_DATA_b_i    : in  std_logic_vector(31 downto 0);
+    VME_DATA_b_o    : out std_logic_vector(31 downto 0);
+    VME_DATA_DIR_o  : out std_logic;
+    VME_DATA_OE_N_o : out std_logic;
+
+    master_o : out t_wishbone_master_out;
+    master_i : in  t_wishbone_master_in
+    );
+
+end xmini_vme;
+
+architecture rtl of xmini_vme is
+
+  constant c_AM_CS_CSR    : std_logic_vector(5 downto 0) := "101111";
+  constant c_DTACK_LENGTH : integer                      := 20;
+
+  signal as_synced, ds_synced                 : std_logic;
+  signal ds_a, as_p1, ds_p1, write_n          : std_logic;
+  signal lword_latched                        : std_logic;
+  signal addr_latched                         : std_logic_vector(31 downto 1);
+  signal readback_data, data_latched          : std_logic_vector(31 downto 0);
+  signal am_latched                           : std_logic_vector(5 downto 0);
+  signal ds_latched                           : std_logic_vector(1 downto 0);
+  signal ga_latched                           : std_logic_vector(5 downto 0);
+  signal addr_valid, data_valid, ga_parity_ok : std_logic;
+
+  type t_fsm_state is (IDLE, DECODE_ADDR, EXEC_CYCLE, WAIT_ACK, DTACK);
+
+  signal state : t_fsm_state;
+
+  signal am_match, addr_match, dtype_match : std_logic;
+  signal is_write                          : std_logic;
+
+  signal dtack_counter : unsigned(7 downto 0);
+  
+begin  -- rtl
+
+  U_Sync_AS : gc_sync_ffs
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => VME_AS_n_i,
+      npulse_o => as_p1,
+      synced_o => as_synced);
+
+  ds_a <= VME_DS_n_i(0) and VME_DS_n_i(1);
+
+  U_Sync_DS : gc_sync_ffs
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => ds_a,
+      npulse_o => ds_p1,
+      synced_o => ds_synced);
+
+  U_Sync_Write : gc_sync_ffs
+    port map (
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => VME_WRITE_n_i,
+      synced_o => write_n);
+
+
+  ga_parity_ok <= ga_latched(5) xor ga_latched(4) xor ga_latched(3) xor ga_latched(2) xor ga_latched(1) xor ga_latched(0);
+
+  p_latch_addr : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(rst_n_i = '0') then
+        addr_valid <= '0';
+      elsif(as_p1 = '1') then
+        addr_latched  <= VME_ADDR_i;
+        addr_valid    <= '1';
+        am_latched    <= VME_AM_i;
+        ga_latched    <= VME_GA_i;
+        lword_latched <= VME_LWORD_n_i;
+      elsif(as_synced = '1') then
+        addr_valid <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_latch_data : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        data_valid <= '0';
+      elsif(ds_p1 = '1') then
+        data_latched <= VME_DATA_b_i;
+        ds_latched   <= VME_DS_n_i;
+        data_valid   <= '1';
+      elsif(ds_synced = '1') then
+        data_valid <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_decode : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        am_match    <= '0';
+        addr_match  <= '0';
+        dtype_match <= '0';
+      else
+        -- we accept only CS/CSR accesses
+        if(am_latched = c_AM_CS_CSR) then
+          am_match <= '1';
+        else
+          am_match <= '0';
+        end if;
+        -- ... D32 data type
+
+        if(ds_latched = "00" and lword_latched = '0' and addr_latched(1) = '0') then
+          dtype_match <= '1';
+        else
+          dtype_match <= '0';
+        end if;
+
+        -- ... and address matches our supported range
+        if(ga_parity_ok = '1' and addr_latched(23 downto 19) = not ga_latched(4 downto 0) and addr_latched(31 downto 24) = x"00") then
+          addr_match <= '1';
+        else
+          addr_match <= '0';
+        end if;
+        
+      end if;
+    end if;
+  end process;
+
+  p_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state <= IDLE;
+
+        VME_DATA_DIR_o  <= '0';
+        VME_DATA_OE_N_o <= '0';
+        VME_DTACK_n_o   <= '0';
+        VME_DTACK_OE_o  <= '0';
+      else
+        case state is
+          when IDLE =>
+            VME_DATA_DIR_o  <= '0';
+            VME_DTACK_n_o  <= '1';
+            VME_DTACK_OE_o <= '0';
+            dtack_counter  <= (others => '0');
+
+            if(addr_valid = '1' and data_valid = '1') then
+              state <= DECODE_ADDR;
+            end if;
+            
+          when DECODE_ADDR =>
+            if(addr_valid = '1') then
+              if(addr_match = '1' and am_match = '1' and dtype_match = '1') then
+                if((unsigned(addr_latched(18 downto 2)) & "00") >= g_user_csr_start
+                   and (unsigned(addr_latched(18 downto 2)) & "00") <= g_user_csr_end) then
+                  state    <= EXEC_CYCLE;
+                  is_write <= not write_n;
+                end if;
+              else
+                state <= IDLE;
+              end if;
+            end if;
+
+          when EXEC_CYCLE =>
+            master_o.adr <= std_logic_vector(resize(((unsigned(addr_latched(18 downto 2)) & "00") - g_user_csr_start), c_wishbone_address_width));
+            master_o.dat <= data_latched;
+            master_o.cyc <= '1';
+            master_o.sel <= "1111";
+            master_o.stb <= '1';
+            master_o.we  <= is_write;
+
+            state <= WAIT_ACK;
+
+          when WAIT_ACK =>
+            if(master_i.stall = '0') then
+              master_o.stb <= '0';
+            end if;
+
+            if(master_i.ack = '1') then
+              state         <= DTACK;
+              readback_data <= master_i.dat;
+            elsif(ds_synced = '1') then
+              state <= IDLE;
+            end if;
+            
+          when DTACK =>
+            VME_DATA_b_o <= readback_data;
+
+            if(passive_i = '1') then
+              VME_DATA_DIR_o <= '0';
+              VME_DATA_DIR_o <= '0';
+              VME_DTACK_OE_o <= '0';
+            else
+              VME_DTACK_n_o  <= '0';
+              VME_DTACK_OE_o <= '1';
+              VME_DATA_DIR_o <= not is_write;
+            end if;
+
+            dtack_counter <= dtack_counter + 1;
+
+            if(ds_synced = '1') then
+              state <= IDLE;
+            end if;
+            
+        end case;
+      end if;
+    end if;
+  end process;
+
+end rtl;
--- a/hdl/sim/regs/xloader_regs.vh
+++ b/hdl/sim/regs/xloader_regs.vh
+`define ADDR_XLDR_CSR                  5'h0
+`define XLDR_CSR_START_OFFSET 0
+`define XLDR_CSR_START 32'h00000001
+`define XLDR_CSR_DONE_OFFSET 1
+`define XLDR_CSR_DONE 32'h00000002
+`define XLDR_CSR_ERROR_OFFSET 2
+`define XLDR_CSR_ERROR 32'h00000004
+`define XLDR_CSR_BUSY_OFFSET 3
+`define XLDR_CSR_BUSY 32'h00000008
+`define XLDR_CSR_MSBF_OFFSET 4
+`define XLDR_CSR_MSBF 32'h00000010
+`define XLDR_CSR_SWRST_OFFSET 5
+`define XLDR_CSR_SWRST 32'h00000020
+`define XLDR_CSR_EXIT_OFFSET 6
+`define XLDR_CSR_EXIT 32'h00000040
+`define XLDR_CSR_CLKDIV_OFFSET 8
+`define XLDR_CSR_CLKDIV 32'h00003f00
+`define ADDR_XLDR_BTRIGR               5'h4
+`define ADDR_XLDR_GPIOR                5'h8
+`define ADDR_XLDR_FIFO_R0              5'hc
+`define XLDR_FIFO_R0_XSIZE_OFFSET 0
+`define XLDR_FIFO_R0_XSIZE 32'h00000003
+`define XLDR_FIFO_R0_XLAST_OFFSET 2
+`define XLDR_FIFO_R0_XLAST 32'h00000004
+`define ADDR_XLDR_FIFO_R1              5'h10
+`define XLDR_FIFO_R1_XDATA_OFFSET 0
+`define XLDR_FIFO_R1_XDATA 32'hffffffff
+`define ADDR_XLDR_FIFO_CSR             5'h14
+`define XLDR_FIFO_CSR_FULL_OFFSET 16
+`define XLDR_FIFO_CSR_FULL 32'h00010000
+`define XLDR_FIFO_CSR_EMPTY_OFFSET 17
+`define XLDR_FIFO_CSR_EMPTY 32'h00020000
+`define XLDR_FIFO_CSR_USEDW_OFFSET 0
+`define XLDR_FIFO_CSR_USEDW 32'h000000ff
--- a/hdl/sim/vme64x_bfm/components/sn74vmeh22501.v
+++ b/hdl/sim/vme64x_bfm/components/sn74vmeh22501.v
+`timescale 1ns/1ns 
+
+module sn74vmeh22501 (
+    input   oeab1,
+            oeby1_n,
+            a1,
+    output  y1,
+    inout   b1,
+
+    input   oeab2,
+            oeby2_n,
+            a2,
+    output  y2,
+    inout   b2,
+
+    input   oe_n,
+    input   dir,    
+            clkab,
+            le,
+            clkba,
+    inout   [1:8] a3,
+    inout   [1:8] b3);
+
+assign b1   = oeab1   ? a1      : 1'bz;
+assign y1   = oeby1_n ? 1'bz    : b1;
+
+assign b2   = oeab2   ? a2      : 1'bz;
+assign y2   = oeby2_n ? 1'bz    : b2;
+
+reg [1:8] b3LFF;
+always @(posedge clkab) if (~le) b3LFF <= #1 a3;
+always @* if (le) b3LFF = a3;
+assign b3   = (~oe_n && dir) ? b3LFF : 8'hz;
+
+reg [1:8] a3LFF;
+always @(posedge clkba) if (~le) a3LFF <= #1 b3;
+always @* if (le) a3LFF = b3;
+assign a3   = (~oe_n && ~dir) ? a3LFF : 8'hz;
+
+endmodule
+
--- a/hdl/sim/vme64x_bfm/svec_vme_buffers.svh
+++ b/hdl/sim/vme64x_bfm/svec_vme_buffers.svh
+`include "components/sn74vmeh22501.v"
+
+`include "vme64x_bfm.svh"
+
+module bidir_buf(
+    a,
+    b,
+    dir, /* 0: a->b, 1: b->a */
+    oe_n );
+
+   parameter g_width = 1;
+   
+   inout [g_width-1:0] a,b;
+   input               dir, oe_n;
+   
+   assign b = (!dir && !oe_n) ? a : 'bz;
+   assign a = (dir && !oe_n) ? b : 'bz;
+endmodule // bidir_buf
+
+
+
+
+module svec_vme_buffers (
+    output       VME_AS_n_o,
+    output       VME_RST_n_o,
+    output       VME_WRITE_n_o,
+    output [5:0] VME_AM_o,
+    output [1:0] VME_DS_n_o,
+    output [5:0] VME_GA_o,
+    input        VME_BERR_i,
+    input        VME_DTACK_n_i,
+    input        VME_RETRY_n_i,
+    input        VME_RETRY_OE_i,
+    inout        VME_LWORD_n_b,
+    inout [31:1] VME_ADDR_b,
+    inout [31:0] VME_DATA_b,
+    output       VME_BBSY_n_o,
+    input [6:0]  VME_IRQ_n_i,
+    output       VME_IACKIN_n_o,
+    input        VME_IACKOUT_n_i,
+    output        VME_IACK_n_o,
+    input        VME_DTACK_OE_i,
+    input        VME_DATA_DIR_i,
+    input        VME_DATA_OE_N_i,
+    input        VME_ADDR_DIR_i,
+    input        VME_ADDR_OE_N_i,
+                 
+    IVME64X.slave slave
+    );
+
+   pullup(slave.as_n);
+   pullup(slave.rst_n);
+   pullup(slave.irq_n[0]);
+   pullup(slave.irq_n[1]);
+   pullup(slave.irq_n[2]);
+   pullup(slave.irq_n[3]);
+   pullup(slave.irq_n[4]);
+   pullup(slave.irq_n[5]);
+   pullup(slave.irq_n[6]);
+   pullup(slave.iack_n);
+   pullup(slave.dtack_n);
+   pullup(slave.retry_n);
+   pullup(slave.ds_n[1]);
+   pullup(slave.ds_n[0]);
+   pullup(slave.lword_n);
+   pullup(slave.berr_n);
+   pullup(slave.write_n);
+   pulldown(slave.bbsy_n);
+   pullup(slave.iackin_n);
+   
+   assign VME_RST_n_o = slave.rst_n;
+   
+   assign VME_AS_n_o     = slave.as_n;
+   assign VME_GA_o     = slave.ga;
+   assign VME_WRITE_n_o  = slave.write_n;
+   assign VME_AM_o = slave.am;
+   assign VME_DS_n_o = slave.ds_n;
+   assign VME_BBSY_n_o = slave.bbsy_n;
+   assign VME_IACKIN_n_o = slave.iackin_n;
+   assign VME_IACK_n_o = slave.iack_n;
+
+   bidir_buf #(1)  b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(33) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
+
+   pulldown(VME_BERR_i);
+   pulldown(VME_ADDR_DIR_i);
+   pulldown(VME_ADDR_OE_N_i);
+   pulldown(VME_DATA_DIR_i);
+   pulldown(VME_DATA_OE_N_i);
+   
+   
+   assign slave.dtack_n = VME_DTACK_n_i;
+   assign slave.berr_n = ~VME_BERR_i;
+   assign slave.retry_n = VME_RETRY_n_i;
+endmodule
+
+
+`define DECLARE_VME_BUFFERS(iface) \
+    wire VME_AS_n;\
+    wire VME_RST_n;\
+    wire VME_WRITE_n;\
+    wire [5:0] VME_AM;\
+    wire [1:0] VME_DS_n;\
+    wire VME_BERR;\
+    wire VME_DTACK_n;\
+    wire VME_RETRY_n;\
+    wire VME_RETRY_OE;\
+    wire VME_LWORD_n;\
+    wire [31:1]VME_ADDR;\
+    wire [31:0]VME_DATA;\
+    wire VME_BBSY_n;\
+    wire [6:0]VME_IRQ_n;\
+    wire VME_IACKIN_n,VME_IACK_n;\
+    wire VME_IACKOUT_n;\
+    wire VME_DTACK_OE;\
+    wire VME_DATA_DIR;\
+    wire VME_DATA_OE_N;\
+    wire VME_ADDR_DIR;\
+    wire VME_ADDR_OE_N;\
+    svec_vme_buffers U_VME_Bufs ( \
+    .VME_AS_n_o(VME_AS_n),\
+    .VME_RST_n_o(VME_RST_n),\
+    .VME_WRITE_n_o(VME_WRITE_n),\
+    .VME_AM_o(VME_AM),\
+    .VME_DS_n_o(VME_DS_n),\
+    .VME_BERR_i(VME_BERR),\
+    .VME_DTACK_n_i(VME_DTACK_n),\
+    .VME_RETRY_n_i(VME_RETRY_n),\
+    .VME_RETRY_OE_i(VME_RETRY_OE),\
+    .VME_LWORD_n_b(VME_LWORD_n),\
+    .VME_ADDR_b(VME_ADDR),\
+    .VME_DATA_b(VME_DATA),\
+    .VME_BBSY_n_o(VME_BBSY_n),\
+    .VME_IRQ_n_i(VME_IRQ_n),\
+    .VME_IACK_n_o(VME_IACK_n),\
+    .VME_IACKIN_n_o(VME_IACKIN_n),\
+    .VME_IACKOUT_n_i(VME_IACKOUT_n),\
+    .VME_DTACK_OE_i(VME_DTACK_OE),\
+    .VME_DATA_DIR_i(VME_DATA_DIR),\
+    .VME_DATA_OE_N_i(VME_DATA_OE_N),\
+    .VME_ADDR_DIR_i(VME_ADDR_DIR),\
+    .VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
+    .slave(iface)\
+    );
+
+function automatic bit[5:0] _gen_ga(int slot);
+     bit[4:0] slot_id = slot;
+     return {^slot_id, ~slot_id};
+endfunction // _gen_ga
+
+   
+		
+`define WIRE_VME_PINS(slot_id) \
+    .VME_AS_n_i(VME_AS_n),\
+    .VME_RST_n_i(VME_RST_n),\
+    .VME_WRITE_n_i(VME_WRITE_n),\
+    .VME_AM_i(VME_AM),\
+    .VME_DS_n_i(VME_DS_n),\
+    .VME_GA_i(_gen_ga(slot_id)),\
+    .VME_BERR_o(VME_BERR),\
+    .VME_DTACK_n_o(VME_DTACK_n),\
+    .VME_RETRY_n_o(VME_RETRY_n),\
+    .VME_RETRY_OE_o(VME_RETRY_OE),\
+    .VME_LWORD_n_b(VME_LWORD_n),\
+    .VME_ADDR_b(VME_ADDR),\
+    .VME_DATA_b(VME_DATA),\
+    .VME_BBSY_n_i(VME_BBSY_n),\
+    .VME_IRQ_n_o(VME_IRQ_n),\
+    .VME_IACK_n_i(VME_IACK_n),\
+    .VME_IACKIN_n_i(VME_IACKIN_n),\
+    .VME_IACKOUT_n_o(VME_IACKOUT_n),\
+    .VME_DTACK_OE_o(VME_DTACK_OE),\
+    .VME_DATA_DIR_o(VME_DATA_DIR),\
+    .VME_DATA_OE_N_o(VME_DATA_OE_N),\
+    .VME_ADDR_DIR_o(VME_ADDR_DIR),\
+    .VME_ADDR_OE_N_o(VME_ADDR_OE_N)
+
+
+		
\ No newline at end of file
--- a/hdl/sim/vme64x_bfm/vme64x_bfm.svh
+++ b/hdl/sim/vme64x_bfm/vme64x_bfm.svh
+`ifndef __VME64X_BFM_SVH
+ `define __VME64X_BFM_SVH 1
+
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+
+`define assert_wait(name, condition, timeout) \
+begin\
+   time t=$time;\
+   while(!(condition)) begin\
+      #1ns;\
+      if($time - t > timeout) begin\
+         $display("Wait timeout : ", `"name`"); \
+        //   $stop;\
+           break;\
+             end\
+      end\
+end
+
+
+
+
+
+interface IVME64X ( input sys_rst_n_i );
+
+   wire as_n;
+   wire rst_n;
+   wire write_n;
+   wire [5:0] am;
+   wire [1:0] ds_n;
+   wire [5:0] ga;
+   wire berr_n, dtack_n;
+   wire retry_n;
+   wire lword_n;
+   wire [31:1] addr;
+   wire [31:0] data;
+   wire bbsy_n;
+   wire [6:0]  irq_n;
+   wire iackin_n, iackout_n, iack_n;
+
+   logic q_as_n = 1'bz;
+   logic q_rst_n = 1'bz;
+   logic q_write_n = 1'bz;
+   logic [5:0] q_am = 6'bz;
+   logic [1:0] q_ds_n = 2'bz;
+   logic [5:0] q_ga = 6'bz;
+   logic q_berr_n = 1'bz, q_dtack_n = 1'bz;
+   logic q_retry_n = 1'bz;
+   logic q_lword_n = 1'bz;
+   logic [31:1] q_addr = 31'bz;
+   logic [31:0] q_data = 32'bz;
+   logic q_bbsy_n = 1'bz;
+   logic [6:0] q_irq_n = 7'bz;
+   logic q_iackin_n = 1'bz, q_iackout_n = 1'bz, q_iack_n = 1'bz;
+
+
+   /* SystemVerilog does not allow pullups inside interfaces or on logic type */
+   
+   assign as_n = q_as_n;
+   assign rst_n = q_rst_n;
+   assign write_n = q_write_n;
+   assign am = q_am;
+   assign ds_n = q_ds_n;
+   assign ga = q_ga;
+   assign berr_n = q_berr_n;
+   assign dtack_n = q_dtack_n;
+   assign retry_n = q_retry_n;
+   assign lword_n = q_lword_n;
+   assign addr = q_addr;
+   assign data = q_data;
+   assign bbsy_n = q_bbsy_n;
+   assign irq_n = q_irq_n;
+   assign iackin_n = q_iackin_n;
+   assign iackout_n = q_iackout_n;
+   assign iack_n = q_iack_n;
+   
+ //  VME Master
+   modport tb
+     (
+      output as_n, 
+      output rst_n, 
+      output write_n, 
+      output am, 
+      output ds_n, 
+      output ga, 
+      output bbsy_n,
+      output iackin_n,
+      output iack_n,
+      input  berr_n, 
+      input  irq_n, 
+      input  iackout_n,
+      inout  addr,
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n,
+
+      input q_as_n, 
+      input q_rst_n, 
+      input q_write_n, 
+      input q_am, 
+      input q_ds_n, 
+      input q_ga, 
+      input q_bbsy_n,
+      input q_iackin_n,
+      input q_iack_n,
+      input  q_berr_n, 
+      input  q_irq_n, 
+      input  q_iackout_n,
+      input  q_addr,
+      input  q_data, 
+      input  q_lword_n, 
+      input  q_retry_n, 
+      input  q_dtack_n
+      );
+
+    modport master
+     (
+      output as_n, 
+      output rst_n, 
+      output write_n, 
+      output am, 
+      output ds_n, 
+      output ga, 
+      output bbsy_n,
+      output iackin_n,
+      output iack_n,
+      input  berr_n, 
+      input  irq_n, 
+      input  iackout_n,
+      inout  addr,
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n);
+   
+   
+   //  VME Slave
+   modport slave
+     (
+      input  as_n, 
+      input  rst_n, 
+      input  write_n, 
+      input  am, 
+      input  ds_n, 
+      input  ga, 
+      input  bbsy_n, 
+      input  iackin_n,
+      input iack_n,
+      output berr_n, 
+      output irq_n, 
+      output iackout_n,
+      inout  addr, 
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n
+      );
+
+   initial forever begin
+      @(posedge sys_rst_n_i);
+      #100ns;
+      q_rst_n = 0;
+      #100ns;
+      q_rst_n = 1;
+   end
+   
+   
+
+endinterface // IVME64x
+
+
+
+const uint64_t CSR_BAR             = 'h7FFFF;
+const uint64_t CSR_BIT_SET_REG     = 'h7FFFB;
+const uint64_t CSR_BIT_CLR_REG     = 'h7FFF7;
+const uint64_t CSR_CRAM_OWNER      = 'h7FFF3;
+const uint64_t CSR_USR_BIT_SET_REG = 'h7FFEF;
+const uint64_t CSR_USR_BIT_CLR_REG = 'h7FFEB;
+
+typedef enum { DONT_CARE = 'h100, 
+               A16       = 'h200, 
+               A24       = 'h300, 
+               A32       = 'h400, 
+               A64       = 'h500 
+               } vme_addr_size_t;
+
+typedef enum { 
+               SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70 } vme_xfer_type_t;
+
+typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
+   
+class CBusAccessor_VME64x extends CBusAccessor;
+
+   const bit [3:0] dt_map [vme_data_type_t] =
+                   '{
+                     D08Byte0  : 4'b0101,	
+                     D08Byte1  : 4'b1001,
+                     D08Byte2  : 4'b0111,	
+                     D08Byte3  : 4'b1011,
+                     D16Byte01 : 4'b0001,
+                     D16Byte23 : 4'b0011,
+                     D32       : 4'b0000};
+   
+   protected bit [7:0] m_ba;
+   protected bit [4:0] m_ga;
+   virtual             IVME64X.tb vme;
+
+   function new(virtual IVME64X.tb _vme);
+      vme = _vme;
+      m_ga = 6'b010111;
+      vme.q_ga = m_ga;
+      m_ba = 8'b10000000;
+   endfunction // new
+
+   protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
+      bit[63:0] a = addr_in;
+      bit [31:0] a_out;
+      
+     const bit [5:0] am_map [int] = 
+                      '{
+                        A32 | CR_CSR : 6'b101111,
+                        A24 | CR_CSR : 6'b101111,
+                        A16 | SINGLE: 6'b101001,
+                        A16 | LCK : 6'b101100,
+                        A24 | SINGLE: 6'b111001,
+                        A24 | BLT : 6'b111011,
+                        A24 | MBLT : 6'b111000,
+                        A24 | LCK : 6'b110010,
+                        A32 | SINGLE: 6'b001001,
+                        A32 | BLT : 6'b001011,
+                        A32 | MBLT : 6'b001000,
+                        A32 | LCK : 6'b000101,
+                        A64 | SINGLE: 6'b000001,
+                        A64 | BLT : 6'b000011,
+                        A64 | MBLT : 6'b000000,
+                        A64 | LCK : 6'b001000,
+                        A32 | TwoeVME : 6'b100000,
+                        A64 | TwoeVME : 6'b100000,
+                        A32 | TwoeSST : 6'b100000,
+                        A64 | TwoeSST : 6'b100000};
+
+      vme.q_am = am_map[asize|xtype];
+
+      
+      if(xtype == CR_CSR)
+        a_out = {8'h0, ~m_ga[4:0], a[18:0]};
+      else case(asize)
+        A16: 
+          a_out = {16'h0, m_ba[7:3], a[10:2], 2'b00};
+        A24: 
+          a_out = {8'h0, m_ba[7:3], a[18:2], 2'b00};
+        A32:
+          a_out = {m_ba[7:3], a[26:2], 2'b00};
+      endcase // case (xtype)
+
+      vme.q_addr[31:2] = a_out[31:2];
+      
+   endtask // set_address
+
+   
+   protected task release_bus();
+      vme.q_as_n = 1'bz;
+      vme.q_write_n = 1'bz;
+      vme.q_ds_n = 2'bzz;
+      vme.q_lword_n = 1'bz;
+      vme.q_addr = 0;
+      vme.q_data = 32'bz;
+   endtask // release_bus
+   
+
+/* Simple generic VME read/write: single, BLT and CSR xfers */
+   protected task rw_generic(bit write, uint64_t _addr, ref uint64_t _data[], input vme_addr_size_t asize, input vme_xfer_type_t xtype, vme_data_type_t dtype);
+      bit[3:0] dt;
+      int      i;
+      
+      `assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
+      release_bus();
+      #10ns;
+
+      set_address(_addr, asize, xtype);
+      dt = dt_map[dtype];
+
+      vme.q_lword_n = dt[0];
+      vme.q_addr[1] = dt[1];
+      vme.q_write_n = !write;
+      
+      #35ns;
+      
+      vme.q_as_n = 0;
+      #10ns;
+
+//      $display("RWG %x\n", _data.size());
+      
+      
+      for(i=0;i<_data.size();i++)
+        begin
+           
+           if(write)
+             vme.q_data = (dtype == D08Byte0 || dtype == D08Byte2) ? (_data[i] << 8) : (_data[i]);
+
+           #35ns;
+           vme.q_ds_n = dt[3:2]; 
+
+           `assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
+           if(!vme.berr_n)
+             $error("[rw_simple_generic]: VME bus error.");
+
+           if(!write)
+             _data[i] = (dtype == D08Byte0 || dtype == D08Byte2) ? (vme.data >> 8) : (vme.data);
+           #10ns;
+           
+           end // for (i=0;i<_data.size();i++)
+      
+      release_bus();
+   endtask // rw_generic
+
+   protected task extract_xtype(int s, ref vme_xfer_type_t xtype, vme_addr_size_t asize, vme_data_type_t dtype);
+      xtype = vme_xfer_type_t'( s & 'h0f0);
+      asize = vme_addr_size_t'( s & 'hf00);
+      dtype = vme_data_type_t'( s & 'h00f);
+   endtask // extract_xtype
+
+   protected int m_default_modifiers = A32 | SINGLE | D32;
+   
+   
+   task set_default_modifiers(int mods);
+      m_default_modifiers = mods;
+   endtask // set_default_modifiers
+   
+   
+   task writem(uint64_t addr[], uint64_t data[], input int size = m_default_modifiers, ref int result);
+      int    i;
+      vme_addr_size_t asize;
+      vme_data_type_t dtype;
+      vme_xfer_type_t xtype;
+      
+      extract_xtype(size, xtype, asize, dtype);
+      if(xtype == SINGLE || xtype == CR_CSR)
+        for(i=0;i<addr.size();i++)
+          begin
+             uint64_t tmp[];
+             tmp = new[1];
+             tmp[0] = data[i];
+             rw_generic(1, addr[i], tmp, asize, xtype, dtype);
+          end
+      else if (xtype == BLT)
+           rw_generic(1, addr[0], data, asize, xtype, dtype);
+      
+   endtask // writem
+   
+   task readm(uint64_t addr[], ref uint64_t data[], input int size = m_default_modifiers, ref int result);
+      int    i;
+
+      vme_addr_size_t asize;
+      vme_data_type_t dtype;
+      vme_xfer_type_t xtype;
+      
+      extract_xtype(size, xtype, asize, dtype);
+      if(xtype == SINGLE || xtype == CR_CSR)
+        for(i=0;i<addr.size();i++)
+          begin
+             uint64_t tmp[];
+             tmp=new[1];
+             
+             rw_generic(0, addr[i], tmp, asize, xtype, dtype);
+             data[i] = tmp[0];
+          end
+
+   endtask // readm
+
+   task read(uint64_t addr, ref uint64_t data, input int size = m_default_modifiers, ref int result = _null);
+      int res;
+      uint64_t aa[1], da[];
+
+      da= new[1];
+
+      
+      aa[0]  = addr;
+      readm(aa, da, size, res);
+      data  = da[0];
+   endtask
+
+   task write(uint64_t addr, uint64_t data, input int size = m_default_modifiers, ref int result = _null);
+      uint64_t aa[], da[];
+      aa=new[1];
+      da=new[1];
+
+//      $display("VMEWrite s %x", size);
+      
+      
+      aa[0]  = addr;
+      da[0]  = data;
+
+      
+      writem(aa, da, size, result);
+   endtask
+
+   
+endclass // CBusAccessor_VME64x
+
+  
+
+
+   
+`endif //  `ifndef __VME64X_BFM_SVH
--- a/hdl/syn/svec_sfpga/Manifest.py
+++ b/hdl/syn/svec_sfpga/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../../ip_cores"
+
+syn_device = "xc6slx9"
+syn_grade = "-2"
+syn_package = "ftg256"
+syn_top = "svec_sfpga_top"
+syn_project = "svec_sfpga.xise"
+
+modules = { "local" : [ "../../top/svec_sfpga", "../../platform" ] }
--- a/hdl/syn/svec_sfpga/svec_sfpga.xise
+++ b/hdl/syn/svec_sfpga/svec_sfpga.xise
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_sfpga_top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_sfpga_top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="svec_sfpga_top" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="svec_sfpga_top_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="svec_sfpga_top_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="svec_sfpga_top_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="svec_sfpga_top_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="svec_sfpga" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-19T13:48:53" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="194246B812987A4976E1712D8445DFA6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <libraries>
+    <library xil_pn:name="blk_mem_gen_v4_1"/>
+    <library xil_pn:name="fifo_generator_v6_1"/>
+  </libraries>
+
+  <files>
+    <file xil_pn:name="../../top/svec_sfpga/svec_sfpga_top.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+      <library xil_pn:name="blk_mem_gen_v4_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+      <library xil_pn:name="fifo_generator_v6_1"/>
+    </file>
+    <file xil_pn:name="../../rtl/sfpga_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+    </file>
+    <file xil_pn:name="../../rtl/sfpga_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+    </file>
+    <file xil_pn:name="../../rtl/mini_vme.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+    </file>
+    <file xil_pn:name="../../top/svec_sfpga/svec_sfpga_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+    </file>
+    <file xil_pn:name="../../../../wr-repos/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
+    </file>
+  </files>
+
+  <bindings/>
+
+  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+
+</project>
--- a/hdl/testbench/svec_sfpga_top/Manifest.py
+++ b/hdl/testbench/svec_sfpga_top/Manifest.py
+action = "simulation"
+target = "xilinx"
+fetchto = "../../ip_cores"
+vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
+
+files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v" ]
+
+modules = { "local" :  [ "../../top/svec_sfpga" ] }
+
--- a/hdl/testbench/svec_sfpga_top/SIM_CONFIG_S6_SERIAL.v
+++ b/hdl/testbench/svec_sfpga_top/SIM_CONFIG_S6_SERIAL.v
+// Copyright (c) 1995/2005 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Function Simulation Library Component
+//  /   /                  Configuration Simulation Model
+// /___/   /\     Filename : SIM_CONFIG_S6_SERIAL.v
+// \   \  /  \    Timestamp : 
+//  \___\/\___\
+//
+// Revision:
+//    03/22/09 - Initial version of serial configuration simulation model for
+//               Spartann6.
+//    11/25/09 - Fix CRC (CR538766)
+//    02/24/10 - Change Tprog to 500 ns (CR550552)
+//    03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316)
+// End Revision
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale  1 ps / 1 ps
+
+module SIM_CONFIG_S6_SERIAL2 (
+                   DONE,
+                   CCLK,
+                   DIN,
+                   INITB,
+                   M,
+                   PROGB
+                   );
+
+  inout  DONE;
+  input  CCLK;
+  input  DIN;
+  inout  INITB;
+  input  [1:0] M;
+  input  PROGB;
+   
+  parameter DEVICE_ID     = 32'h0;
+
+  localparam cfg_Tprog    = 500000;   // min PROG must be low, 300 ns
+  localparam cfg_Tpl      = 100000;  // max program latency us.
+  localparam STARTUP_PH0  = 3'b000;
+  localparam STARTUP_PH1  = 3'b001;
+  localparam STARTUP_PH2  = 3'b010;
+  localparam STARTUP_PH3  = 3'b011;
+  localparam STARTUP_PH4  = 3'b100;
+  localparam STARTUP_PH5  = 3'b101;
+  localparam STARTUP_PH6  = 3'b110;
+  localparam STARTUP_PH7  = 3'b111;
+
+  wire GSR, GTS, GWE;
+  wire cclk_in;
+  wire init_b_in;
+  wire prog_b_in;
+  wire crc_err_flag_tot;
+  reg crc_err_flag_reg = 0;
+  reg mode_sample_flag = 0;
+  reg init_b_p = 1;
+  reg done_o = 0;
+  tri1 p_up;
+
+  triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p;
+  triand (weak1, strong0) DONE=done_o;
+
+  assign DONE = p_up;
+  assign INITB = p_up;
+
+  wire done_in;
+  reg por_b;
+  wire [1:0] m_in;
+  reg [2:0]  mode_pin_in = 3'b0;
+  wire [15:0] d_in;
+  wire [15:0] d_out;
+
+//  assign glbl.GSR = GSR;
+//  assign glbl.GTS = GTS;
+//  assign glbl.GWE = GWE;
+  wire d_out_en;
+  wire init_b_t;
+  wire prog_b_t;
+  wire crc_rst;
+ 
+  buf buf_cclk (cclk_in, CCLK);
+
+  buf buf_din (ds_in, DIN);
+//  buf buf_dout (DOUT, ds_out);
+  buf buf_init (init_b_in, INITB);
+  buf buf_m_0  (m_in[0], M[0]);
+  buf buf_m_1  (m_in[1], M[1]);
+  buf buf_prog (prog_b_in, PROGB);
+
+  time  prog_pulse_low_edge = 0;
+  time  prog_pulse_low = 0;
+  integer  wr_cnt  = 0;
+  reg  [4:0]   csbo_cnt = 5'b0;
+  reg csbo_flag = 0;
+  reg dcm_locked = 1;
+  reg [4:0] conti_data_cnt = 5'b0;
+  reg [5:0] rd_data_cnt = 6'b0;
+  reg [15:0]  pack_in_reg  = 16'b0;
+  reg  [5:0] reg_addr;
+  reg  [5:0] rd_reg_addr;
+  reg  new_data_in_flag  = 0;
+  reg  wr_flag  = 1;
+  reg  rd_flag  = 0;
+  reg  cmd_wr_flag  = 0;
+  reg  cmd_rd_flag  = 0;
+  reg  bus_sync_flag = 0;
+  reg  [1:0] buswidth = 2'b00;
+  reg  rd_sw_en = 0;
+  reg  conti_data_flag = 0;
+  reg  conti_data_flag_set = 0;
+  reg  [2:0] st_state = STARTUP_PH0;
+  reg  startup_begin_flag = 0;
+  reg  startup_end_flag = 0;
+  reg  cmd_reg_new_flag = 0;
+  reg  far_maj_min_flag = 0;
+  reg  crc_reset = 0;
+  reg  crc_ck = 0;
+  reg  crc_err_flag = 0;
+  wire crc_en, desync_flag;
+  reg  [21:0] crc_curr = 22'b0;
+  reg  [21:0] crc_new = 22'b0;
+  reg  [21:0] crc_input = 22'b0;
+  reg  gwe_out = 0;
+  reg  gts_out = 1;
+  reg  reboot_set = 0;
+  reg  gsr_set = 0;
+  reg  gts_usr_b = 1;
+  reg  done_pin_drv = 0;
+  reg  crc_bypass = 0;
+  reg  reset_on_err = 0;
+  reg  sync_timeout = 0;
+  reg  [31:0] crc_reg, idcode_reg, idcode_tmp;
+  reg  [15:0] far_maj_reg;
+  reg  [15:0] far_min_reg;
+  reg  [15:0]  fdri_reg;
+  reg  [15:0]  fdro_reg;
+  reg  [15:0]  cwdt_reg; 
+  reg  [15:0] ctl_reg = 8'b10000001;
+  reg  [4:0] cmd_reg;
+  reg  [15:0]  general1_reg;
+  reg  [15:0] mask_reg = 8'b0;
+  reg  [15:0] lout_reg, flr_reg;
+  reg  [15:0] cor1_reg = 16'b0x11011100000000;
+  reg  [15:0] cor2_reg = 16'b0000100111101110;
+  reg  [15:0] pwrdn_reg = 16'bx00010001000x001;
+  reg  [15:0] snowplow_reg;
+  reg  [15:0]  hc_opt_reg;
+  reg  [15:0]  csbo_reg;
+  reg  [15:0]  general2_reg;
+  reg  [15:0]  mode_reg;
+  reg  [15:0] general3_reg;
+  reg  [15:0]  general4_reg;
+  reg  [15:0]  general5_reg;
+  reg  [15:0] eye_mask_reg;
+  reg  [15:0]  cbc_reg;
+  reg  [15:0]  seu_reg;
+  reg  [15:0]  bootsts_reg;
+  reg  [15:0] pu_gwe_reg;
+  reg  [15:0]  pu_gts_reg;
+  reg  [15:0]  mfwr_reg;
+  reg  [15:0]  cclk_freq_reg;
+  reg  [15:0]  seu_opt_reg;
+  reg  [31:0] exp_sign_reg;
+  reg  [15:0]  rdbk_sign_reg;
+
+  reg  shutdown_set = 0;
+  reg  desynch_set = 0;
+  reg  [2:0] done_cycle_reg = 3'b100;
+  reg  [2:0] gts_cycle_reg = 3'b101;
+  reg  [2:0] gwe_cycle_reg=3'b110;
+  reg  [2:0] nx_st_state  = 3'b000;
+  reg  ghigh_b = 0;
+  reg  eos_startup = 0;
+  reg  startup_set = 0;
+  reg  [1:0] startup_set_pulse = 2'b0;
+  reg  [7:0] tmp_byte;
+  reg  [7:0] tmp_byte1;
+  reg  [7:0] tmp_byte2;
+  reg  [7:0] tmp_byte3;
+  reg  [7:0] tmp_byte4;
+  reg  [7:0] tmp_byte5;
+  reg  [7:0] tmp_byte6;
+  reg  [7:0] tmp_byte7;
+  reg  [15:0] tmp_word;
+  reg  [7:0] ctl_reg_tmp;
+  reg  id_error_flag = 0;
+  reg  iprog_b = 1;
+  reg  persist_en = 0;
+  reg  rst_sync = 0;
+  reg  [2:0] lock_cycle_reg = 3'b0;
+  reg  rbcrc_no_pin = 0;
+  reg  gsr_st_out = 1; 
+  reg  gsr_cmd_out = 0;
+  wire  [15:0] stat_reg;
+  wire rst_intl;
+  wire rw_en;
+  wire gsr_out;
+  wire cfgerr_b_flag;
+  reg  [27:0] downcont = 28'b0;
+  reg  type2_flag = 0;
+  reg  rst_en=1, prog_b_a=1;
+  reg [31:0] tmp_dword1;
+  reg [31:0] tmp_dword2;
+  integer wr_bit_addr;
+
+  initial begin
+    if (DEVICE_ID == 32'h0) begin
+      $display("Attribute Error : The attribute DEVICE_ID on  SIM_CONFIG_S6_SERIAL instance %m is not set.");
+     end
+   end
+ 
+
+   assign GSR = gsr_out;
+   assign GTS = gts_out;
+   assign GWE = gwe_out;
+   assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot;
+   assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg;
+   assign crc_en =  1;
+   assign done_in = DONE;
+
+  assign init_b_t = init_b_in;
+
+  always @( negedge prog_b_in) begin
+         rst_en = 0;
+         rst_en <= #cfg_Tprog 1;
+  end
+
+  always @( posedge rst_en or posedge prog_b_in ) 
+   if (rst_en == 1) begin
+     if (prog_b_in == 0 )
+         init_b_p <= 0;
+     else
+         init_b_p <= #(cfg_Tpl) 1;
+   end
+
+  always @( rst_en or prog_b_in or prog_pulse_low)
+    if (rst_en == 1) begin
+       if (prog_pulse_low == cfg_Tprog) begin
+           prog_b_a = 0;
+           prog_b_a <= #500 1;
+       end
+       else
+          prog_b_a = prog_b_in;
+    end
+    else
+          prog_b_a = 1;
+
+  initial begin
+    por_b = 0;
+    por_b = #400000 1;
+  end 
+
+  assign prog_b_t = prog_b_a  & iprog_b   & por_b;
+
+  assign rst_intl = (prog_b_t == 0 ) ? 0 : 1;
+
+
+  always @( init_b_t or  prog_b_t)
+   begin
+ $display("StupidP");
+   
+    if (prog_b_t == 0)
+         mode_sample_flag <= 0;
+    else if (init_b_t && mode_sample_flag == 0) begin
+       if (prog_b_t == 1)  begin
+          mode_pin_in <= m_in;
+          if (m_in != 2'b11) begin
+             mode_sample_flag <=  0;
+             $display("Error: input M is %h. Only Slave Serial mode M=11 supported on SIM_CONFIG_S6_SERIAL instance %m.", m_in);
+          end
+          else
+             mode_sample_flag <= #1 1;
+       end
+     end
+   end // always @ ( init_b_t or  prog_b_t)
+   
+  always @(posedge init_b_t )
+       if (prog_b_t != 1)  begin
+            if ($time != 0 )
+       $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
+    end
+
+  always @(m_in)
+    if (mode_sample_flag == 1 && persist_en == 1)
+       $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
+  
+  always @(posedge prog_b_in or negedge prog_b_in)
+    if (prog_b_in == 0) 
+        prog_pulse_low_edge <= $time;
+    else if (prog_b_in == 1 && $time > 0) begin
+       prog_pulse_low = $time - prog_pulse_low_edge;
+       if (prog_pulse_low < cfg_Tprog )
+        $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S6_SERIAL instance %m at time %t.", cfg_Tprog, $time);
+    end
+
+    assign rw_en = (mode_sample_flag == 1 &&  done_o === 0) ? 1 : 0;
+    assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag;
+
+    always @(posedge cclk_in or  posedge desync_flag)
+      if (desync_flag == 1) begin
+          pack_in_reg <= 16'b0;
+          new_data_in_flag <= 0;
+          bus_sync_flag <= 0;
+          wr_cnt <= 0;
+          wr_flag <= 1;
+          tmp_dword1 <= 32'b0;
+          tmp_dword2 <= 32'b0;
+      end
+      else begin
+       if (rw_en == 1 ) begin
+          if (bus_sync_flag == 0) begin
+               tmp_dword1 = { tmp_dword2[30:0], ds_in};
+               if (tmp_dword1[31:0] == 32'hAA995566) begin
+                          bus_sync_flag <= 1;
+                          new_data_in_flag <= 0;
+                          tmp_dword2 <= 32'b0;
+                          pack_in_reg <= 16'b0;
+                          wr_cnt <= 0;
+                end
+                else begin
+                      tmp_dword2 <= tmp_dword1;
+                end
+           end
+          else begin
+                pack_in_reg <= {pack_in_reg[14:0], ds_in};
+                if (wr_cnt == 15) begin
+                     new_data_in_flag <= 1;
+                     wr_cnt <=  0;
+                end
+                else  begin
+                     new_data_in_flag <= 0;
+                     wr_cnt <= wr_cnt + 1;
+                 end
+          end
+     end
+     else begin  //rw_en = 0
+            new_data_in_flag <= 0;
+     end
+    end
+
+     always @(negedge cclk_in or negedge rst_intl)
+      if (rst_intl == 0) begin
+         conti_data_flag <= 0;
+         conti_data_cnt <= 5'b0;
+         cmd_wr_flag <= 0;
+         cmd_rd_flag <= 0;
+         id_error_flag <= 0;
+         far_maj_min_flag <= 0;
+         cmd_reg_new_flag <= 0;
+         crc_curr <= 22'b0;
+         crc_ck <= 0;
+         csbo_cnt <= 0;
+         csbo_flag <= 0;
+         downcont <= 28'b0;
+         rd_data_cnt <= 0;
+      end
+      else begin
+        if (crc_reset == 1 ) begin
+            crc_reg <= 32'b0;
+            exp_sign_reg <= 32'b0;
+            crc_ck <= 0;
+            crc_curr <= 22'b0;
+        end
+        if (desynch_set == 1 || crc_err_flag==1) begin
+           conti_data_flag <= 0;
+           conti_data_cnt <= 5'b0;
+           cmd_wr_flag <= 0;
+           cmd_rd_flag <= 0;
+           far_maj_min_flag <= 0;
+           cmd_reg_new_flag <= 0;
+           crc_ck <= 0;
+           csbo_cnt <= 0;
+           csbo_flag <= 0;
+           downcont <= 28'b0;
+           rd_data_cnt <= 0;
+        end
+
+        if (new_data_in_flag == 1 && wr_flag == 1) begin
+           if (conti_data_flag == 1 ) begin
+             if (type2_flag == 0) begin
+               case (reg_addr)
+               6'b000000 : if (conti_data_cnt == 5'b00001) begin
+                             crc_reg[15:0] <= pack_in_reg;
+                             crc_ck <= 1;
+                           end
+                          else if (conti_data_cnt == 5'b00010) begin
+                             crc_reg[31:16] <= pack_in_reg;
+                             crc_ck <= 0;
+                          end
+               6'b000001 : if (conti_data_cnt == 5'b00010) begin
+                              far_maj_reg <= pack_in_reg;
+                              far_maj_min_flag <=1;
+                            end
+                           else if (conti_data_cnt == 5'b00001) begin
+                               if (far_maj_min_flag ==1) begin
+                                  far_min_reg <= pack_in_reg;
+                                  far_maj_min_flag <= 0;
+                               end
+                               else
+                                  far_maj_reg <= pack_in_reg;
+                           end
+               6'b000010 : far_min_reg <= pack_in_reg;
+               6'b000011 : fdri_reg <= pack_in_reg;
+               6'b000101 : cmd_reg <= pack_in_reg[4:0];
+               6'b000110 : begin
+                             ctl_reg_tmp = (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg);
+                             ctl_reg <= {8'b0, ctl_reg_tmp[7:0]};
+                           end
+               6'b000111 : mask_reg <= pack_in_reg;
+               6'b001001 : lout_reg <= pack_in_reg;
+               6'b001010 : cor1_reg <= pack_in_reg;
+               6'b001011 : cor2_reg <= pack_in_reg;
+               6'b001100 : pwrdn_reg <= pack_in_reg;
+               6'b001101 : flr_reg <= pack_in_reg;
+               6'b001110 : 
+                          if (conti_data_cnt == 5'b00001) begin
+                             idcode_reg[15:0] <= pack_in_reg;
+                             idcode_tmp  = {idcode_reg[31:16], pack_in_reg};
+                             $display("IDCode: %x", idcode_tmp);
+                             
+                             if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin
+                                id_error_flag <= 1;
+                                $display("Error :  written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S6_SERIAL instance %m at time %t.", idcode_tmp, DEVICE_ID, $time);
+                             end 
+                             else
+                             id_error_flag <= 0;
+                          end
+                          else if (conti_data_cnt == 5'b00010)
+                             idcode_reg[31:16] <= pack_in_reg;
+                          
+               6'b001111 : cwdt_reg <= pack_in_reg;
+               6'b010000 : hc_opt_reg[6:0] <= pack_in_reg[6:0];
+               6'b010011 : general1_reg <= pack_in_reg;
+               6'b010100 : general2_reg <= pack_in_reg;
+               6'b010101 : general3_reg <= pack_in_reg;
+               6'b010110 : general4_reg <= pack_in_reg;
+               6'b010111 : general5_reg <= pack_in_reg;
+               6'b011000 : mode_reg <= pack_in_reg;
+               6'b011001 : pu_gwe_reg <= pack_in_reg;
+               6'b011010 : pu_gts_reg <= pack_in_reg;
+               6'b011011 : mfwr_reg <= pack_in_reg;
+               6'b011100 : cclk_freq_reg <= pack_in_reg;
+               6'b011101 : seu_opt_reg <= pack_in_reg;
+               6'b011110 : if (conti_data_cnt == 5'b00001)
+                            exp_sign_reg[15:0] <= pack_in_reg;
+                          else if (conti_data_cnt == 5'b00010)
+                            exp_sign_reg[31:16] <= pack_in_reg;
+               6'b011111 : if (conti_data_cnt == 5'b00001)
+                            rdbk_sign_reg[15:0] <= pack_in_reg;
+                          else if (conti_data_cnt == 5'b00010)
+                            rdbk_sign_reg[31:16] <= pack_in_reg;
+               6'b100001 : eye_mask_reg <= pack_in_reg;
+               6'b100010 : cbc_reg <= pack_in_reg;
+               endcase
+
+             if (reg_addr == 6'b000101)
+                 cmd_reg_new_flag <= 1;
+             else
+                 cmd_reg_new_flag <= 0;
+
+             if (crc_en == 1) begin 
+               if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111)
+                   crc_curr[21:0] = 22'b0;
+               else begin
+                  if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h09 &&
+                    reg_addr != 6'h12 && reg_addr != 6'h1f &&
+                    reg_addr != 6'h20 &&  reg_addr != 6'h00) begin
+
+                     crc_input[21:0] = {reg_addr[5:0], pack_in_reg}; 
+                     crc_new[21:0] = crc_next(crc_curr, crc_input);
+                     crc_curr[21:0] <= crc_new;
+                   end
+               end
+             end
+            end
+            else  begin    // type2_flag
+                if (conti_data_cnt == 2)
+                   downcont[27:16] <= pack_in_reg[11:0];
+                else if (conti_data_cnt ==1) 
+                   downcont[15:0] <= pack_in_reg;
+            end
+
+             if (conti_data_cnt <= 5'b00001) begin
+                conti_data_cnt <= 5'b0;
+                type2_flag <= 0;
+             end
+             else
+                conti_data_cnt <= conti_data_cnt - 1;
+           end
+           else begin //if (conti_data_flag == 0 )
+             if ( downcont >= 1) begin
+                   if (crc_en == 1) begin
+                     crc_input[21:0] = {6'b000011, pack_in_reg};  //FDRI address plus data
+                     crc_new[21:0] = crc_next(crc_curr, crc_input);
+                     crc_curr[21:0] <= crc_new;
+                   end
+             end
+
+             if (pack_in_reg[15:13] == 3'b010 && downcont == 0 ) begin
+//                $display("Warning :  only Type 1 Packet supported on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time);
+                cmd_wr_flag <= 0;
+                type2_flag <= 1;
+                conti_data_flag <= 1;
+                conti_data_cnt <= 5'b00010;
+             end
+             else  if (pack_in_reg[15:13] == 3'b001 ) begin
+                if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin
+                    if (pack_in_reg[4:0] != 5'b0) begin
+                       cmd_rd_flag <= 1;
+                       cmd_wr_flag <= 0;
+//                       rd_data_cnt <= {pack_in_reg[4:0], 1'b0};
+                          rd_data_cnt <= 6'b000100;
+                       conti_data_cnt <= 5'b0;
+                       conti_data_flag = 0;
+                       rd_reg_addr <= pack_in_reg[10:5];
+                    end
+                end
+                else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin
+                    if (pack_in_reg[15:5] == 11'b00110010010) begin  // csbo reg
+                           csbo_reg <= pack_in_reg;
+                           csbo_cnt = pack_in_reg[4:0];
+                           csbo_flag <= 1;
+                           conti_data_flag = 0;
+                           reg_addr <= pack_in_reg[10:5];
+                           cmd_wr_flag <= 1;
+                           conti_data_cnt <= 5'b0;
+                    end
+                    else if (pack_in_reg[4:0] != 5'b0 ) begin
+                       cmd_wr_flag <= 1;
+                       conti_data_flag <= 1;
+                       conti_data_cnt <= pack_in_reg[4:0];
+                       reg_addr <= pack_in_reg[10:5];
+                    end
+                end
+                else begin
+                    cmd_wr_flag <= 0;
+                    conti_data_flag <= 0;
+                    conti_data_cnt <= 5'b0;
+                end
+             end
+             cmd_reg_new_flag <= 0;
+          crc_ck <= 0;
+          end // if (conti_data_flag == 0 )
+
+          if (csbo_cnt != 0 ) begin
+             if (csbo_flag)
+              csbo_cnt <= csbo_cnt - 1;
+          end
+          else
+              csbo_flag <= 0;
+
+          if (conti_data_cnt == 5'b00001 ) 
+                conti_data_flag <= 0;
+          
+      end
+
+      if (rw_en == 1) begin
+         if (rd_data_cnt == 1) begin
+            rd_data_cnt <= 0;
+         end
+         else if (rd_data_cnt == 0 && rd_flag == 1)
+               cmd_rd_flag <= 0;
+         else if (cmd_rd_flag == 1 && rd_flag == 1)
+             rd_data_cnt <= rd_data_cnt - 1;
+ 
+         if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1)
+              downcont <= downcont - 1;
+     end
+     if (crc_ck == 1)
+        crc_ck <= 0;
+   end
+
+    assign crc_rst = crc_reset | ~rst_intl;
+
+    always @(posedge cclk_in or posedge crc_rst )
+     if (crc_rst == 1)
+         crc_err_flag <= 0;
+     else
+        if (crc_ck == 1) begin
+          if (crc_bypass == 1) begin
+             if (crc_reg[31:0] != 32'h9876defc) 
+                 crc_err_flag <= 1;
+             else
+                 crc_err_flag <= 0;
+           end
+          else begin
+            if (crc_curr[21:0] != crc_reg[21:0]) 
+                crc_err_flag <= 1;
+            else
+                 crc_err_flag <= 0;
+          end
+       end
+       else
+           crc_err_flag <= 0;
+
+    always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag)
+     if (rst_intl == 0)
+         crc_err_flag_reg <= 0;
+     else if (crc_err_flag == 1)
+         crc_err_flag_reg <= 1;
+     else
+         crc_err_flag_reg <= 0;
+
+    always @(posedge cclk_in or negedge rst_intl)
+    if (rst_intl == 0) begin
+         startup_set <= 0;
+         crc_reset  <= 0;
+         gsr_set <= 0;
+         shutdown_set <= 0;
+         desynch_set <= 0;
+         reboot_set <= 0;
+         ghigh_b <= 0;
+    end
+    else begin
+      if (cmd_reg_new_flag == 1) begin 
+         if (cmd_reg == 5'b00011) 
+             ghigh_b <= 1;
+         else if (cmd_reg == 5'b01000)
+             ghigh_b <= 0;
+
+         if (cmd_reg == 5'b00101)
+             startup_set <= 1;
+         if (cmd_reg == 5'b00111) 
+              crc_reset <= 1;
+         if (cmd_reg == 5'b01010) 
+              gsr_set <= 1;
+         if (cmd_reg == 5'b01011)
+              shutdown_set <= 1;
+         if (cmd_reg == 5'b01101)
+              desynch_set <= 1;
+         if (cmd_reg == 5'b01110) 
+             reboot_set <= 1;
+      end
+      else  begin 
+             startup_set <= 0;
+              crc_reset <= 0;
+              gsr_set <= 0;
+              shutdown_set <= 0;
+              desynch_set <= 0;
+             reboot_set <= 0;
+      end
+    end
+
+
+   always @(posedge startup_set or posedge desynch_set or negedge  rw_en )
+    if (rw_en == 0)
+       startup_set_pulse <= 2'b0;
+    else begin
+      if (startup_set_pulse == 2'b00 && startup_set ==1)
+           startup_set_pulse <= 2'b01;
+      else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin
+           startup_set_pulse <= 2'b11;
+           @(posedge cclk_in )
+             startup_set_pulse <= 2'b00;
+      end
+    end
+    always @(ctl_reg) begin
+      if (ctl_reg[3] == 1)
+         persist_en = 1;
+      else
+         persist_en = 0;
+
+      if (ctl_reg[0] == 1)
+         gts_usr_b = 1;
+      else
+         gts_usr_b = 0;
+    end
+
+    always @(cor1_reg)
+    begin
+      if (cor1_reg[2] ==1)
+         done_pin_drv = 1;
+      else
+         done_pin_drv = 0;
+
+      if (cor1_reg[4] == 1)
+         crc_bypass = 1;
+      else
+         crc_bypass = 0;
+    end
+    
+    always @(cor2_reg) begin
+      if (cor2_reg[15] ==1)
+        reset_on_err = 1;
+      else
+        reset_on_err = 0;
+
+      done_cycle_reg = cor2_reg[11:9];
+      lock_cycle_reg = cor2_reg[8:6];
+      gts_cycle_reg = cor2_reg[5:3];
+      gwe_cycle_reg = cor2_reg[2:0];
+    end
+
+
+    assign stat_reg[15] = sync_timeout;
+    assign stat_reg[14] = 0;
+    assign stat_reg[13] = DONE;
+    assign stat_reg[12] = INITB;
+    assign stat_reg[11:9] = {1'b0, mode_pin_in};
+    assign stat_reg[8:6] = 3'b0;
+   assign stat_reg[5]             = ghigh_b;
+    assign stat_reg[4]            = gwe_out;
+    assign stat_reg[3]            = gts_out;
+    assign stat_reg[2]            = 1'bx;
+    assign stat_reg[1]            = id_error_flag;
+    assign stat_reg[0]            = crc_err_flag_reg; 
+
+
+    always @(posedge cclk_in or negedge rst_intl)
+      if (rst_intl == 0) begin
+        st_state                 <= STARTUP_PH0;
+        startup_begin_flag       <= 0;
+        startup_end_flag         <= 0;
+      end
+      else begin
+           if (nx_st_state == STARTUP_PH1) begin
+              startup_begin_flag <= 1;
+              startup_end_flag   <= 0;
+           end
+           else if (st_state == STARTUP_PH7) begin
+              startup_end_flag   <= 1;
+              startup_begin_flag <= 0;
+           end
+           if  (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg) begin
+                st_state         <= nx_st_state;
+           end
+           else
+              st_state           <= st_state;
+      end
+
+    always @(st_state or startup_set_pulse or DONE ) 
+    if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg))begin
+      $display("NextState?");
+   
+      case (st_state)
+      STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) 
+                       nx_st_state = STARTUP_PH1;
+                    else
+                       nx_st_state = STARTUP_PH0;
+      STARTUP_PH1 : nx_st_state = STARTUP_PH2;
+
+      STARTUP_PH2 : nx_st_state = STARTUP_PH3;
+
+      STARTUP_PH3 : nx_st_state = STARTUP_PH4;
+
+      STARTUP_PH4 : nx_st_state = STARTUP_PH5;
+
+      STARTUP_PH5 : nx_st_state = STARTUP_PH6;
+
+      STARTUP_PH6 : nx_st_state = STARTUP_PH7;
+
+      STARTUP_PH7 : nx_st_state = STARTUP_PH0;
+      endcase // case (st_state)
+    end // if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg))
+   
+
+    always @(posedge cclk_in or negedge rst_intl )
+      if (rst_intl == 0) begin
+          gwe_out <= 0;
+          gts_out <= 1;
+          eos_startup <= 0;
+          gsr_st_out <= 1;
+          done_o <= 0;
+      end
+      else begin
+
+         if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg))
+            if (DONE != 0 || done_pin_drv == 1)
+               done_o <= 1'b1;
+            else
+               done_o <= 1'bz;
+
+         if (nx_st_state == gwe_cycle_reg)  begin
+             gwe_out <= 1;
+         end
+
+         if (nx_st_state == gts_cycle_reg) begin
+             gts_out <= 0;
+         end
+
+         if (nx_st_state == STARTUP_PH6)
+             gsr_st_out <= 0;
+
+         if (nx_st_state == STARTUP_PH7)
+            eos_startup <= 1;
+
+      end
+
+
+     assign gsr_out = gsr_st_out | gsr_cmd_out;
+     
+function [21:0] crc_next;
+  input [21:0] crc_curr;
+  input [21:0] crc_input;
+  integer i_crc;
+  begin         
+    for(i_crc = 21; i_crc > 15; i_crc=i_crc -1)
+       crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
+
+    crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21]; 
+
+   for(i_crc = 14; i_crc > 12; i_crc=i_crc -1) 
+       crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
+
+   crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21];
+
+   for(i_crc = 11; i_crc > 7; i_crc=i_crc -1) 
+       crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
+
+   crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21];
+
+   for(i_crc = 6; i_crc > 0; i_crc=i_crc -1) 
+       crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc];
+
+   crc_next[0] =  crc_input[0] ^ crc_curr[21];
+ 
+  end
+endfunction
+
+function [7:0] bit_revers8;
+  input [7:0] din8;
+  begin
+      bit_revers8[0] = din8[7];
+      bit_revers8[1] = din8[6];
+      bit_revers8[2] = din8[5];
+      bit_revers8[3] = din8[4];
+      bit_revers8[4] = din8[3];
+      bit_revers8[5] = din8[2];
+      bit_revers8[6] = din8[1];
+      bit_revers8[7] = din8[0];
+  end
+endfunction
+
+
+
+endmodule
--- a/hdl/testbench/svec_sfpga_top/glbl.v
+++ b/hdl/testbench/svec_sfpga_top/glbl.v
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
--- a/hdl/testbench/svec_sfpga_top/main.sv
+++ b/hdl/testbench/svec_sfpga_top/main.sv
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
+`include "regs/xloader_regs.vh"
+
+module main;
+
+   reg rst_n = 0;
+   reg clk_20m = 0;
+   wire cclk, din, program_b, init_b, done, suspend;
+   wire [1:0] m;
+
+   
+   always #25ns clk_20m <= ~clk_20m;
+   
+   initial begin
+      repeat(20) @(posedge clk_20m);
+      rst_n = 1;
+   end
+
+   
+   IVME64X VME(rst_n);
+
+   `DECLARE_VME_BUFFERS(VME.slave);
+
+
+   svec_sfpga_top
+     
+     DUT (
+	  .lclk_n_i(clk_20m),
+	  .rst_n_i(rst_n),
+     
+	  `WIRE_VME_PINS(8),
+
+          .boot_clk_o(cclk),
+          .boot_config_o(program_b),
+          .boot_status_i(init_b),
+          .boot_done_i(done),
+          .boot_dout_o(din)
+	  );
+
+   SIM_CONFIG_S6_SERIAL2
+  #(
+    .DEVICE_ID(32'h34000093) // 6slx150t
+    ) U_serial_sim 
+    (
+     .DONE(done),
+     .CCLK(cclk),
+     .DIN(din),
+     .INITB(init_b), 
+     .M(2'b11),
+     .PROGB(program_b)
+     );
+
+
+
+class CSimDrv_Xloader;
+
+   protected CBusAccessor_VME64x acc;
+   protected uint64_t base;
+   
+   function new(CBusAccessor_VME64x _acc, uint64_t _base);
+      acc = _acc;
+      base = _base;
+   endfunction
+     
+        
+   task enter_boot_mode();
+      int i;
+      const int boot_seq[8] = '{'hde, 'had, 'hbe, 'hef, 'hca, 'hfe, 'hba, 'hbe};
+      
+      for(i=0;i<8;i++)
+        acc.write(base + `ADDR_XLDR_BTRIGR, boot_seq[i]);
+   endtask // enter_boot_mode
+
+   
+   task load_bitstream(string filename);
+      int f,i, pos=0;
+      uint64_t csr;
+     
+      acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );
+      acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);
+      f  = $fopen(filename, "r");
+      
+      while(!$feof(f))
+        begin
+           uint64_t r,r2;
+           acc.read(base + `ADDR_XLDR_FIFO_CSR, r);
+           
+           if(!(r&`XLDR_FIFO_CSR_FULL)) begin
+              int n;
+              int x;
+              
+              n  = $fread(x, f);
+              pos+=n;
+
+              if((pos % 4000) == 0)
+                $display("%d bytes sent", pos);
+              
+              
+              r=x;
+              r2=(n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0);
+              acc.write(base +`ADDR_XLDR_FIFO_R0, r2);
+              acc.write(base +`ADDR_XLDR_FIFO_R1, r);
+              end
+        end
+
+      $fclose(f);
+
+      while(1) begin
+        acc.read (base + `ADDR_XLDR_CSR, csr);
+         if(csr & `XLDR_CSR_DONE) begin
+            $display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));
+            acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_EXIT);
+            return;
+         end
+      end
+
+   endtask
+
+endclass
+   
+   
+   
+   initial begin
+      uint64_t d;
+      
+      int i, result;
+      
+      CBusAccessor_VME64x acc = new(VME.master);
+      CSimDrv_Xloader drv;
+      
+
+      #10us;
+      acc.set_default_modifiers(A32 | CR_CSR | D32);
+     // acc.write('h70000 + `ADDR_XLDR_GPIOR, 'haa);
+
+      
+
+      drv = new(acc, 'h70000);
+
+      #100us;
+      
+      drv.enter_boot_mode();
+
+      #100us;
+      
+      drv.load_bitstream("sample_bitstream/crc_gen.bin");
+      
+      
+   end
+
+  
+endmodule // main
+
+
+
--- a/hdl/testbench/svec_sfpga_top/run.do
+++ b/hdl/testbench/svec_sfpga_top/run.do
+vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
+vsim work.main -voptargs=+acc
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+do wave.do
+run 30us
\ No newline at end of file
--- a/hdl/testbench/svec_sfpga_top/sample_bitstream/crc_gen.bin
+++ b/hdl/testbench/svec_sfpga_top/sample_bitstream/crc_gen.bin
--- a/hdl/testbench/svec_sfpga_top/wave.do
+++ b/hdl/testbench/svec_sfpga_top/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/g_interface_mode
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/g_address_granularity
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/clk_sys_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/rst_n_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_cyc_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_stb_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_we_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_adr_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_sel_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_dat_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_dat_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_ack_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_stall_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_cclk_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_din_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_program_b_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_init_b_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_done_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_suspend_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_m_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_trig_p1_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_exit_p1_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_en_i
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/gpio_o
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/state
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/clk_div
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/tick
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/init_b_synced
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/done_synced
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/timeout_counter
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_in
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_out
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/regs_in
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/regs_out
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_data
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_size
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_last
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/bit_counter
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_state
+add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/startup_count
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {123219856 ps} 0}
+configure wave -namecolwidth 177
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {282492928 ps}
--- a/hdl/top/svec_sfpga/Manifest.py
+++ b/hdl/top/svec_sfpga/Manifest.py
+files = [ "svec_sfpga_top.vhd", "svec_sfpga_top.ucf" ]
+
+fetchto = "../../ip_cores"
+
+modules = {
+    "local" : ["../../rtl" ],
+    "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
+    }
--- a/hdl/top/svec_sfpga/svec_sfpga_top.ucf
+++ b/hdl/top/svec_sfpga/svec_sfpga_top.ucf
+#===============================================================================
+# IO Location Constraints
+#===============================================================================
+
+#----------------------------------------
+# VME interface
+#----------------------------------------
+NET "vme_write_n_i" LOC = B1;
+NET "vme_rst_n_i" LOC = G6;
+NET "vme_retry_oe_o" LOC = D3;
+NET "vme_retry_n_o" LOC = D1;
+NET "vme_lword_n_b" LOC = B3;
+NET "vme_iackout_n_o" LOC = E4;
+NET "vme_iackin_n_i" LOC = F6;
+NET "vme_iack_n_i" LOC = E3;
+NET "vme_dtack_oe_o" LOC = C3;
+NET "vme_dtack_n_o" LOC = C2;
+NET "vme_ds_n_i[1]" LOC = N9;
+NET "vme_ds_n_i[0]" LOC = P9;
+NET "vme_data_oe_n_o" LOC = K6;
+NET "vme_data_dir_o" LOC = F4;
+NET "vme_berr_o" LOC = C1;
+NET "vme_as_n_i" LOC = F5;
+NET "vme_addr_oe_n_o" LOC = K5;
+NET "vme_addr_dir_o" LOC = B2;
+NET "vme_irq_n_o[6]" LOC = C11;
+NET "vme_irq_n_o[5]" LOC = C8;
+NET "vme_irq_n_o[4]" LOC = D8;
+NET "vme_irq_n_o[3]" LOC = C10;
+NET "vme_irq_n_o[2]" LOC = E10;
+NET "vme_irq_n_o[1]" LOC = E8;
+NET "vme_irq_n_o[0]" LOC = E7;
+NET "vme_ga_i[5]" LOC = A3;
+NET "vme_ga_i[4]" LOC = A10;
+NET "vme_ga_i[3]" LOC = B10;
+NET "vme_ga_i[2]" LOC = A9;
+NET "vme_ga_i[1]" LOC = C9;
+NET "vme_ga_i[0]" LOC = A8;
+NET "vme_data_b[31]" LOC = F7;
+NET "vme_data_b[30]" LOC = A6;
+NET "vme_data_b[29]" LOC = B6;
+NET "vme_data_b[28]" LOC = C5;
+NET "vme_data_b[27]" LOC = D5;
+NET "vme_data_b[26]" LOC = A5;
+NET "vme_data_b[25]" LOC = B5;
+NET "vme_data_b[24]" LOC = A4;
+NET "vme_data_b[23]" LOC = T8;
+NET "vme_data_b[22]" LOC = P8;
+NET "vme_data_b[21]" LOC = N8;
+NET "vme_data_b[20]" LOC = M9;
+NET "vme_data_b[19]" LOC = T9;
+NET "vme_data_b[18]" LOC = R9;
+NET "vme_data_b[17]" LOC = M10;
+NET "vme_data_b[16]" LOC = L10;
+NET "vme_data_b[15]" LOC = N6;
+NET "vme_data_b[14]" LOC = M6;
+NET "vme_data_b[13]" LOC = T4;
+NET "vme_data_b[12]" LOC = P4;
+NET "vme_data_b[11]" LOC = L7;
+NET "vme_data_b[10]" LOC = L8;
+NET "vme_data_b[9]" LOC = P5;
+NET "vme_data_b[8]" LOC = N5;
+NET "vme_data_b[7]" LOC = T5;
+NET "vme_data_b[6]" LOC = R5;
+NET "vme_data_b[5]" LOC = T6;
+NET "vme_data_b[4]" LOC = P6;
+NET "vme_data_b[3]" LOC = T7;
+NET "vme_data_b[2]" LOC = R7;
+NET "vme_data_b[1]" LOC = M7;
+NET "vme_data_b[0]" LOC = P7;
+NET "vme_am_i[5]" LOC = B8;
+NET "vme_am_i[4]" LOC = C6;
+NET "vme_am_i[3]" LOC = D6;
+NET "vme_am_i[2]" LOC = A7;
+NET "vme_am_i[1]" LOC = C7;
+NET "vme_am_i[0]" LOC = E6;
+NET "vme_addr_b[31]" LOC = E1;
+NET "vme_addr_b[30]" LOC = E2;
+NET "vme_addr_b[29]" LOC = L5;
+NET "vme_addr_b[28]" LOC = L4;
+NET "vme_addr_b[27]" LOC = H3;
+NET "vme_addr_b[26]" LOC = J4;
+NET "vme_addr_b[25]" LOC = K3;
+NET "vme_addr_b[24]" LOC = F1;
+NET "vme_addr_b[23]" LOC = F2;
+NET "vme_addr_b[22]" LOC = G1;
+NET "vme_addr_b[21]" LOC = G3;
+NET "vme_addr_b[20]" LOC = H1;
+NET "vme_addr_b[19]" LOC = H2;
+NET "vme_addr_b[18]" LOC = J1;
+NET "vme_addr_b[17]" LOC = J3;
+NET "vme_addr_b[16]" LOC = K1;
+NET "vme_addr_b[15]" LOC = K2;
+NET "vme_addr_b[14]" LOC = L1;
+NET "vme_addr_b[13]" LOC = L3;
+NET "vme_addr_b[12]" LOC = M1;
+NET "vme_addr_b[11]" LOC = M2;
+NET "vme_addr_b[10]" LOC = N1;
+NET "vme_addr_b[9]" LOC = N3;
+NET "vme_addr_b[8]" LOC = P1;
+NET "vme_addr_b[7]" LOC = P2;
+NET "vme_addr_b[6]" LOC = R1;
+NET "vme_addr_b[5]" LOC = R2;
+NET "vme_addr_b[4]" LOC = N4;
+NET "vme_addr_b[3]" LOC = M5;
+NET "vme_addr_b[2]" LOC = M3;
+NET "vme_addr_b[1]" LOC = M4;
+
+#----------------------------------------
+# Application FPGA boot control
+#----------------------------------------
+NET "boot_clk_o" LOC = F14;
+NET "boot_config_o" LOC = C15;
+NET "boot_done_i" LOC = C16;
+NET "boot_dout_o" LOC = F13;
+NET "boot_status_i" LOC = E16;
+
+NET "debugled_o[2]" LOC = P15;
+NET "debugled_o[1]" LOC = L16;
+
+#IO standards
+
+NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
+NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
+NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
+NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
+NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
+NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
+NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
+NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
+NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
+NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
+NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
+NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
+NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
+NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
+NET "vme_berr_o" IOSTANDARD="LVCMOS33";
+NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
+NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
+NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
+NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[1]" IOSTANDARD="LVCMOS33";
+NET "vme_ga_i[0]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[31]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[30]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[29]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[28]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[27]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[26]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[25]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[24]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[23]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[22]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[21]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[20]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[19]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[18]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[17]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[16]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[15]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[14]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[13]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[12]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[11]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[10]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[9]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[8]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[7]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[6]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[5]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[4]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[3]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[2]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[1]" IOSTANDARD="LVCMOS33";
+NET "vme_data_b[0]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[5]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[4]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[3]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[2]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[1]" IOSTANDARD="LVCMOS33";
+NET "vme_am_i[0]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[31]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[30]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[29]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[28]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[27]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[26]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[25]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[24]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[23]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[22]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[21]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[20]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[19]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[18]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[17]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[16]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[15]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[14]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[13]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[12]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[11]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[10]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[9]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[8]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[7]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[6]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[5]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[4]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[3]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[2]" IOSTANDARD="LVCMOS33";
+NET "vme_addr_b[1]" IOSTANDARD="LVCMOS33";
+
+#----------------------------------------
+# Application FPGA boot control
+#----------------------------------------
+NET "boot_clk_o" IOSTANDARD="LVCMOS33";
+NET "boot_config_o" IOSTANDARD="LVCMOS33";
+NET "boot_done_i" IOSTANDARD="LVCMOS33";
+NET "boot_dout_o" IOSTANDARD="LVCMOS33";
+NET "boot_status_i" IOSTANDARD="LVCMOS33";
+
+NET "debugled_o[2]" IOSTANDARD="LVCMOS33";
+NET "debugled_o[1]" IOSTANDARD="LVCMOS33";
+
+# Clocks/resets
+
+NET "rst_n_i" LOC = E15;
+NET "lclk_n_i" LOC = H5;
+
+NET "rst_n_i" IOSTANDARD="LVCMOS33";
+NET "lclk_n_i" IOSTANDARD="LVCMOS33";
\ No newline at end of file
--- a/hdl/top/svec_sfpga/svec_sfpga_top.vhd
+++ b/hdl/top/svec_sfpga/svec_sfpga_top.vhd
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.svl_wbgen2_pkg.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity svec_sfpga_top is
+  port
+    (
+
+      -------------------------------------------------------------------------
+      -- Standard SVEC ports (Gennum bridge, LEDS, Etc. Do not modify
+      -------------------------------------------------------------------------
+
+      lclk_n_i : in std_logic;          -- 20MHz VCXO clock
+      rst_n_i  : in std_logic;
+
+      -------------------------------------------------------------------------
+      -- VME Interface pins
+      -------------------------------------------------------------------------
+
+      VME_AS_n_i    : in    std_logic;
+      VME_RST_n_i   : in    std_logic;
+      VME_WRITE_n_i : in    std_logic;
+      VME_AM_i      : in    std_logic_vector(5 downto 0);
+      VME_DS_n_i    : in    std_logic_vector(1 downto 0);
+      VME_GA_i      : in    std_logic_vector(5 downto 0);
+      VME_BERR_o    : inout std_logic := 'Z';
+      VME_DTACK_n_o : inout std_logic;
+      VME_LWORD_n_b : inout std_logic;
+      VME_ADDR_b    : inout std_logic_vector(31 downto 1);
+
+      VME_DATA_b      : inout std_logic_vector(31 downto 0);
+      VME_DTACK_OE_o  : inout std_logic;
+      VME_DATA_DIR_o  : inout std_logic;
+      VME_DATA_OE_N_o : inout std_logic;
+
+      -- unused pins, tied hi-impedance
+
+      VME_ADDR_DIR_o  : inout std_logic                    := 'Z';
+      VME_ADDR_OE_N_o : inout std_logic                    := 'Z';
+      VME_RETRY_n_o   : out   std_logic                    := 'Z';
+      VME_RETRY_OE_o  : out   std_logic                    := 'Z';
+      VME_BBSY_n_i    : in    std_logic;
+      VME_IRQ_n_o     : out   std_logic_vector(6 downto 0) := "ZZZZZZZ";
+      VME_IACK_n_i    : in    std_logic;
+      VME_IACKIN_n_i  : in    std_logic;
+      VME_IACKOUT_n_o : out   std_logic                    := 'Z';
+
+      -------------------------------------------------------------------------
+      -- AFPGA boot signals
+      -------------------------------------------------------------------------
+
+      boot_clk_o    : out std_logic;
+      boot_config_o : out std_logic;
+      boot_done_i   : in  std_logic;
+      boot_dout_o   : out std_logic;
+      boot_status_i : in  std_logic;
+
+      debugled_o : out std_logic_vector(2 downto 1)
+      );
+end svec_sfpga_top;
+
+architecture rtl of svec_sfpga_top is
+
+  component xmini_vme
+    generic (
+      g_user_csr_start : unsigned(20 downto 0);
+      g_user_csr_end   : unsigned(20 downto 0));
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_n_i         : in  std_logic;
+      passive_i       : in  std_logic;
+      VME_RST_n_i     : in  std_logic;
+      VME_AS_n_i      : in  std_logic;
+      VME_LWORD_n_i   : in  std_logic;
+      VME_WRITE_n_i   : in  std_logic;
+      VME_DS_n_i      : in  std_logic_vector(1 downto 0);
+      VME_GA_i        : in  std_logic_vector(5 downto 0);
+      VME_DTACK_n_o   : out std_logic;
+      VME_DTACK_OE_o  : out std_logic;
+      VME_AM_i        : in  std_logic_vector(5 downto 0);
+      VME_ADDR_i      : in  std_logic_vector(31 downto 1);
+      VME_DATA_b_i    : in  std_logic_vector(31 downto 0);
+      VME_DATA_b_o    : out std_logic_vector(31 downto 0);
+      VME_DATA_DIR_o  : out std_logic;
+      VME_DATA_OE_N_o : out std_logic;
+      master_o        : out t_wishbone_master_out;
+      master_i        : in  t_wishbone_master_in);
+  end component;
+
+  component xwb_xilinx_fpga_loader
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity);
+    port (
+      clk_sys_i       : in  std_logic;
+      rst_n_i         : in  std_logic;
+      slave_i         : in  t_wishbone_slave_in;
+      slave_o         : out t_wishbone_slave_out;
+      desc_o          : out t_wishbone_device_descriptor;
+      xlx_cclk_o      : out std_logic := '0';
+      xlx_din_o       : out std_logic;
+      xlx_program_b_o : out std_logic := '1';
+      xlx_init_b_i    : in  std_logic;
+      xlx_done_i      : in  std_logic;
+      xlx_suspend_o   : out std_logic;
+      xlx_m_o         : out std_logic_vector(1 downto 0);
+      boot_trig_p1_o  : out std_logic;
+      boot_exit_p1_o  : out std_logic;
+      boot_en_i       : in  std_logic;
+      gpio_o          : out std_logic_vector(7 downto 0));
+  end component;
+
+  signal VME_DATA_o_int                    : std_logic_vector(31 downto 0);
+  signal vme_dtack_oe_int, VME_DTACK_n_int : std_logic;
+  signal vme_data_dir_int                  : std_logic;
+  signal VME_DATA_OE_N_int                 : std_logic;
+
+  signal wb_vme_in  : t_wishbone_master_out;
+  signal wb_vme_out : t_wishbone_master_in;
+
+  signal passive : std_logic := '0';
+  signal gpio    : std_logic_vector(7 downto 0);
+
+
+-- bootloader is active right after bootup
+  signal boot_en                    : std_logic := '1';
+  signal boot_trig_p1, boot_exit_p1 : std_logic;
+
+  component chipscope_ila
+    port (
+      CONTROL : inout std_logic_vector(35 downto 0);
+      CLK     : in    std_logic;
+      TRIG0   : in    std_logic_vector(31 downto 0);
+      TRIG1   : in    std_logic_vector(31 downto 0);
+      TRIG2   : in    std_logic_vector(31 downto 0);
+      TRIG3   : in    std_logic_vector(31 downto 0));
+  end component;
+
+  component chipscope_icon
+    port (
+      CONTROL0 : inout std_logic_vector (35 downto 0));
+  end component;
+
+
+  signal CONTROL : std_logic_vector(35 downto 0);
+  signal CLK     : std_logic;
+  signal TRIG0   : std_logic_vector(31 downto 0);
+  signal TRIG1   : std_logic_vector(31 downto 0);
+  signal TRIG2   : std_logic_vector(31 downto 0);
+  signal TRIG3   : std_logic_vector(31 downto 0);
+
+  signal boot_config_int : std_logic;
+  signal erase_afpga_n, erase_afpga_n_d0     : std_logic;
+  
+  signal pllout_clk_fb_sys, pllout_clk_sys,clk_sys : std_logic;
+  
+begin
+
+  cmp_dmtd_clk_pll : PLL_BASE
+    generic map (
+      BANDWIDTH          => "OPTIMIZED",
+      CLK_FEEDBACK       => "CLKFBOUT",
+      COMPENSATION       => "INTERNAL",
+      DIVCLK_DIVIDE      => 1,
+      CLKFBOUT_MULT      => 50,
+      CLKFBOUT_PHASE     => 0.000,
+      CLKOUT0_DIVIDE     => 12,         -- 62.5 MHz
+      CLKOUT0_PHASE      => 0.000,
+      CLKOUT0_DUTY_CYCLE => 0.500,
+      CLKOUT1_DIVIDE     => 16,         -- 62.5 MHz
+      CLKOUT1_PHASE      => 0.000,
+      CLKOUT1_DUTY_CYCLE => 0.500,
+      CLKOUT2_DIVIDE     => 8,
+      CLKOUT2_PHASE      => 0.000,
+      CLKOUT2_DUTY_CYCLE => 0.500,
+      CLKIN_PERIOD       => 50.0,
+      REF_JITTER         => 0.016)
+    port map (
+      CLKFBOUT => pllout_clk_fb_sys,
+      CLKOUT0  => pllout_clk_sys,
+      CLKOUT1  => open,                 --pllout_clk_sys,
+      CLKOUT2  => open,
+      CLKOUT3  => open,
+      CLKOUT4  => open,
+      CLKOUT5  => open,
+      LOCKED   => open,
+      RST      => '0',
+      CLKFBIN  => pllout_clk_fb_sys,
+      CLKIN    => lclk_n_i);
+
+  cmp_clk_sys_buf : BUFG
+    port map (
+      O => clk_sys,
+      I => pllout_clk_sys);
+
+  
+  chipscope_ila_1 : chipscope_ila
+    port map (
+      CONTROL => CONTROL,
+      CLK     => clk_sys,
+      TRIG0   => TRIG0,
+      TRIG1   => TRIG1,
+      TRIG2   => TRIG2,
+      TRIG3   => TRIG3);
+
+  chipscope_icon_1 : chipscope_icon
+    port map (
+      CONTROL0 => CONTROL);
+
+  TRIG0(31 downto 1) <= VME_ADDR_b;
+  TRIG1(31 downto 0) <= VME_DATA_b;
+  TRIG2(5 downto 0)  <= VME_AM_i;
+  trig2(7 downto 6)  <= VME_DS_n_i;
+  trig2(13 downto 8) <= VME_GA_i;
+  trig2(14)          <= VME_DTACK_n_o;
+  trig2(15)          <= VME_DTACK_oe_o;
+  trig2(16)          <= VME_LWORD_n_b;
+  trig2(17)          <= VME_WRITE_n_i;
+  trig2(18)          <= VME_AS_n_i;
+  trig2(19)          <= VME_DATA_DIR_o;
+  trig2(20)          <= VME_DATA_OE_N_o;
+  trig2(21)          <= VME_addr_DIR_o;
+  trig2(22)          <= VME_addr_OE_N_o;
+  trig2(23)          <= rst_n_i;
+  trig2(24)          <= '1';
+  trig2(25)          <= VME_RST_n_i;
+  trig2(26) <= passive;
+
+
+  U_MiniVME : xmini_vme
+    generic map (
+      g_user_csr_start => resize(x"70000", 21),
+      g_user_csr_end   => resize(x"70020", 21))
+    port map (
+      clk_sys_i       => clk_sys,
+      rst_n_i         => rst_n_i,
+      passive_i       => '0',
+      VME_RST_n_i     => VME_RST_n_i,
+      VME_AS_n_i      => VME_AS_n_i,
+      VME_LWORD_n_i   => VME_LWORD_n_b,
+      VME_WRITE_n_i   => VME_WRITE_n_i,
+      VME_DS_n_i      => VME_DS_n_i,
+      VME_GA_i        => VME_GA_i,
+      VME_DTACK_n_o   => VME_DTACK_n_int,
+      VME_DTACK_OE_o  => vme_dtack_oe_int,
+      VME_AM_i        => VME_AM_i,
+      VME_ADDR_i      => VME_ADDR_b,
+      VME_DATA_b_i    => VME_DATA_b,
+      VME_DATA_b_o    => VME_DATA_o_int,
+      VME_DATA_DIR_o  => vme_data_dir_int,
+      VME_DATA_OE_N_o => VME_DATA_OE_N_int,
+      master_o        => wb_vme_in,
+      master_i        => wb_vme_out);
+
+  U_Xilinx_Loader : xwb_xilinx_fpga_loader
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+    port map (
+      clk_sys_i       => clk_sys,
+      rst_n_i         => rst_n_i,
+      slave_i         => wb_vme_in,
+      slave_o         => wb_vme_out,
+      xlx_cclk_o      => boot_clk_o,
+      xlx_din_o       => boot_dout_o,
+      xlx_program_b_o => boot_config_int,
+      xlx_init_b_i    => boot_status_i,
+      xlx_done_i      => boot_done_i,
+      xlx_suspend_o   => open,
+      xlx_m_o         => open,
+      boot_trig_p1_o  => boot_trig_p1,
+      boot_exit_p1_o  => boot_exit_p1,
+      boot_en_i       => boot_en,
+      gpio_o          => gpio);
+
+  U_Extend_Erase_Pulse : gc_extend_pulse
+    generic map (
+      g_width => 100)
+    port map (
+      clk_i      => clk_sys,
+      rst_n_i    => rst_n_i,
+      pulse_i    => boot_trig_p1,
+      extended_o => erase_afpga_n);
+
+  boot_config_o <= boot_config_int and (not erase_afpga_n);
+  
+  p_enable_disable_bootloader : process(clk_sys)
+  begin
+    if rising_edge(clk_sys) then
+
+      erase_afpga_n_d0 <= erase_afpga_n;
+      
+      if(erase_afpga_n = '0' and erase_afpga_n_d0 = '1') then
+        boot_en <= '1';
+      elsif(boot_exit_p1 = '1') then
+        boot_en <= '0';
+      end if;
+    end if;
+  end process;
+
+  passive <= not boot_en;
+
+  
+  VME_ADDR_b <= (others => 'Z');
+
+  VME_DTACK_n_o   <= VME_DTACK_n_int   when passive = '0'                                                          else 'Z';
+  vme_dtack_oe_o  <= vme_dtack_oe_int  when passive = '0'                                                          else 'Z';
+  VME_DATA_DIR_o  <= vme_data_dir_int  when passive = '0'                                                          else 'Z';
+  VME_DATA_OE_N_o <= VME_DATA_OE_N_int when passive = '0'                                                          else 'Z';
+  VME_DATA_b      <= VME_DATA_o_int    when (passive = '0' and VME_DATA_OE_N_int = '0' and vme_data_dir_int = '1') else (others => 'Z');
+  VME_ADDR_OE_N_o <= '0'               when passive = '0'                                                          else 'Z';
+  VME_ADDR_DIR_o  <= '0'               when passive = '0'                                                          else 'Z';
+  VME_BERR_o      <= 'Z';
+  VME_LWORD_n_b   <= 'Z';
+
+  debugled_o(1) <= gpio(0);
+  debugled_o(2) <= boot_en;
+
+  
+end rtl;
+
+