With project evergreen's CI/CD templates and includes, it is much easier
to build CI/Cd of other projects with simple .gitlab-ci.yml file.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Resolve "automate svec-base version assignment"

Closes #20

See merge request be-cem-edl/fec/hardware-modules/svec!16

Resolve "Make v3.0.0 release"

Closes #15

See merge request be-cem-edl/fec/hardware-modules/svec!12

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Resolve "fix licences"

Closes #17

See merge request be-cem-edl/fec/hardware-modules/svec!14

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Resolve "remove sdbfs"

Closes #16

See merge request be-cem-edl/fec/hardware-modules/svec!13

We never used SDBFS (we never programmed the flash), nor we plan to use
it in the future.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Resolve "If not used remove the rtl/golden"

Closes #5

See merge request be-cem-edl/fec/hardware-modules/svec!6

Resolve "rename sysfs attribute for firmware loading"

Closes #14

See merge request be-cem-edl/fec/hardware-modules/svec!10

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Commited chipscope files were anyway for the 150T FPGA (AFPGA), not for the small SFPGA

It is not possible to run this anymore, among other things it depends on hdl/sim/flash/M25P128.v,
which in turns depends on a missing file (include/DevParam.h).

If we really need it we can try to restore it and revive it one day, but the SFPGA bootloader has
been stable for years as it is.

These files, when needed are now available from dependencies in hdl/ip_cores.

(for example, ddr memory model can be found in ddr controller project).

There were also some obsolete testbenches in here.

These are obsolete

Resolve "Fix dependencies / submodules"

Closes #7

See merge request be-cem-edl/fec/hardware-modules/svec!8

Merge branch '12-svec-fmc-carrier-svec-vme-slot-fpga-cannot-create-debugfs-file-csr_regs-0' into 'master'

Resolve "svec-fmc-carrier svec-vme.<slot>-fpga: Cannot create debugfs file "csr_regs" (0)"

Closes #12

See merge request be-cem-edl/fec/hardware-modules/svec!9

After this:
	commit 156b03ec ("software: kernel:
	svec-core-fpga: Update API 'debugfs_create_regset32'")

The pointer `svec_fpga->dbg_csr` was never initialized. And when we
check it for "IS_ERR_ORNULL", we get false failure.

Thus, put conditional directive for this API update.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Some constraints were commented-out by Tristan because the golden
did not use them and Xilinx ISE was producing errors because of that.

This commits re-enables all constraints and enables an option in the Translate step of the golden
design to demote empty timegroups to warnings instead.

The xilinx-generated DDR ip-cores do not use self-refresh (the 'enter self-refresh' signal is tied
to ground). This constraint as such is not needed and many times it creates issues because ISE will
remove the signal and then Translate step will fail because it cannot match the constraint to a
signal.

Resolve "Removing "svec_fmc_carrier" module results in OOPS"

Closes #9

See merge request be-cem-edl/fec/hardware-modules/svec!7

Resolve "copy relevant documentation from texi to sphinx"

Closes #4

See merge request be-cem-edl/fec/hardware-modules/svec!5

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

If the driver is not able to create "dbg_dir", the pointer should be set
as NULL and should not be left with some error-pointer.
Reported-by: Federico Vaga <federico.vaga@cern.ch>
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>