Commits · 6d407b82e477ed6bc76b42d32dba2540e14163f1 · Projects / Simple VME FMC Carrier SVEC

03 Feb, 2021 29 commits
- Check CYC as well as STB in a WB cycle · 6d407b82
  Dimitris Lampridis authored Nov 06, 2017
  
  6d407b82
- Fix minor syntax error in header comments · 02b5ad67
  Dimitris Lampridis authored Nov 06, 2017
  
  02b5ad67
- vmecore_test: increase size of pattern area. · 18a8bc29
  Tristan Gingold authored Oct 20, 2017
  
  18a8bc29
- Fix minor style issues. · c829896c
  Tristan Gingold authored Oct 11, 2017
  
  c829896c
- Add top level file for svec vmecore. · 49be322c
  Tristan Gingold authored Oct 05, 2017
  
  49be322c
- vmecore_test: add copyright headers. · 4b447880
  Tristan Gingold authored Oct 02, 2017
  
  4b447880
- test_vme.c: improve output of DMA tests. · bfc53781
  Tristan Gingold authored Oct 02, 2017
  
  bfc53781
- vmecore test: test BERR. · 57fdecdc
  Tristan Gingold authored Sep 29, 2017
  
  57fdecdc
- test_vme: check DMA writes. · d03ffd6d
  Tristan Gingold authored Sep 28, 2017
  
  d03ffd6d
- fpga to test the vme64xcore · 0a4c94b9
  Tristan Gingold authored Sep 28, 2017
  
  0a4c94b9
- Remove deprecated svec_v0 afpga template · 6dcf4bfc
  Tristan Gingold authored Sep 19, 2017
  
  6dcf4bfc
- removed binary gatawares from the repo · ee01de97
  Tomasz Wlostowski authored Jan 16, 2014
  
  ee01de97
- added SVEC default bitstreams that come preloaded with every SVEC card · 5f509d96
  Evangelia Gousiou authored Jul 31, 2013
  
  5f509d96
- Remove outdated/unused SVFC files from SVEC dir. · 2fdf1e2a
  Matthieu Cattin authored Oct 02, 2012
  
  2fdf1e2a
- Cleanup circuit_board sir, add VME P2 tester design. · 3a637780
  Matthieu Cattin authored Oct 02, 2012
```
 - Rename SVEC dir into EDA-02530-V0-0_SVEC.
 - Remove SVFC dir.
 - Add VME P2 tester Altium design (P2_tester).
```
  3a637780
- fixed cosmetic issues · 7e7251a5
  Greg authored May 01, 2012
  
  7e7251a5
- fixed issues from 26.04.2012 · e5a5a68c
  Greg authored Apr 27, 2012
  
  e5a5a68c
- small cosmetic changes, updated with final version of CERN components · 45586cc9
  Greg authored Apr 23, 2012
  
  45586cc9
- added SATA power connector and optional USB connector for stand-alone operation.… · ff58eda2
  Greg authored Apr 16, 2012
```
added SATA power connector and optional USB connector for stand-alone operation. Added optional UFL clock connector to supply custom FMC cards requiring precise synchronization
```
  ff58eda2
- almost final verion - still needs to replace non-CERN components with right ones. · f7ab6632
  Greg authored Apr 13, 2012
  
  f7ab6632
- just backup of 2 days of work · c3a354a7
  Greg authored Apr 13, 2012
  
  c3a354a7
- --no commit message · 9c257bad
  Greg authored Mar 29, 2012
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--no commit message
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  9c257bad
- final routing, polygons, DDR length matching and tracks clean out done · 3ebef17e
  Greg authored Mar 29, 2012
  
  3ebef17e
- 100% routing done, still needs some tracks clean out and pouring the polygons · 59ce0aa0
  Greg authored Mar 25, 2012
  
  59ce0aa0
- 99% of PCB done, schematics updated with post-routing changes · 0e2d562c
  Greg authored Mar 24, 2012
  
  0e2d562c
- --no commit message · 696a5c54
  Greg authored Feb 09, 2012
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--no commit message
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  696a5c54
- --no commit message · f00855d4
  Greg authored Feb 08, 2012
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--no commit message
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  f00855d4
- --no commit message · 7a2d00e4
  Greg authored Feb 07, 2012
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--no commit message
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  7a2d00e4
- some bugs fixed, reduced number of different components · c17b4d54
  Greg authored Jan 25, 2012
  
  c17b4d54
02 Feb, 2021 2 commits
- Add data pages for DMA (so that it supports MBLT). · 4f3c6cb4
  Tristan Gingold authored Feb 02, 2021
```
The memory map of the svec base is therefore changed.
```
  4f3c6cb4
- svec_base_wr.vhd: add a workaround for planAhead · 908a1b22
  Tristan Gingold authored Feb 02, 2021
```
so that it properly computes dependencies
```
  908a1b22
05 Jan, 2021 5 commits
- Merge branch 'release/v1.5.2' into master · c15d15c7
  Federico Vaga authored Jan 05, 2021
  
  c15d15c7
- hdl: set version 1.5.2 · 730b8339
  Federico Vaga authored Jan 05, 2021
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  730b8339
- update CHANGELOG · 5d33f760
  Federico Vaga authored Jan 05, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  5d33f760
- sw: add tool to read FPGA version · 0b12a113
  Federico Vaga authored Jan 05, 2021
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  0b12a113
- sw: create userspace API header file · e7859e87
  Federico Vaga authored Jan 05, 2021
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  e7859e87
26 Nov, 2020 3 commits
- doc: change theme to RTD · 1974d2cc
  Federico Vaga authored Nov 26, 2020
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  1974d2cc
- doc: show only one version of the fixed fields · dde52369
  Federico Vaga authored Nov 26, 2020
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  dde52369
- doc: get version from git · 9a059998
  Federico Vaga authored Nov 26, 2020
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  9a059998
24 Nov, 2020 1 commit

Merge tag 'v1.5.1' into develop · da4ccd8a

Federico Vaga authored Nov 24, 2020

1.5.1 - 2020-11-24
==================
Fixed
-----
- sw: NULL pointer at load time when using the SPI controller
- sw: remove old unload procedure that causes BUG_ON to be triggered
  without valid reasons

da4ccd8a