- 16 Aug, 2023 4 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 24 Jul, 2023 1 commit
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Federico Vaga authored
Resolve "Use project evergreen's template for driver building and validation" Closes #26 See merge request be-cem-edl/fec/hardware-modules/svec!18
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- 20 Jul, 2023 2 commits
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Vaibhav Gupta authored
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
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Vaibhav Gupta authored
With project evergreen's CI/CD templates and includes, it is much easier to build CI/Cd of other projects with simple .gitlab-ci.yml file. Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
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- 19 Jan, 2023 1 commit
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Dimitris Lampridis authored
Resolve "automate svec-base version assignment" Closes #20 See merge request be-cem-edl/fec/hardware-modules/svec!16
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- 15 Dec, 2022 1 commit
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Dimitris Lampridis authored
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- 05 Dec, 2022 5 commits
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Dimitris Lampridis authored
Resolve "Make v3.0.0 release" Closes #15 See merge request be-cem-edl/fec/hardware-modules/svec!12
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 02 Dec, 2022 5 commits
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Federico Vaga authored
Resolve "fix licences" Closes #17 See merge request be-cem-edl/fec/hardware-modules/svec!14
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Resolve "remove sdbfs" Closes #16 See merge request be-cem-edl/fec/hardware-modules/svec!13
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Federico Vaga authored
We never used SDBFS (we never programmed the flash), nor we plan to use it in the future. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Resolve "If not used remove the rtl/golden" Closes #5 See merge request be-cem-edl/fec/hardware-modules/svec!6
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- 01 Dec, 2022 14 commits
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Federico Vaga authored
Resolve "rename sysfs attribute for firmware loading" Closes #14 See merge request be-cem-edl/fec/hardware-modules/svec!10
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Commited chipscope files were anyway for the 150T FPGA (AFPGA), not for the small SFPGA
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Dimitris Lampridis authored
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Dimitris Lampridis authored
It is not possible to run this anymore, among other things it depends on hdl/sim/flash/M25P128.v, which in turns depends on a missing file (include/DevParam.h). If we really need it we can try to restore it and revive it one day, but the SFPGA bootloader has been stable for years as it is.
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Dimitris Lampridis authored
These files, when needed are now available from dependencies in hdl/ip_cores. (for example, ddr memory model can be found in ddr controller project). There were also some obsolete testbenches in here.
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Dimitris Lampridis authored
These are obsolete
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- 30 Nov, 2022 7 commits
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Dimitris Lampridis authored
Resolve "Fix dependencies / submodules" Closes #7 See merge request be-cem-edl/fec/hardware-modules/svec!8
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Federico Vaga authored
Merge branch '12-svec-fmc-carrier-svec-vme-slot-fpga-cannot-create-debugfs-file-csr_regs-0' into 'master' Resolve "svec-fmc-carrier svec-vme.<slot>-fpga: Cannot create debugfs file "csr_regs" (0)" Closes #12 See merge request be-cem-edl/fec/hardware-modules/svec!9
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Vaibhav Gupta authored
After this: commit 156b03ec ("software: kernel: svec-core-fpga: Update API 'debugfs_create_regset32'") The pointer `svec_fpga->dbg_csr` was never initialized. And when we check it for "IS_ERR_ORNULL", we get false failure. Thus, put conditional directive for this API update. Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Some constraints were commented-out by Tristan because the golden did not use them and Xilinx ISE was producing errors because of that. This commits re-enables all constraints and enables an option in the Translate step of the golden design to demote empty timegroups to warnings instead.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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