the FPGA board:

SW5 | SW4 | SW3 | SW2 | SW1 | SW0 ||
 0  |  0  |  0  |  0  |  0  |  0  || division by 1  (3 GHz) for MAX IV ; no PLL
 0  |  0  |  0  |  0  |  0  |  1  || division by 1  (2.8 GHz) ; with PLL
 0  |  0  |  0  |  0  |  1  |  0  || division by 8  (352 MHz) ; TEMPO
 0  |  0  |  0  |  0  |  1  |  1  || division by 32 (88 MHz)  ; CRISTAL
 0  |  0  |  0  |  1  |  0  |  0  || division by 64 (44 MHz)  ; ODE

 On branch development

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	modified:   fpga/sources/top.vhdl