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urv-core
Commit 0af7cf34 authored by Tristan Gingold's avatar Tristan Gingold
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rtl/xurv_core.vhd: remove dm_ready_i (cleanup)

parent 1a9e0f86
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rtl/xurv_core.vhd
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......@@ -69,7 +69,6 @@ architecture wrapper of xurv_core is
dm_data_s_o : out std_logic_vector(31 downto 0);
dm_data_l_i : in std_logic_vector(31 downto 0);
dm_data_select_o : out std_logic_vector(3 downto 0);
dm_ready_i : in std_logic;
dm_store_o : out std_logic;
dm_load_o : out std_logic;
dm_load_done_i : in std_logic;
......@@ -116,7 +115,7 @@ architecture wrapper of xurv_core is
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done, dm_ready : std_logic;
signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;
signal dm_cycle_in_progress, dm_is_wishbone : std_logic;
......@@ -231,7 +230,6 @@ begin
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
im_addr_muxed <= ha_im_addr when ha_im_access = '1' else im_addr(g_address_bits-1 downto 0);
dm_ready <= '1';
cpu_core : urv_cpu
port map (
......@@ -245,7 +243,6 @@ begin
dm_data_s_o => dm_data_s,
dm_data_l_i => dm_data_l,
dm_data_select_o => dm_data_select,
dm_ready_i => dm_ready,
dm_store_o => dm_store,
dm_load_o => dm_load,
dm_load_done_i => dm_load_done,
......
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