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urv-core
Commit a102497b authored by Tristan Gingold's avatar Tristan Gingold
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rtl: add fault output (in case of unfixable ecc error)

parent 01d9672d
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Showing with 27 additions and 14 deletions
rtl/urv_cpu.v
View file @ a102497b
...@@ -40,16 +40,19 @@ module urv_cpu ...@@ -40,16 +40,19 @@ module urv_cpu
parameter g_with_compressed_insns = 0 parameter g_with_compressed_insns = 0
) )
( (
input clk_i, input clk_i,
input rst_i, input rst_i,
input irq_i, input irq_i,
// For ECC double error
output fault_o,
// instruction mem I/F // instruction mem I/F
output [31:0] im_addr_o, output [31:0] im_addr_o,
output im_rd_o, output im_rd_o,
input [31:0] im_data_i, input [31:0] im_data_i,
input im_valid_i, input im_valid_i,
// data mem I/F // data mem I/F
// The interface is pipelined: store/load are asserted for one cycle // The interface is pipelined: store/load are asserted for one cycle
...@@ -59,10 +62,10 @@ module urv_cpu ...@@ -59,10 +62,10 @@ module urv_cpu
input [31:0] dm_data_l_i, input [31:0] dm_data_l_i,
output [3:0] dm_data_select_o, output [3:0] dm_data_select_o,
output dm_store_o, output dm_store_o,
output dm_load_o, output dm_load_o,
input dm_load_done_i, input dm_load_done_i,
input dm_store_done_i, input dm_store_done_i,
// Debug I/F // Debug I/F
// Debug mode is entered either when dbg_force_i is set, or when the ebreak // Debug mode is entered either when dbg_force_i is set, or when the ebreak
...@@ -73,14 +76,14 @@ module urv_cpu ...@@ -73,14 +76,14 @@ module urv_cpu
// In debug mode, instructions are executed from dbg_insn_i. // In debug mode, instructions are executed from dbg_insn_i.
// As instructions are always fetched, they must be always valid. Use // As instructions are always fetched, they must be always valid. Use
// a nop (0x13) if nothing should be executed. // a nop (0x13) if nothing should be executed.
input dbg_force_i, input dbg_force_i,
output dbg_enabled_o, output dbg_enabled_o,
input [31:0] dbg_insn_i, input [31:0] dbg_insn_i,
input dbg_insn_set_i, input dbg_insn_set_i,
output dbg_insn_ready_o, output dbg_insn_ready_o,
input [31:0] dbg_mbx_data_i, input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i, input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o output [31:0] dbg_mbx_data_o
); );
...@@ -95,6 +98,8 @@ module urv_cpu ...@@ -95,6 +98,8 @@ module urv_cpu
wire w_stall_req; wire w_stall_req;
wire x_stall_req; wire x_stall_req;
wire x_fault;
// X1->F stage interface // X1->F stage interface
wire [31:0] x2f_pc_bra; wire [31:0] x2f_pc_bra;
wire x2f_bra; wire x2f_bra;
...@@ -310,6 +315,8 @@ module urv_cpu ...@@ -310,6 +315,8 @@ module urv_cpu
.x_kill_i(x_kill), .x_kill_i(x_kill),
.x_stall_req_o(x_stall_req), .x_stall_req_o(x_stall_req),
.x_fault_o(x_fault),
// from register file // from register file
.rf_rs1_value_i(x_rs1_value), .rf_rs1_value_i(x_rs1_value),
.rf_rs2_value_i(x_rs2_value), .rf_rs2_value_i(x_rs2_value),
...@@ -423,6 +430,8 @@ module urv_cpu ...@@ -423,6 +430,8 @@ module urv_cpu
.rf_rd_write_o(rf_rd_write) .rf_rd_write_o(rf_rd_write)
); );
assign fault_o = x_fault & g_with_ecc;
// Built-in timer // Built-in timer
generate generate
if (g_timer_frequency > 0) if (g_timer_frequency > 0)
......
rtl/urv_exec.v
View file @ a102497b
...@@ -37,6 +37,8 @@ module urv_exec ...@@ -37,6 +37,8 @@ module urv_exec
input x_kill_i, input x_kill_i,
output reg x_stall_req_o, output reg x_stall_req_o,
// Unfixable ecc error
output reg x_fault_o,
input [31:0] d_pc_i, input [31:0] d_pc_i,
input [4:0] d_rd_i, input [4:0] d_rd_i,
...@@ -513,6 +515,7 @@ module urv_exec ...@@ -513,6 +515,7 @@ module urv_exec
w_load_o <= 0; w_load_o <= 0;
w_store_o <= 0; w_store_o <= 0;
w_ecc_flip_o <= 2'b0; w_ecc_flip_o <= 2'b0;
x_fault_o <= 0;
// Values so that 0 could be written to register 0. // Values so that 0 could be written to register 0.
w_rd_value_o <= 0; w_rd_value_o <= 0;
w_rd_o <= 0; w_rd_o <= 0;
...@@ -531,6 +534,7 @@ module urv_exec ...@@ -531,6 +534,7 @@ module urv_exec
w_rd_o <= d_rd_i; w_rd_o <= d_rd_i;
w_rd_value_o <= rd_value; w_rd_value_o <= rd_value;
w_ecc_flip_o <= {2{d_is_write_ecc_i}} & rs2[1:0]; w_ecc_flip_o <= {2{d_is_write_ecc_i}} & rs2[1:0];
x_fault_o <= d_is_fix_ecc_i & rf_rs1_ecc_err_i & rf_rs2_ecc_err_i;
f_branch_take <= branch_take && !x_kill_i && d_valid_i; f_branch_take <= branch_take && !x_kill_i && d_valid_i;
f_dbg_toggle_o <= g_with_hw_debug && d_is_ebreak_i && !x_kill_i && d_valid_i; f_dbg_toggle_o <= g_with_hw_debug && d_is_ebreak_i && !x_kill_i && d_valid_i;
......
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