Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
U
urv-core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
3
Issues
3
List
Board
Labels
Milestones
Merge Requests
2
Merge Requests
2
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
urv-core
Commits
b1d08d0e
Commit
b1d08d0e
authored
Feb 11, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add urv_pkg.vhd
parent
232a62b5
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
57 additions
and
1 deletion
+57
-1
Manifest.py
rtl/Manifest.py
+2
-1
urv_pkg.vhd
rtl/urv_pkg.vhd
+55
-0
No files found.
rtl/Manifest.py
View file @
b1d08d0e
...
...
@@ -11,4 +11,5 @@ files = [ "urv_cpu.v",
"urv_timer.v"
,
"urv_exceptions.v"
,
"urv_iram.v"
,
"xurv_core.vhd"
];
"xurv_core.vhd"
,
"urv_pkg.vhd"
]
rtl/urv_pkg.vhd
0 → 100644
View file @
b1d08d0e
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
urv_pkg
is
component
urv_cpu
is
generic
(
g_timer_frequency
:
natural
:
=
1000
;
g_clock_frequency
:
natural
:
=
100000000
;
g_with_hw_div
:
natural
:
=
1
;
g_with_hw_mulh
:
natural
:
=
1
;
g_with_hw_debug
:
natural
:
=
0
;
g_with_compressed_insns
:
natural
:
=
0
;
g_debug_breakpoints
:
natural
:
=
6
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
irq_i
:
in
std_logic
;
-- instruction mem I/F
im_addr_o
:
out
std_logic_vector
(
31
downto
0
);
im_data_i
:
in
std_logic_vector
(
31
downto
0
);
im_valid_i
:
in
std_logic
;
-- data mem I/F
-- The interface is pipelined: store/load are asserted for one cycle
-- and then store_done/load_done is awaited.
dm_addr_o
:
out
std_logic_vector
(
31
downto
0
);
dm_data_s_o
:
out
std_logic_vector
(
31
downto
0
);
dm_data_l_i
:
in
std_logic_vector
(
31
downto
0
);
dm_data_select_o
:
out
std_logic_vector
(
3
downto
0
);
dm_store_o
:
out
std_logic
;
dm_load_o
:
out
std_logic
;
dm_load_done_i
:
in
std_logic
;
dm_store_done_i
:
in
std_logic
;
-- Debug I/F
-- Debug mode is entered either when dbg_force_i is set, or when the ebreak
-- instructions is executed. Debug mode is left when the ebreak instruction
-- is executed (from the dbg_insn_i port).
-- When debug mode is entered, dbg_enabled_o is set. This may not be
-- immediate. Interrupts are disabled in debug mode.
-- In debug mode, instructions are executed from dbg_insn_i.
-- As instructions are always fetched, they must be always valid. Use
-- a nop (0x13) if nothing should be executed.
dbg_force_i
:
in
std_logic
;
dbg_enabled_o
:
out
std_logic
;
dbg_insn_i
:
in
std_logic_vector
(
31
downto
0
);
dbg_insn_set_i
:
in
std_logic
;
dbg_insn_ready_o
:
out
std_logic
;
dbg_mbx_data_i
:
in
std_logic_vector
(
31
downto
0
);
dbg_mbx_write_i
:
in
std_logic
;
dbg_mbx_data_o
:
out
std_logic_vector
(
31
downto
0
));
end
component
;
end
urv_pkg
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment