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Commit de5044f0 authored by Shareef Jalloq's avatar Shareef Jalloq
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feat[riscof]: adding riscof arch tests

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.gitignore
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/build/
.vscode
.venv
docs/build
\ No newline at end of file
docs/build
__pycache__
tb/riscof/sail-riscv
docs/source/index.rst
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......@@ -11,6 +11,7 @@ Welcome to uRV's documentation!
:caption: Contents:
getting_started.rst
riscof.rst
Indices and tables
==================
......
docs/source/riscof.rst 0 → 100644
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.. Headings guide:
# with overline, for parts
* with overline, for chapters
= for sections
- for subsections
^ for subsubsections
" for paragraphs
######
RISCOF
######
************
Dependencies
************
The following instructions assume you are using Ubuntu, update as necessary.
.. code-block::
sudo apt-get install git help2man perl python3 \
make autoconf g++ flex bison ccache pkg-config \
libgoogle-perftools-dev numactl perl-doc \
libfl2 libfl-dev zlib1g zlib1g-dev \
opam libgmp-dev z3 srecord
Verilator
=========
Install Verilator from source using a recent 5.x tag.
.. code-block::
git clone https://github.com/verilator/verilator
cd verilator
git checkout v5.020
./configure [--prefix=/opt/verilator/v5.020]
make -j `nproc`
make install
export PATH=/opt/verilator/v5.020/bin:$PATH
Sail
====
Install the Sail language which is used for ISA architecture modelling.
.. code-block::
opam init -y --disable-sandboxing
opam switch create 5.1.0
opam install sail -y
eval $(opam config env)
.. admonition::Note
Make sure all tools are available on your `PATH`.
Sail-RISCV
==========
Clone and build the RISCV model that will be used as the reference model.
.. code-block::
git clone https://github.com/riscv/sail-riscv.git
cd sail-riscv
ARCH=RV32 make c_emulator/riscv_sim_RV32
export PATH=$(realpath c_emulator):$PATH
RISCV GNU Compiler
==================
.. code-block::
wget https://ohwr.org/project/wrpc-sw/wikis/uploads/9f9224d2249848ed3e854636de9c08dc/riscv-11.2-small.tgz
tar zxf riscv-11.2-small.tgz -C /opt/riscv
export PATH=/opt/riscv/11.2-small/bin:$PATH
**********************
Running The Test Suite
**********************
.. code-block::
riscof arch-test --clone
riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
\ No newline at end of file
lint/urv_cpu.vlt
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......@@ -8,6 +8,10 @@ lint_off --rule CASEINCOMPLETE --file "*/urv_exceptions.v"
lint_off --rule UNUSED --file "*/urv_*.v"
lint_off --rule WIDTH --file "*/urv_multiply.v"
lint_off --rule GENUNNAMED --file "*/urv_*.v"
lint_off --rule WIDTHTRUNC --file "*/urv_*.v"
lint_off --rule WIDTHEXPAND --file "*/urv_*.v"
lint_off --rule IMPLICIT --file "*/urv_*.v"
lint_off --rule UNDRIVEN --file "*/urv_*.v"
// Use of integer parameter causes width mismatch; ignore.
lint_off --rule WIDTH --file "*/urv_decode.v" --match "*g_with_hw_mul*"
......
requirements.txt
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......@@ -6,4 +6,7 @@ edalize
pre-commit
# Documentation
sphinx
\ No newline at end of file
sphinx
# RISCV Compliance
riscof
tb/riscof/config.ini 0 → 100644
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[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=plugin-sail_cSim
DUTPlugin=urv
DUTPluginPath=plugin-urv
[urv]
pluginpath=plugin-urv
ispec=plugin-urv/urv_isa.yaml
pspec=plugin-urv/urv_platform.yaml
target_run=1
[sail_cSim]
pluginpath=plugin-sail_cSim
tb/riscof/plugin-sail_cSim/__init__.py 0 → 100644
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from pkgutil import extend_path
__path__ = extend_path(__path__, __name__)
\ No newline at end of file
tb/riscof/plugin-sail_cSim/env/link.ld 0 → 100644
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OUTPUT_ARCH( "riscv" )
ENTRY(rvtest_entry_point)
SECTIONS
{
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.data.string : { *(.data.string)}
.bss : { *(.bss) }
_end = .;
}
tb/riscof/plugin-sail_cSim/env/model_test.h 0 → 100644
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#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H
#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
.align 8; .global fromhost; fromhost: .dword 0; \
.popsection; \
.align 8; .global begin_regstate; begin_regstate: \
.word 128; \
.align 8; .global end_regstate; end_regstate: \
.word 4;
//RV_COMPLIANCE_HALT
#define RVMODEL_HALT \
li x1, 1; \
write_tohost: \
sw x1, tohost, t5; \
j write_tohost;
#define RVMODEL_BOOT
//RV_COMPLIANCE_DATA_BEGIN
#define RVMODEL_DATA_BEGIN \
RVMODEL_DATA_SECTION \
.align 4;\
.global begin_signature; begin_signature:
//RV_COMPLIANCE_DATA_END
#define RVMODEL_DATA_END \
.align 4; .global end_signature; end_signature:
//RVTEST_IO_INIT
#define RVMODEL_IO_INIT
//RVTEST_IO_WRITE_STR
#define RVMODEL_IO_WRITE_STR(_R, _STR)
//RVTEST_IO_CHECK
#define RVMODEL_IO_CHECK()
//RVTEST_IO_ASSERT_GPR_EQ
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
//RVTEST_IO_ASSERT_SFPR_EQ
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
//RVTEST_IO_ASSERT_DFPR_EQ
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
#define RVMODEL_SET_MSW_INT
#define RVMODEL_CLEAR_MSW_INT
#define RVMODEL_CLEAR_MTIMER_INT
#define RVMODEL_CLEAR_MEXT_INT
#endif // _COMPLIANCE_MODEL_H
tb/riscof/plugin-sail_cSim/riscof_sail_cSim.py 0 → 100644
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import os
import re
import shutil
import subprocess
import shlex
import logging
import random
import string
from string import Template
import riscof.utils as utils
from riscof.pluginTemplate import pluginTemplate
import riscof.constants as constants
from riscv_isac.isac import isac
logger = logging.getLogger()
class sail_cSim(pluginTemplate):
__model__ = "sail_c_simulator"
__version__ = "0.5.0"
def __init__(self, *args, **kwargs):
sclass = super().__init__(*args, **kwargs)
config = kwargs.get('config')
if config is None:
logger.error("Config node for sail_cSim missing.")
raise SystemExit(1)
self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
self.pluginpath = os.path.abspath(config['pluginpath'])
self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV32"),
'64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV64")}
self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
self.make = config['make'] if 'make' in config else 'make'
logger.debug("SAIL CSim plugin initialised using the following configuration.")
for entry in config:
logger.debug(entry+' : '+config[entry])
return sclass
def initialise(self, suite, work_dir, archtest_env):
self.suite = suite
self.work_dir = work_dir
self.objdump_cmd = 'riscv{1}-elf-objdump -D {0} > {2};'
self.compile_cmd = 'riscv{1}-elf-gcc -march={0} \
-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles\
-T '+self.pluginpath+'/env/link.ld\
-I '+self.pluginpath+'/env/\
-I ' + archtest_env
def build(self, isa_yaml, platform_yaml):
ispec = utils.load_yaml(isa_yaml)['hart0']
self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
self.isa = 'rv' + self.xlen
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
if "I" in ispec["ISA"]:
self.isa += 'i'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "C" in ispec["ISA"]:
self.isa += 'c'
if "F" in ispec["ISA"]:
self.isa += 'f'
if "D" in ispec["ISA"]:
self.isa += 'd'
objdump = "riscv{0}-elf-objdump".format(self.xlen)
if shutil.which(objdump) is None:
logger.error(objdump+": executable not found. Please check environment setup.")
raise SystemExit(1)
compiler = "riscv{0}-elf-gcc".format(self.xlen)
if shutil.which(compiler) is None:
logger.error(compiler+": executable not found. Please check environment setup.")
raise SystemExit(1)
if shutil.which(self.sail_exe[self.xlen]) is None:
logger.error(self.sail_exe[self.xlen]+ ": executable not found. Please check environment setup.")
raise SystemExit(1)
if shutil.which(self.make) is None:
logger.error(self.make+": executable not found. Please check environment setup.")
raise SystemExit(1)
def runTests(self, testList, cgf_file=None):
if os.path.exists(self.work_dir+ "/Makefile." + self.name[:-1]):
os.remove(self.work_dir+ "/Makefile." + self.name[:-1])
make = utils.makeUtil(makefilePath=os.path.join(self.work_dir, "Makefile." + self.name[:-1]))
make.makeCommand = self.make + ' -j' + self.num_jobs
for file in testList:
testentry = testList[file]
test = testentry['test_path']
test_dir = testentry['work_dir']
test_name = test.rsplit('/',1)[1][:-2]
elf = 'ref.elf'
execute = "@cd "+testentry['work_dir']+";"
cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
execute+=compile_cmd+";"
execute += self.objdump_cmd.format(elf, self.xlen, 'ref.disass')
sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
cov_str = ' '
for label in testentry['coverage_labels']:
cov_str+=' -l '+label
if cgf_file is not None:
coverage_cmd = 'riscv_isac --verbose info coverage -d \
-t {0}.log --parser-name c_sail -o coverage.rpt \
--sig-label begin_signature end_signature \
--test-label rvtest_code_begin rvtest_code_end \
-e ref.elf -c {1} -x{2} {3};'.format(\
test_name, ' -c '.join(cgf_file), self.xlen, cov_str)
else:
coverage_cmd = ''
execute+=coverage_cmd
make.add_target(execute)
make.execute_all(self.work_dir)
tb/riscof/plugin-urv/env/link.ld 0 → 100644
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OUTPUT_ARCH( "riscv" )
ENTRY(rvtest_entry_point)
SECTIONS
{
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.data.string : { *(.data.string)}
.bss : { *(.bss) }
_end = .;
}
tb/riscof/plugin-urv/env/model_test.h 0 → 100644
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#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H
#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
.align 8; .global fromhost; fromhost: .dword 0; \
.popsection; \
.align 8; .global begin_regstate; begin_regstate: \
.word 128; \
.align 8; .global end_regstate; end_regstate: \
.word 4;
#define RVMODEL_HALT \
la a0, begin_signature; \
la a1, end_signature; \
sub a1, a1, a0; \
li a2, -8; \
beqz a1, compliance_quit; \
compliance_loop: \
lw a3, 0(a0); \
sw a3, 0(a2); \
addi a0, a0, 4; \
addi a1, a1, -4; \
bnez a1, compliance_loop; \
compliance_quit: \
li a0, 0; \
sw a0, 4(a2); \
j .
#define RVMODEL_BOOT
#define RVMODEL_DATA_BEGIN \
RVMODEL_DATA_SECTION \
.align 4; \
.global begin_signature; begin_signature:
#define RVMODEL_DATA_END \
.align 4; \
.global end_signature; end_signature:
#define RVMODEL_IO_INIT
#define RVMODEL_IO_WRITE_STR(_R, _STR)
#define RVMODEL_IO_CHECK()
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
#define RVMODEL_SET_MSW_INT
#define RVMODEL_CLEAR_MSW_INT
#define RVMODEL_CLEAR_MTIMER_INT
#define RVMODEL_CLEAR_MEXT_INT
#endif
tb/riscof/plugin-urv/riscof_urv.py 0 → 100644
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import os
import re
import shutil
import subprocess
import shlex
import logging
import random
import string
from string import Template
import sys
import riscof.utils as utils
import riscof.constants as constants
from riscof.pluginTemplate import pluginTemplate
logger = logging.getLogger()
class urv(pluginTemplate):
__model__ = "urv"
__version__ = "1.0.0"
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
config = kwargs.get('config')
self.config_dir = kwargs.get('config_dir')
# If the config node for this DUT is missing or empty. Raise an error. At minimum we need
# the paths to the ispec and pspec files
if config is None:
print("Please enter input file paths in configuration.")
raise SystemExit(1)
# In case of an RTL based DUT, this would be point to the final binary executable of your
# test-bench produced by a simulator (like verilator, vcs, incisive, etc). In case of an iss or
# emulator, this variable could point to where the iss binary is located. If 'PATH variable
# is missing in the config.ini we can hardcode the alternate here.
# Number of parallel jobs that can be spawned off by RISCOF
# for various actions performed in later functions, specifically to run the tests in
# parallel on the DUT executable. Can also be used in the build function if required.
self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
# Path to the directory where this python file is located. Collect it from the config.ini
self.pluginpath=os.path.abspath(config['pluginpath'])
# Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose
# to hardcode these here itself instead of picking it from the config.ini file.
self.isa_spec = os.path.abspath(config['ispec'])
self.platform_spec = os.path.abspath(config['pspec'])
#We capture if the user would like the run the tests on the target or
#not. If you are interested in just compiling the tests and not running
#them on the target, then following variable should be set to False
if 'target_run' in config and config['target_run']=='0':
self.target_run = False
else:
self.target_run = True
def initialise(self, suite, work_dir, archtest_env):
# capture the working directory. Any artifacts that the DUT creates should be placed in this
# directory. Other artifacts from the framework and the Reference plugin will also be placed
# here itself.
self.work_dir = work_dir
logger.info(f"work_dir={work_dir}")
# capture the architectural test-suite directory.
self.suite_dir = suite
# Note the march is not hardwired here, because it will change for each
# test. Similarly the output elf name and compile macros will be assigned later in the
# runTests function
self.compile_cmd = 'riscv{1}-elf-gcc -march={0} \
-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\
-T '+self.pluginpath+'/env/link.ld\
-I '+self.pluginpath+'/env/\
-I ' + archtest_env + ' {2} -o {3} {4}'
# Build the Verilator model of the DUT
build_urv = 'fusesoc run --build-root riscof_dut --target verilator_tb --build ohwr:urv:riscof'
utils.shellCommand(build_urv).run()
self.dut_exe = os.path.join(
self.config_dir,
'riscof_dut/ohwr_urv_riscof_0/verilator_tb-verilator/Vriscof_tb'
)
def build(self, isa_yaml, platform_yaml):
# load the isa yaml as a dictionary in python.
ispec = utils.load_yaml(isa_yaml)['hart0']
# capture the XLEN value by picking the max value in 'supported_xlen' field of isa yaml. This
# will be useful in setting integer value in the compiler string (if not already hardcoded);
self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
# for urv start building the '--isa' argument. the self.isa is dutnmae specific and may not be
# useful for all DUTs
self.isa = 'rv' + self.xlen
if "I" in ispec["ISA"]:
self.isa += 'i'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "F" in ispec["ISA"]:
self.isa += 'f'
if "D" in ispec["ISA"]:
self.isa += 'd'
if "C" in ispec["ISA"]:
self.isa += 'c'
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
def runTests(self, testList):
# We will iterate over each entry in the testList. Each entry node will be referred to by the
# variable testname.
for testname in testList:
logger.debug('Running Test: {0} on DUT'.format(testname))
# for each testname we get all its fields (as described by the testList format)
testentry = testList[testname]
# we capture the path to the assembly file of this test
test = testentry['test_path']
test_name = os.path.splitext(os.path.basename(test))[0]
# capture the directory where the artifacts of this test will be dumped/created.
test_dir = testentry['work_dir']
# name of the elf file after compilation of the test
elf = test_name + '.elf'
# name of the signature file as per requirement of RISCOF. RISCOF expects the signature to
# be named as DUT-<dut-name>.signature. The below variable creates an absolute path of
# signature file.
sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
# for each test there are specific compile macros that need to be enabled. The macros in
# the testList node only contain the macros/values. For the gcc toolchain we need to
# prefix with "-D". The following does precisely that.
compile_macros= ' -D' + " -D".join(testentry['macros'])
# collect the march string required for the compiler
marchstr = testentry['isa'].lower()
compile_cmd = self.compile_cmd.format(marchstr, self.xlen, test, elf, compile_macros)
utils.shellCommand(compile_cmd).run(cwd=test_dir)
objcopy_cmd = f'riscv32-elf-objcopy -O binary {elf} {test_name}.bin'
utils.shellCommand(objcopy_cmd).run(cwd=test_dir)
srec_cmd = f'srec_cat {test_name}.bin -binary -fill 0xFF -within {test_name}.bin -binary -range-pad 4 -byte-swap 4 -output {test_name}.hex -vmem 32'
utils.shellCommand(srec_cmd).run(cwd=test_dir)
if self.target_run:
if not os.path.exists(self.dut_exe):
raise RuntimeError('DUT executable does not exist')
# dut_run = [self.dut_exe, f'+initfile={test_name}.hex', f'+signature={sig_file}', '+waves']
dut_run = [self.dut_exe, f'+initfile={test_name}.hex', f'+signature={sig_file}']
utils.shellCommand(' '.join(dut_run)).run(cwd=test_dir)
# if target runs are not required then we simply exit as this point after running all
# the makefile targets.
if not self.target_run:
raise SystemExit
tb/riscof/plugin-urv/urv_isa.yaml 0 → 100644
View file @ de5044f0
hart_ids: [0]
hart0:
ISA: RV32IM
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x40001100
rv32:
accessible: true
mxl:
implemented: true
type:
warl:
dependency_fields: []
legal:
- mxl[1:0] in [0x1]
wr_illegal:
- Unchanged
extensions:
implemented: true
type:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000]
wr_illegal:
- Unchanged
tb/riscof/plugin-urv/urv_platform.yaml 0 → 100644
View file @ de5044f0
mtime:
implemented: false
mtimecmp:
implemented: false
nmi:
label: nmi_vector
reset:
label: reset_vector
tb/riscof/riscof.core 0 → 100644
View file @ de5044f0
CAPI=2:
name: ohwr:urv:riscof
description: Riscof architecture test suite
filesets:
rtl:
depend:
- ohwr:urv:urv_cpu
files:
- sv/generic_ram.sv
- sv/riscof_tb.sv
file_type: verilogSource
verilator_waivers:
files:
- lint/toplevel.vlt
file_type: vlt
targets:
default: &default
filesets:
- rtl
toplevel: riscof_tb
lint:
<<: *default
default_tool: verilator
tools:
verilator:
mode: lint-only
verilator_options:
- -Wall
verilator_tb:
<<: *default
default_tool: verilator
tools:
verilator:
mode: binary
verilator_options:
- -Wall
- --trace-fst
tb/riscof/sv/generic_ram.sv 0 → 100644
View file @ de5044f0
module generic_ram #(
parameter int AW = 10,
parameter int DW = 32,
localparam int BW = DW / 8,
localparam int Depth = 2**AW
) (
input logic clk,
input logic cen0,
input logic [AW-1:0] addr0,
output logic [DW-1:0] rdata0,
input logic cen1,
input logic wen1,
input logic [AW-1:0] addr1,
input logic [DW-1:0] wdata1,
input logic [BW-1:0] wstrb1,
output logic [DW-1:0] rdata1
);
logic [DW-1:0] mem[Depth];
logic [DW-1:0] wmask;
assign wmask = {{8{wstrb1[3]}}, {8{wstrb1[2]}}, {8{wstrb1[1]}}, {8{wstrb1[0]}}};
always @(posedge clk) begin
if (cen0) begin
rdata0 <= mem[addr0];
end
if (cen1) begin
if (wen1) begin
mem[addr1] <= wdata1 & wmask;
end else begin
rdata1 <= mem[addr1];
end
end
end
endmodule
tb/riscof/sv/riscof_tb.sv 0 → 100644
View file @ de5044f0
module riscof_tb ();
// Riscof tests can be big! RAM size of 8MB.
parameter int RAM_DEPTH = 8192 * 1024 / 4;
parameter int RAM_AW = $clog2(RAM_DEPTH);
parameter int RAM_DW = 32;
// --------------------------------------------------------------------------------
// Logic Declarations
// --------------------------------------------------------------------------------
logic clk;
logic rst;
logic [31:0] watchdog;
logic [31:0] i_addr;
logic i_rd;
logic [31:0] i_data;
logic [31:0] d_addr;
logic [31:0] d_data_s;
logic [31:0] d_data_l;
logic [ 3:0] d_data_s_stb;
logic d_store;
logic d_load;
logic d_load_done;
logic d_store_done;
logic dbg_enabled;
logic dbg_insn_ready;
logic [31:0] dbg_mbx_data;
logic fault;
integer fh;
// --------------------------------------------------------------------------------
// Clock/Reset
// --------------------------------------------------------------------------------
initial begin
clk = '0;
rst = '1;
#10 rst = '0;
end
always #5 clk <= !clk;
// --------------------------------------------------------------------------------
// Testbench Control
// --------------------------------------------------------------------------------
initial begin
if ($test$plusargs("waves")) begin
$dumpfile("waves.fst");
$dumpvars(0, riscof_tb);
end
end
initial begin
string signature;
if ($value$plusargs("signature=%s", signature)) begin
fh = $fopen(signature, "w");
end
end
initial begin
string filename;
if ($value$plusargs("initfile=%s", filename)) begin
$readmemh(filename, u_ram.mem);
end
end
always @(posedge clk)
if (rst) watchdog <= '0;
else begin
if (watchdog == 32'd10000000) begin
$display("End of simulation due to watchdog timeout");
$finish();
end
if (d_store && (d_addr == 32'hFFFFFFFC)) begin
$display("End of test signalled by software");
$finish();
end
if (d_store && (d_addr == 32'hFFFFFFF8)) begin
$fdisplay(fh, "%x", d_data_s);
end
watchdog <= watchdog + 1'b1;
end
// --------------------------------------------------------------------------------
// RAM Implementation
// --------------------------------------------------------------------------------
generic_ram #(
.AW(RAM_AW),
.DW(RAM_DW)
) u_ram (
.clk,
.cen0 (i_rd),
.addr0 (i_addr[RAM_AW+2-1:2]),
.rdata0(i_data),
.cen1 (d_store || d_load),
.wen1 (d_store),
.addr1 (d_addr[RAM_AW+2-1:2]),
.wdata1(d_data_s),
.wstrb1(d_data_s_stb),
.rdata1(d_data_l)
);
always @(posedge clk) begin
if (rst) begin
d_store_done <= '0;
d_load_done <= '0;
end else begin
d_store_done <= d_store;
d_load_done <= d_load;
end
end
// --------------------------------------------------------------------------------
// DUT
// --------------------------------------------------------------------------------
urv_cpu u_dut (
.clk_i (clk),
.rst_i (rst),
.irq_i ('0),
.fault_o (fault),
.im_addr_o (i_addr),
.im_rd_o (i_rd),
.im_valid_i ('1),
.im_data_i (i_data),
.dm_addr_o (d_addr),
.dm_data_s_o (d_data_s),
.dm_data_l_i (d_data_l),
.dm_data_select_o(d_data_s_stb),
.dm_store_o (d_store),
.dm_load_o (d_load),
.dm_load_done_i (d_load_done),
.dm_store_done_i (d_store_done),
.dbg_force_i ('0),
.dbg_enabled_o (dbg_enabled),
.dbg_insn_i ('0),
.dbg_insn_set_i ('0),
.dbg_insn_ready_o(dbg_insn_ready),
.dbg_mbx_data_i ('0),
.dbg_mbx_write_i ('0),
.dbg_mbx_data_o (dbg_mbx_data)
);
wire unused_ok = &{
1'b0,
fault,
dbg_enabled,
dbg_insn_ready,
dbg_mbx_data,
i_addr[1:0],
i_addr[31:RAM_AW],
1'b0
};
endmodule
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