sw/tools/wrc: first working version of vuart, wrc_loader and eeprom_loader

f1b55890 · Dimitris Lampridis · 6b7908bc · f1b55890 · f1b55890 · f1b55890
Commit f1b55890 authored Mar 01, 2017 by Dimitris Lampridis
9 changed files
--- a/sw/tools/wrc/.gitignore
+++ b/sw/tools/wrc/.gitignore
+*.L866
+*.o
+*.a
--- a/sw/tools/wrc/Makefile
+++ b/sw/tools/wrc/Makefile
+CPU ?= L866
+
+-include /acc/src/dsc/co/Make.auto
+
+VME_INC ?= /acc/src/dsc/drivers/coht/vmebridge/include/
+VME_LIB ?= /acc/src/dsc/drivers/coht/vmebridge/lib/libvmebus.$(CPU).o
+
+CFLAGS  += -g -Wall
+CFLAGS  += -I $(VME_INC)
+LDFLAGS += -L.
+LDLIBS  += -lvfchd.$(CPU)
+
+TARGETS = vfchd-vuart.$(CPU) vfchd-wrc_loader.$(CPU) vfchd-eeprom_loader.$(CPU)
+
+all: $(TARGETS)
+
+$(TARGETS): libvfchd.$(CPU).a
+
+libvfchd.$(CPU).a: vfchdlib.$(CPU).o $(VME_LIB)
+	$(AR) r $@ $^
+
+clean:
+	rm -f *.o *.a $(TARGETS) *~
+
+.PHONY: all clean
--- a/sw/tools/wrc/vfchd-eeprom_loader.c
+++ b/sw/tools/wrc/vfchd-eeprom_loader.c
+/* A simple tool to update the I2C EEPROM attached to the WR PTP core from a Linux terminal. */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <errno.h>
+
+#include "vfchdlib.h"
+#include "wrc_syscon_regs.h"
+
+#define I2C_EEPROM_SIZE ((size_t)(8 * 1024))
+#define I2C_EEPROM_ADDR 0x51
+
+void set_sda(struct vfchd_dev *dev, int val)
+{
+	if (val)
+		vfchd_wrc_writel(dev, SYSC_GPSR_FMC_SDA,
+				 dev->wrc_syscon_base + SYSC_REG_GPSR);
+	else
+		vfchd_wrc_writel(dev ,SYSC_GPCR_FMC_SDA,
+				 dev->wrc_syscon_base + SYSC_REG_GPCR);
+	usleep(1.25); /* 400kHz -> 2.5us/loop */
+}
+
+void set_scl(struct vfchd_dev *dev, int val)
+{
+	if (val)
+		vfchd_wrc_writel(dev, SYSC_GPSR_FMC_SCL,
+				 dev->wrc_syscon_base + SYSC_REG_GPSR);
+	else
+		vfchd_wrc_writel(dev, SYSC_GPCR_FMC_SCL,
+				 dev->wrc_syscon_base + SYSC_REG_GPCR);
+	usleep(1.25); /* 400kHz -> 2.5us/loop */
+}
+
+int get_sda(struct vfchd_dev *dev)
+{
+	return vfchd_wrc_readl(dev, dev->wrc_syscon_base + SYSC_REG_GPSR) &
+		SYSC_GPSR_FMC_SDA ? 1 : 0;
+}
+
+static void mi2c_start(struct vfchd_dev *dev)
+{
+	set_sda(dev, 0);
+	set_scl(dev, 0);
+}
+
+static void mi2c_stop(struct vfchd_dev *dev)
+{
+	set_sda(dev, 0);
+	set_scl(dev, 1);
+	set_sda(dev, 1);
+}
+
+static int mi2c_put_byte(struct vfchd_dev *dev, int data)
+{
+	int i;
+	int ack;
+
+	for (i = 0; i < 8; i++, data<<=1) {
+		set_sda(dev, data & 0x80);
+		set_scl(dev, 1);
+		set_scl(dev, 0);
+	}
+
+	set_sda(dev, 1);
+	set_scl(dev, 1);
+
+	ack = get_sda(dev);
+
+	set_scl(dev, 0);
+	set_sda(dev, 0);
+
+	return ack ? -EIO : 0; /* ack low == success */
+}
+
+static int mi2c_get_byte(struct vfchd_dev *dev, unsigned char *data, int ack)
+{
+	int i;
+	int indata = 0;
+
+	/* assert: scl is low */
+	set_scl(dev, 0);
+	set_sda(dev, 1);
+	for (i = 0; i < 8; i++) {
+		set_scl(dev, 1);
+		indata <<= 1;
+		if (get_sda(dev))
+			indata |= 0x01;
+		set_scl(dev, 0);
+	}
+
+	set_sda(dev, (ack ? 0 : 1));
+	set_scl(dev, 1);
+	set_scl(dev, 0);
+	set_sda(dev, 0);
+
+	*data= indata;
+	return 0;
+}
+
+void mi2c_init(struct vfchd_dev *dev)
+{
+	set_scl(dev, 1);
+	set_sda(dev, 1);
+}
+
+int vfchd_eeprom_read(struct vfchd_dev *dev, uint16_t offset, void *buf, size_t size)
+{
+	int ret = size;
+	uint8_t *buf8 = buf;
+	unsigned char c;
+
+	if (offset > I2C_EEPROM_SIZE)
+		return -EINVAL;
+	if (offset + size > I2C_EEPROM_SIZE)
+		return -EINVAL;
+
+	/* Read it all in a single loop: hardware allows it */
+	mi2c_start(dev);
+	if(mi2c_put_byte(dev, I2C_EEPROM_ADDR << 1) < 0) {
+		mi2c_stop(dev);
+		return -EIO;
+	}
+	mi2c_put_byte(dev, (offset >> 8) & 0xff);
+	mi2c_put_byte(dev, offset & 0xff);
+	mi2c_stop(dev);
+	mi2c_start(dev);
+	mi2c_put_byte(dev, (I2C_EEPROM_ADDR << 1) | 1);
+	while (size--) {
+		mi2c_get_byte(dev, &c, size != 0);
+		*buf8++ = c;
+	}
+	mi2c_stop(dev);
+	return ret;
+}
+
+int vfchd_eeprom_write(struct vfchd_dev *dev, uint16_t offset, const void *buf, size_t size)
+{
+	int i, busy;
+	const uint8_t *buf8 = buf;
+
+	if (offset > I2C_EEPROM_SIZE)
+		return -EINVAL;
+	if (offset + size > I2C_EEPROM_SIZE)
+		return -EINVAL;
+
+	for(i = 0; i < size; i++) {
+
+		mi2c_start(dev);
+
+		if(mi2c_put_byte(dev, I2C_EEPROM_ADDR << 1) < 0) {
+			mi2c_stop(dev);
+			return -1;
+		}
+		mi2c_put_byte(dev, (offset >> 8) & 0xff);
+		mi2c_put_byte(dev, offset & 0xff);
+		mi2c_put_byte(dev, buf8[i]);
+		mi2c_stop(dev);
+
+		do { /* wait until the chip becomes ready */
+			mi2c_start(dev);
+			busy = mi2c_put_byte(dev, I2C_EEPROM_ADDR << 1);
+			mi2c_stop(dev);
+		} while(busy);
+	}
+	return size;
+}
+
+void vfchd_eeprom_dump (struct vfchd_dev *dev)
+{
+
+	uint8_t buf8[16];
+
+	int i;
+
+	for (i = 0; i < I2C_EEPROM_SIZE; i += 16) {
+
+		if (vfchd_eeprom_read(dev, i, (void *)buf8, 16)) {
+
+			printf ("%8.x: "
+				"%.2x%.2x %.2x%.2x %.2x%.2x %.2x%.2x "
+				"%.2x%.2x %.2x%.2x %.2x%.2x %.2x%.2x\n", i,
+				buf8[0], buf8[1], buf8[2], buf8[3],
+				buf8[4], buf8[5], buf8[6], buf8[7],
+				buf8[8], buf8[9], buf8[10], buf8[11],
+				buf8[12], buf8[13], buf8[14], buf8[15]);
+		} else {
+			fprintf (stderr, "(EE): error reading from address 0x%.4x\n", i);
+		}
+
+	}
+}
+
+int vfchd_eeprom_loader (struct vfchd_dev *dev, const char *fname)
+{
+
+	int retval = 0;
+
+	FILE *f = fopen(fname, "rb");
+	if ( f == NULL )
+	{
+		fprintf( stderr, "(EE): Could not access file %s\n", fname );
+		return -1;
+	}
+
+	fseek(f, 0, SEEK_END);
+
+	long fsize = ftell(f);
+
+	fseek(f, 0, SEEK_SET);
+
+	uint8_t datum, readback;
+
+	int i = 0;
+
+	vfchd_wrc_disable(dev);
+
+	for (i=0; i < fsize; i++) {
+
+		fread((void *)&datum, 1, 1, f);
+
+		vfchd_eeprom_write (dev, i, &datum, 1);
+
+		vfchd_eeprom_read (dev, i, &readback, 1);
+
+		if ( readback != datum) {
+			fprintf(stderr,
+				"(EE): error writing value 0x%.2x to address "
+				"0x%.4x. Read-back value was 0x%.2x\n",
+				datum, i, readback);
+			retval = -1;
+			break;
+		}
+
+	}
+	fclose(f);
+
+	vfchd_wrc_enable(dev);
+
+	return retval;
+}
+
+int main(int argc, char **argv)
+{
+	int retval = 0;
+
+	struct vfchd_dev *dev = vfchd_open(argc, argv);
+
+	if (!dev)
+		return 1;
+
+	if (optind >= argc) {
+		printf("(II): no binary name provided, dumping current WRC EEPROM contents instead...\n");
+		vfchd_eeprom_dump(dev);
+
+	} else if (vfchd_eeprom_loader(dev, argv[optind]) < 0)	{
+		fprintf(stderr, "(EE): WRC loader failure.\n");
+		retval = 1;
+	}
+
+	vfchd_close(dev);
+
+	return retval;
+}
--- a/sw/tools/wrc/vfchd-vuart.c
+++ b/sw/tools/wrc/vfchd-vuart.c
+/* A simple console for accessing the VFC-HD virtual UART (i.e. for communicating with the WR Core shell
+   from a Linux terminal. */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <unistd.h>
+#include <termios.h>
+
+#include "vfchdlib.h"
+#include "wb_uart.h"
+
+int vfchd_vuart_rx(struct vfchd_dev *dev, char *d)
+{
+	int rdr = vfchd_wrc_readl(dev, dev->wrc_vuart_base + UART_REG_HOST_RDR);
+
+	if(rdr & UART_HOST_RDR_RDY)
+	{
+		*d = UART_HOST_RDR_DATA_R(rdr);
+		return 1;
+	}    else
+		return 0;
+}
+
+int vfchd_vuart_tx(struct vfchd_dev *dev, char d)
+{
+	while( vfchd_wrc_readl(dev, dev->wrc_vuart_base + UART_REG_SR) & UART_SR_RX_RDY );
+	vfchd_wrc_writel(dev, UART_HOST_TDR_DATA_W(d), dev->wrc_vuart_base + UART_REG_HOST_TDR);
+
+	return 0;
+}
+
+static int transfer_byte(struct vfchd_dev *dev, int from, int is_control) {
+	char c;
+	int ret;
+	do {
+		ret = read(from, &c, 1);
+	} while (ret < 0 && errno == EINTR);
+	if(ret == 1) {
+		if(is_control) {
+			if(c == '\x01') { // C-a
+				return -1;
+			}
+		}
+		vfchd_vuart_tx(dev, c);
+	} else {
+		fprintf(stderr, "\n(EE): nothing to read. probably port disconnected.\n");
+		return -2;
+	}
+	return 0;
+}
+
+
+void term_main(struct vfchd_dev *dev, int keep_term)
+{
+	struct termios oldkey, newkey;
+	int need_exit = 0;
+
+	fprintf(stderr, "[press C-a to exit]\n");
+
+	if(!keep_term) {
+		tcgetattr(STDIN_FILENO,&oldkey);
+		newkey.c_cflag = B9600 | CS8 | CLOCAL | CREAD;
+		newkey.c_iflag = IGNPAR;
+		newkey.c_oflag = 0;
+		newkey.c_lflag = 0;
+		newkey.c_cc[VMIN]=1;
+		newkey.c_cc[VTIME]=0;
+		tcflush(STDIN_FILENO, TCIFLUSH);
+		tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
+	}
+	while(!need_exit) {
+		fd_set fds;
+		int ret;
+		char rx;
+		struct timeval tv = {0, 10000};
+
+		FD_ZERO(&fds);
+		FD_SET(STDIN_FILENO, &fds);
+
+		ret = select(STDIN_FILENO+1, &fds, NULL, NULL, &tv);
+		if(ret == -1) {
+			perror("select");
+		} else if (ret > 0) {
+			if(FD_ISSET(STDIN_FILENO, &fds)) {
+				need_exit = transfer_byte(dev, STDIN_FILENO, 1);
+			}
+		}
+
+		while((vfchd_vuart_rx(dev, &rx)) == 1)
+			fprintf(stderr,"%c", rx);
+
+	}
+
+	if(!keep_term)
+		tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
+}
+
+int main(int argc, char **argv)
+{
+	struct vfchd_dev *dev = vfchd_open(argc, argv);
+
+	if (!dev)
+		return 1;
+
+	term_main(dev, 0);
+
+	vfchd_close(dev);
+
+	return 0;
+}
--- a/sw/tools/wrc/vfchd-wrc_loader.c
+++ b/sw/tools/wrc/vfchd-wrc_loader.c
+/* A simple tool to update the WR PTP core software from a Linux terminal. */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <arpa/inet.h>
+
+#include "vfchdlib.h"
+#include "wrc_syscon_regs.h"
+
+uint32_t vfchd_wrcmem_read(struct vfchd_dev *dev, uint32_t offset)
+{
+	return vfchd_wrc_readl(dev, dev->wrc_mem_base + offset);
+}
+
+
+void vfchd_wrcmem_write(struct vfchd_dev *dev, uint32_t datum, uint32_t offset)
+{
+	vfchd_wrc_writel(dev, datum, dev->wrc_mem_base + offset);
+}
+
+int vfchd_wrc_loader (struct vfchd_dev *dev, const char *fname)
+{
+
+	int retval = 0;
+
+	FILE *f = fopen(fname, "rb");
+	if ( f == NULL )
+	{
+		fprintf( stderr, "(EE): Could not access file %s\n", fname );
+		return -1;
+	}
+
+	fseek(f, 0, SEEK_END);
+
+	long fsize = ftell(f);
+
+	fseek(f, 0, SEEK_SET);
+
+	uint32_t datum, readback;
+
+	int i = 0;
+
+	vfchd_wrc_disable(dev);
+
+	for (i = 0; i < fsize; i += 4) {
+
+		fread((struct vfchd_dev *)&datum, 4, 1, f);
+
+		vfchd_wrcmem_write(dev, ntohl(datum), i);
+
+		readback = vfchd_wrcmem_read(dev, i);
+
+		if ( readback != ntohl(datum)) {
+			fprintf(stderr,
+				"(EE): error writing value 0x%.8x "
+				"to address 0x%.8x. "
+				"Read-back value was 0x%.8x\n",
+				ntohl(datum), i, readback);
+			retval = -1;
+			break;
+		}
+	}
+
+	fclose(f);
+
+	vfchd_wrc_enable(dev);
+
+	return retval;
+}
+
+int main(int argc, char **argv)
+{
+	struct vfchd_dev *dev = vfchd_open(argc, argv);
+
+	if (!dev)
+		return 1;
+
+	if (optind >= argc) {
+		fprintf(stderr, "(EE): expected binary name after options.\n");
+		return 1;
+	}
+
+	if (vfchd_wrc_loader(dev, argv[optind]) < 0)
+	{
+		fprintf(stderr, "(EE): WRC loader failure.\n");
+		return 1;
+	}
+
+	vfchd_close(dev);
+
+	return 0;
+}
--- a/sw/tools/wrc/vfchdlib.c
+++ b/sw/tools/wrc/vfchdlib.c
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <arpa/inet.h>
+
+#include "vfchdlib.h"
+#include "wrc_syscon_regs.h"
+
+uint32_t _vfchd_readl(struct vfchd_dev *dev, uint32_t offset)
+{
+	volatile uint32_t *addr = dev->map.user_va + offset;
+
+	uint32_t datum = ntohl(addr[0]);
+
+	return datum;
+}
+
+void _vfchd_writel(struct vfchd_dev *dev, uint32_t datum, uint32_t offset)
+{
+	volatile uint32_t *addr = dev->map.user_va + offset;
+
+	addr[0] = htonl(datum);
+}
+
+uint32_t vfchd_wrc_readl(struct vfchd_dev *dev, uint32_t offset)
+{
+	return _vfchd_readl(dev, dev->wrc_base_offset + offset);
+}
+
+
+void vfchd_wrc_writel(struct vfchd_dev *dev, uint32_t datum, uint32_t offset)
+{
+	_vfchd_writel(dev, datum, dev->wrc_base_offset + offset);
+}
+
+void vfchd_wrc_disable(struct vfchd_dev *dev)
+{
+	vfchd_wrc_writel(dev, 0x1deadbee, dev->wrc_syscon_base);
+}
+
+void vfchd_wrc_enable(struct vfchd_dev *dev)
+{
+	vfchd_wrc_writel(dev, 0x0deadbee, dev->wrc_syscon_base);
+}
+
+void _vfchd_print_usage(const char *progname)
+{
+	fprintf(stderr,
+		"\nUsage: \"%s "
+		"[-a VME_AM] "
+		"[-d DATA_WIDTH] "
+		"[-s MAP_SIZE] "
+		"[-w WRC_BASE_OFFSET] "
+		"[-m WRC_MEM_BASE] "
+		"[-y WRC_SYSCON_BASE] "
+		"[-u WRC_VUART_BASE] "
+		"-l SLOT [...]\n", progname);
+	fprintf(stderr,
+		"By default, a=0x%02x, d=%d, "
+		"s=0x%x, w=0x%x, "
+		"m=0x%x, y=0x%x, "
+		"and u=0x%x\n\n",
+		VFCHD_AM_DEFAULT,
+		VFCHD_DW_DEFAULT,
+		VFCHD_SIZEL_DEFAULT,
+		VFCHD_WRC_OFFSET_DEFAULT,
+		VFCHD_WRC_MEMORY_DEFAULT,
+		VFCHD_WRC_SYSCON_DEFAULT,
+		VFCHD_WRC_VUART_DEFAULT);
+}
+
+int _vfchd_vme64x_rellocate(struct vfchd_dev *dev)
+{
+	int i;
+
+	// Simple hard-coded values which declare two functions
+	// for A24 and A32 accesses.
+
+	const uint32_t vme64x_relloc_seq_addr[] =
+		{
+			0x7fff8, 0x7fff4, 0x7ff30, 0x7ff5c,
+			0x7ff58, 0x7ff60, 0x7ff64, 0x7ff68,
+			0x7ff6c, 0x7ff70, 0x7ff74, 0x7ff78,
+			0x7ff7c, 0x7fff8
+		};
+
+	const uint8_t vme64x_relloc_seq_data[] =
+		{
+			0x80, 0x10, 0x01, 0x00,
+			0x00, 0x04, 0x00, 0x00,
+			0x24, 0x00, 0x20, 0x00,
+			0xe4, 0x10
+		};
+
+	dev->map.am         = VME_CR_CSR;
+	dev->map.data_width = VME_D32;
+	dev->map.sizel      = 0x80000;
+	dev->map.vme_addrl  = dev->slot << 19;
+
+	if (vme_map(&(dev->map), 1) == NULL) {
+		fprintf(stderr, "(EE): could not map at 0x%08x\n",
+			dev->map.vme_addrl);
+		return -1;
+	}
+
+	for (i = 0; i < 14; i++) {
+		_vfchd_writel(dev,
+			      vme64x_relloc_seq_data[i],
+			      vme64x_relloc_seq_addr[i]);
+	}
+
+	vme_unmap(&(dev->map), 1);
+
+	return 0;
+}
+
+struct vfchd_dev *vfchd_open(int argc, char **argv)
+{
+	struct vfchd_dev *dev;
+
+	int c;
+
+	// Required arguments
+	uint8_t slot = 0;
+
+	// Default values for optional arguments
+	uint32_t     wrc_base_offset = VFCHD_WRC_OFFSET_DEFAULT;
+	uint32_t        wrc_mem_base = VFCHD_WRC_MEMORY_DEFAULT;
+	uint32_t     wrc_syscon_base = VFCHD_WRC_SYSCON_DEFAULT;
+	uint32_t      wrc_vuart_base = VFCHD_WRC_VUART_DEFAULT;
+	enum vme_address_modifier am = VFCHD_AM_DEFAULT;
+	enum vme_data_width       dw = VFCHD_DW_DEFAULT;
+	unsigned int           sizel = VFCHD_SIZEL_DEFAULT;
+
+	// Process cmd line arguments
+	while ((c = getopt (argc, argv, "a:d:s:w:m:y:u:l:")) != -1)
+		switch (c)
+		{
+		case 'a':
+			am = strtol(optarg, NULL, 0);
+			break;
+		case 'd':
+			dw = strtol(optarg, NULL, 0);
+			break;
+		case 's':
+			sizel = strtol(optarg, NULL, 0);
+			break;
+		case 'w':
+			wrc_base_offset = strtol(optarg, NULL, 0);
+			break;
+		case 'm':
+			wrc_mem_base = strtol(optarg, NULL, 0);
+			break;
+		case 'y':
+			wrc_syscon_base = strtol(optarg, NULL, 0);
+			break;
+		case 'u':
+			wrc_vuart_base = strtol(optarg, NULL, 0);
+			break;
+		case 'l':
+			slot  = strtol(optarg, NULL, 0);
+			break;
+		case '?':
+		default:
+			_vfchd_print_usage(argv[0]);
+			return NULL;
+		}
+
+	if (!slot) {
+		fprintf(stderr, "(EE): missing SLOT argument.\n");
+		_vfchd_print_usage(argv[0]);
+		return NULL;
+	}
+
+	// Allocate and init the device structure
+	dev = malloc(sizeof(struct vfchd_dev));
+
+	if (!dev)
+		return NULL;
+
+	dev->wrc_base_offset = wrc_base_offset;
+	dev->wrc_mem_base    = wrc_mem_base;
+	dev->wrc_syscon_base = wrc_syscon_base;
+	dev->wrc_vuart_base  = wrc_vuart_base;
+
+	dev->slot = slot;
+
+	// Perform VME64x rellocation if necessary
+	if (_vfchd_vme64x_rellocate(dev) < 0) {
+		fprintf(stderr,"(EE): VME64x rellocation failed.\n");
+		free(dev);
+		return NULL;
+	}
+
+	dev->map.am         = am;
+	dev->map.data_width = dw;
+	dev->map.sizel      = sizel;
+
+	switch(am)
+	{
+	case VME_A32_USER_DATA_SCT:
+		dev->map.vme_addrl = dev->slot << 24;
+		break;
+
+	case VME_A24_USER_DATA_SCT:
+		dev->map.vme_addrl = dev->slot << 19;
+		break;
+
+	default:
+		dev->map.vme_addrl = 0;
+		break;
+	}
+
+	if (!dev->map.vme_addrl) {
+		fprintf(stderr,
+			"(EE): unsupported AM 0x%02x, "
+			"only 0x09 and 0x39 are allowed\n",
+			dev->map.am);
+		free(dev);
+		return NULL;
+	}
+
+	if (vme_map(&(dev->map), 1) == NULL) {
+		fprintf(stderr, "(EE): could not map at 0x%08x\n",
+			dev->map.vme_addrl);
+		free(dev);
+		return NULL;
+	}
+
+	return (struct vfchd_dev *)dev;
+
+}
+
+void vfchd_close(struct vfchd_dev *dev) {
+
+	if (!dev)
+		return;
+
+	vme_unmap(&(dev->map), 1);
+
+	free(dev);
+}
--- a/sw/tools/wrc/vfchdlib.h
+++ b/sw/tools/wrc/vfchdlib.h
+#ifndef __VFCHDLIB_H
+#define __VFCHDLIB_H
+
+#include <stdint.h>
+#include <libvmebus.h>
+
+#define VFCHD_AM_DEFAULT         VME_A32_USER_DATA_SCT
+#define VFCHD_DW_DEFAULT         VME_D32
+#define VFCHD_SIZEL_DEFAULT      0x80000
+#define VFCHD_WRC_OFFSET_DEFAULT 0x40000
+#define VFCHD_WRC_MEMORY_DEFAULT 0x00000
+#define VFCHD_WRC_SYSCON_DEFAULT 0x20400
+#define VFCHD_WRC_VUART_DEFAULT  0x20500
+
+struct vfchd_dev {
+	uint32_t           wrc_base_offset;
+	uint32_t           wrc_mem_base;
+	uint32_t           wrc_syscon_base;
+	uint32_t           wrc_vuart_base;
+	uint8_t            slot;
+	struct vme_mapping map;
+};
+
+uint32_t vfchd_wrc_readl(struct vfchd_dev *, uint32_t);
+
+void vfchd_wrc_writel(struct vfchd_dev *, uint32_t, uint32_t);
+
+void vfchd_wrc_disable(struct vfchd_dev *);
+
+void vfchd_wrc_enable(struct vfchd_dev *);
+
+void vfchd_close(struct vfchd_dev *);
+
+struct vfchd_dev *vfchd_open(int, char **);
+
+
+#endif //__VFCHDLIB_H
--- a/sw/tools/wrc/wb_uart.h
+++ b/sw/tools/wrc/wb_uart.h
+/*
+  Register definitions for slave core: Simple Wishbone UART
+
+  * File           : wb_uart.h
+  * Author         : auto-generated by wbgen2 from simple_uart_wb.wb
+  * Created        : Thu May  3 17:36:38 2012
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
+#define __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Status Register */
+
+/* definitions for field: TX busy in reg: Status Register */
+#define UART_SR_TX_BUSY                       WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: RX ready in reg: Status Register */
+#define UART_SR_RX_RDY                        WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Baudrate control register */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for field: Transmit data in reg: Transmit data regsiter */
+#define UART_TDR_TX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_TDR_TX_DATA_SHIFT                0
+#define UART_TDR_TX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_TDR_TX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for field: Received data in reg: Receive data regsiter */
+#define UART_RDR_RX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
+#define UART_RDR_RX_DATA_SHIFT                0
+#define UART_RDR_RX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_RDR_RX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Host VUART Tx register */
+
+/* definitions for field: TX Data in reg: Host VUART Tx register */
+#define UART_HOST_TDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
+#define UART_HOST_TDR_DATA_SHIFT              0
+#define UART_HOST_TDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_HOST_TDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: TX Ready in reg: Host VUART Tx register */
+#define UART_HOST_TDR_RDY                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for register: Host VUART Rx register */
+
+/* definitions for field: RX Data in reg: Host VUART Rx register */
+#define UART_HOST_RDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
+#define UART_HOST_RDR_DATA_SHIFT              0
+#define UART_HOST_RDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_HOST_RDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: RX Ready in reg: Host VUART Rx register */
+#define UART_HOST_RDR_RDY                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: RX FIFO Count in reg: Host VUART Rx register */
+#define UART_HOST_RDR_COUNT_MASK              WBGEN2_GEN_MASK(9, 16)
+#define UART_HOST_RDR_COUNT_SHIFT             9
+#define UART_HOST_RDR_COUNT_W(value)          WBGEN2_GEN_WRITE(value, 9, 16)
+#define UART_HOST_RDR_COUNT_R(reg)            WBGEN2_GEN_READ(reg, 9, 16)
+
+#define UART_REG_SR 0x0
+#define UART_REG_HOST_TDR 0x10
+#define UART_REG_HOST_RDR 0x14
+
+#endif
--- a/sw/tools/wrc/wrc_syscon_regs.h
+++ b/sw/tools/wrc/wrc_syscon_regs.h
+/*
+  Register definitions for slave core: WR Core System Controller
+
+  * File           : wrc_syscon_regs.h
+  * Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
+  * Created        : Mon Jul 11 14:59:51 2016
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
+#define __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Syscon reset register */
+
+/* definitions for field: Reset trigger in reg: Syscon reset register */
+#define SYSC_RSTR_TRIG_MASK                   WBGEN2_GEN_MASK(0, 28)
+#define SYSC_RSTR_TRIG_SHIFT                  0
+#define SYSC_RSTR_TRIG_W(value)               WBGEN2_GEN_WRITE(value, 0, 28)
+#define SYSC_RSTR_TRIG_R(reg)                 WBGEN2_GEN_READ(reg, 0, 28)
+
+/* definitions for field: Reset line state value in reg: Syscon reset register */
+#define SYSC_RSTR_RST                         WBGEN2_GEN_MASK(28, 1)
+
+/* definitions for register: GPIO Set/Readback Register */
+
+/* definitions for field: Status LED in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_LED_STAT                    WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Link LED in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_LED_LINK                    WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_FMC_SCL                     WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_FMC_SDA                     WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: Network AP reset in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_NET_RST                     WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: SPEC Pushbutton 1 state in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_BTN1                        WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: SPEC Pushbutton 2 state in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_BTN2                        WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: SFP detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SFP_DET                     WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SFP_SCL                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SFP_SDA                     WBGEN2_GEN_MASK(9, 1)
+
+/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SPI_SCLK                    WBGEN2_GEN_MASK(10, 1)
+
+/* definitions for field: SPI bitbanged NCS in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SPI_NCS                     WBGEN2_GEN_MASK(11, 1)
+
+/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SPI_MOSI                    WBGEN2_GEN_MASK(12, 1)
+
+/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_SPI_MISO                    WBGEN2_GEN_MASK(13, 1)
+
+/* definitions for register: GPIO Clear Register */
+
+/* definitions for field: Status LED in reg: GPIO Clear Register */
+#define SYSC_GPCR_LED_STAT                    WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Link LED in reg: GPIO Clear Register */
+#define SYSC_GPCR_LED_LINK                    WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Clear Register */
+#define SYSC_GPCR_FMC_SCL                     WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
+#define SYSC_GPCR_FMC_SDA                     WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Clear Register */
+#define SYSC_GPCR_SFP_SCL                     WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
+#define SYSC_GPCR_SFP_SDA                     WBGEN2_GEN_MASK(9, 1)
+
+/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
+#define SYSC_GPCR_SPI_SCLK                    WBGEN2_GEN_MASK(10, 1)
+
+/* definitions for field: SPI bitbanged CS in reg: GPIO Clear Register */
+#define SYSC_GPCR_SPI_CS                      WBGEN2_GEN_MASK(11, 1)
+
+/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
+#define SYSC_GPCR_SPI_MOSI                    WBGEN2_GEN_MASK(12, 1)
+
+/* definitions for register: Hardware Feature Register */
+
+/* definitions for field: Memory size in reg: Hardware Feature Register */
+#define SYSC_HWFR_MEMSIZE_MASK                WBGEN2_GEN_MASK(0, 4)
+#define SYSC_HWFR_MEMSIZE_SHIFT               0
+#define SYSC_HWFR_MEMSIZE_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
+#define SYSC_HWFR_MEMSIZE_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for register: Timer Control Register */
+
+/* definitions for field: Timer Divider in reg: Timer Control Register */
+#define SYSC_TCR_TDIV_MASK                    WBGEN2_GEN_MASK(0, 12)
+#define SYSC_TCR_TDIV_SHIFT                   0
+#define SYSC_TCR_TDIV_W(value)                WBGEN2_GEN_WRITE(value, 0, 12)
+#define SYSC_TCR_TDIV_R(reg)                  WBGEN2_GEN_READ(reg, 0, 12)
+
+/* definitions for field: Timer Enable in reg: Timer Control Register */
+#define SYSC_TCR_ENABLE                       WBGEN2_GEN_MASK(31, 1)
+
+/* definitions for register: Timer Counter Value Register */
+
+/* definitions for register: User Diag: version register */
+
+/* definitions for field: Ver in reg: User Diag: version register */
+#define SYSC_DIAG_INFO_VER_MASK               WBGEN2_GEN_MASK(0, 16)
+#define SYSC_DIAG_INFO_VER_SHIFT              0
+#define SYSC_DIAG_INFO_VER_W(value)           WBGEN2_GEN_WRITE(value, 0, 16)
+#define SYSC_DIAG_INFO_VER_R(reg)             WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Id in reg: User Diag: version register */
+#define SYSC_DIAG_INFO_ID_MASK                WBGEN2_GEN_MASK(16, 16)
+#define SYSC_DIAG_INFO_ID_SHIFT               16
+#define SYSC_DIAG_INFO_ID_W(value)            WBGEN2_GEN_WRITE(value, 16, 16)
+#define SYSC_DIAG_INFO_ID_R(reg)              WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: User Diag: number of words */
+
+/* definitions for field: Read/write words in reg: User Diag: number of words */
+#define SYSC_DIAG_NW_RW_MASK                  WBGEN2_GEN_MASK(0, 16)
+#define SYSC_DIAG_NW_RW_SHIFT                 0
+#define SYSC_DIAG_NW_RW_W(value)              WBGEN2_GEN_WRITE(value, 0, 16)
+#define SYSC_DIAG_NW_RW_R(reg)                WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Read-only words in reg: User Diag: number of words */
+#define SYSC_DIAG_NW_RO_MASK                  WBGEN2_GEN_MASK(16, 16)
+#define SYSC_DIAG_NW_RO_SHIFT                 16
+#define SYSC_DIAG_NW_RO_W(value)              WBGEN2_GEN_WRITE(value, 16, 16)
+#define SYSC_DIAG_NW_RO_R(reg)                WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: User Diag: Control Register */
+
+/* definitions for field: Address in reg: User Diag: Control Register */
+#define SYSC_DIAG_CR_ADR_MASK                 WBGEN2_GEN_MASK(0, 16)
+#define SYSC_DIAG_CR_ADR_SHIFT                0
+#define SYSC_DIAG_CR_ADR_W(value)             WBGEN2_GEN_WRITE(value, 0, 16)
+#define SYSC_DIAG_CR_ADR_R(reg)               WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: R/W in reg: User Diag: Control Register */
+#define SYSC_DIAG_CR_RW                       WBGEN2_GEN_MASK(31, 1)
+
+/* definitions for register: User Diag: data to read/write */
+/* [0x0]: REG Syscon reset register */
+#define SYSC_REG_RSTR 0x00000000
+/* [0x4]: REG GPIO Set/Readback Register */
+#define SYSC_REG_GPSR 0x00000004
+/* [0x8]: REG GPIO Clear Register */
+#define SYSC_REG_GPCR 0x00000008
+/* [0xc]: REG Hardware Feature Register */
+#define SYSC_REG_HWFR 0x0000000c
+/* [0x10]: REG Timer Control Register */
+#define SYSC_REG_TCR 0x00000010
+/* [0x14]: REG Timer Counter Value Register */
+#define SYSC_REG_TVR 0x00000014
+/* [0x18]: REG User Diag: version register */
+#define SYSC_REG_DIAG_INFO 0x00000018
+/* [0x1c]: REG User Diag: number of words */
+#define SYSC_REG_DIAG_NW 0x0000001c
+/* [0x20]: REG User Diag: Control Register */
+#define SYSC_REG_DIAG_CR 0x00000020
+/* [0x24]: REG User Diag: data to read/write */
+#define SYSC_REG_DIAG_DAT 0x00000024
+#endif