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VME ADC 250k 16b 36cha
Commit f7ea7ecc authored by Greg's avatar Greg
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HDL for FPGA and CPLD added

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trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/VME_BRIDGE.qsf 0 → 100644
View file @ f7ea7ecc
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# VME_BRIDGE_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM570F256C3
set_global_assignment -name TOP_LEVEL_ENTITY VME_BRIDGE
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:16:17 MAY 02, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
set_location_assignment PIN_J16 -to adrsel[0]
set_location_assignment PIN_H16 -to adrsel[1]
set_location_assignment PIN_G16 -to adrsel[2]
set_location_assignment PIN_F15 -to adrsel[3]
set_location_assignment PIN_L15 -to adrsel[4]
set_location_assignment PIN_L16 -to adrsel[5]
set_location_assignment PIN_K15 -to adrsel[6]
set_location_assignment PIN_K16 -to adrsel[7]
set_location_assignment PIN_J12 -to clk
set_location_assignment PIN_D15 -to FPGA_RESET
set_location_assignment PIN_R16 -to xdata[8]
set_location_assignment PIN_T13 -to xdata[9]
set_location_assignment PIN_T12 -to xdata[10]
set_location_assignment PIN_N12 -to xdata[4]
set_location_assignment PIN_R11 -to xdata[2]
set_location_assignment PIN_P12 -to xdata[13]
set_location_assignment PIN_T11 -to xdata[11]
set_location_assignment PIN_R12 -to xdata[1]
set_location_assignment PIN_R10 -to xdata[3]
set_location_assignment PIN_P11 -to xdata[5]
set_location_assignment PIN_M8 -to xdata[0]
set_location_assignment PIN_T10 -to xdata[12]
set_location_assignment PIN_P10 -to xdata[14]
set_location_assignment PIN_R9 -to xdsn[1]
set_location_assignment PIN_T9 -to xlwordn
set_location_assignment PIN_T8 -to xwriten
set_location_assignment PIN_P9 -to xdata[6]
set_location_assignment PIN_R8 -to xdsn[0]
set_location_assignment PIN_P8 -to xdata[15]
set_location_assignment PIN_T7 -to xaddr[23]
set_location_assignment PIN_P7 -to xdata[7]
set_location_assignment PIN_R7 -to xam[5]
set_location_assignment PIN_P6 -to xam[1]
set_location_assignment PIN_T6 -to xaddr[22]
set_location_assignment PIN_R5 -to xam[2]
set_location_assignment PIN_R6 -to xam[0]
set_location_assignment PIN_T5 -to xaddr[21]
set_location_assignment PIN_N5 -to xaddr[11]
set_location_assignment PIN_T4 -to xaddr[20]
set_location_assignment PIN_R4 -to xas
set_location_assignment PIN_P4 -to xaddr[10]
set_location_assignment PIN_R1 -to xaddr[19]
set_location_assignment PIN_R3 -to xaddr[4]
set_location_assignment PIN_P2 -to xam[3]
set_location_assignment PIN_N3 -to xaddr[3]
set_location_assignment PIN_N1 -to xaddr[18]
set_location_assignment PIN_N2 -to xiackn
set_location_assignment PIN_M1 -to xiackinn
set_location_assignment PIN_M4 -to xaddr[9]
set_location_assignment PIN_L2 -to xaddr[15]
set_location_assignment PIN_M3 -to xaddr[2]
set_location_assignment PIN_L1 -to xaddr[16]
set_location_assignment PIN_M2 -to xaddr[17]
set_location_assignment PIN_K2 -to xaddr[14]
set_location_assignment PIN_L4 -to xaddr[8]
set_location_assignment PIN_K1 -to xam[4]
set_location_assignment PIN_L3 -to xaddr[1]
set_location_assignment PIN_J2 -to xaddr[13]
set_location_assignment PIN_K3 -to xiackoutn
set_location_assignment PIN_J1 -to xaddr[7]
set_location_assignment PIN_J3 -to xdata[24]
set_location_assignment PIN_H1 -to xaddr[6]
set_location_assignment PIN_H3 -to xdata[25]
set_location_assignment PIN_H2 -to xaddr[12]
set_location_assignment PIN_G3 -to xdata[26]
set_location_assignment PIN_G1 -to xaddr[5]
set_location_assignment PIN_F3 -to xdata[27]
set_location_assignment PIN_E2 -to xdata[20]
set_location_assignment PIN_F1 -to xdata[23]
set_location_assignment PIN_E3 -to xdata[28]
set_location_assignment PIN_F2 -to xdata[22]
set_location_assignment PIN_E4 -to xdata[29]
set_location_assignment PIN_E1 -to xdata[21]
set_location_assignment PIN_D2 -to xdata[18]
set_location_assignment PIN_D1 -to xdata[19]
set_location_assignment PIN_D3 -to xdata[30]
set_location_assignment PIN_C2 -to xdata[31]
set_location_assignment PIN_B1 -to xdata[17]
set_location_assignment PIN_A2 -to xdata[16]
set_location_assignment PIN_C4 -to xdtack
set_location_assignment PIN_P15 -to xbufdir
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_A5 -to C_EXT[4]
set_location_assignment PIN_B6 -to C_EXT[6]
set_location_assignment PIN_D5 -to C_EXT[3]
set_location_assignment PIN_A6 -to C_EXT[5]
set_location_assignment PIN_B3 -to RVD0
set_location_assignment PIN_D4 -to RVD1
set_location_assignment PIN_A4 -to CPU_INT
set_location_assignment PIN_H12 -to CPLD_CLK
set_location_assignment PIN_B5 -to xbufoen[0]
set_location_assignment PIN_G2 -to xbufoen[1]
set_location_assignment PIN_A7 -to C_EXT[7]
set_location_assignment PIN_A8 -to C_EXT[8]
set_location_assignment PIN_C7 -to C_EXT[2]
set_location_assignment PIN_B4 -to C_EXT[1]
set_location_assignment PIN_C6 -to Main_CK_enable
set_location_assignment PIN_H5 -to PCI_CLK
set_location_assignment PIN_D11 -to RSV3
set_location_assignment PIN_J5 -to RVD12
set_location_assignment PIN_C3 -to RVD13
set_location_assignment PIN_N15 -to spi_CS
set_location_assignment PIN_M15 -to SPI_SCK
set_location_assignment PIN_N16 -to SPI_SO
set_location_assignment PIN_M16 -to SPI_SI
set_location_assignment PIN_T2 -to RVD11
set_location_assignment PIN_A9 -to reconfig
set_location_assignment PIN_C5 -to xirq
set_location_assignment PIN_A10 -to CPLD_STAT
set_location_assignment PIN_P5 -to xsysreset
set_global_assignment -name VHDL_FILE shiftreg.vhd
set_global_assignment -name VHDL_FILE spi_link.vhd
set_global_assignment -name VHDL_FILE clock_divider.vhd
set_global_assignment -name VHDL_FILE types.vhd
set_global_assignment -name VHDL_FILE as_programmer.vhd
set_global_assignment -name VHDL_FILE vme_bridge.vhd
set_global_assignment -name VHDL_FILE VME_CONTROLLER.vhd
set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
set_global_assignment -name FMAX_REQUIREMENT "55 MHz" -section_id "CLK 50"
set_instance_assignment -name CLOCK_SETTINGS "CLK 50" -to clk
set_location_assignment PIN_T15 -to FPGA_AD[0]
set_location_assignment PIN_R14 -to FPGA_AD[1]
set_location_assignment PIN_R13 -to FPGA_AD[2]
set_location_assignment PIN_P14 -to FPGA_AD[3]
set_location_assignment PIN_P13 -to FPGA_AD[4]
set_location_assignment PIN_N14 -to FPGA_AD[5]
set_location_assignment PIN_N13 -to FPGA_AD[6]
set_location_assignment PIN_C9 -to FPGA_AD[7]
set_location_assignment PIN_M13 -to FPGA_AD[8]
set_location_assignment PIN_L14 -to FPGA_AD[9]
set_location_assignment PIN_L13 -to FPGA_AD[10]
set_location_assignment PIN_K14 -to FPGA_AD[11]
set_location_assignment PIN_E15 -to FPGA_AD[12]
set_location_assignment PIN_J15 -to FPGA_AD[13]
set_location_assignment PIN_J14 -to FPGA_AD[14]
set_location_assignment PIN_H15 -to FPGA_AD[15]
set_location_assignment PIN_D16 -to FPGA_TRDYn
set_location_assignment PIN_C15 -to FPGA_IRDYn
set_location_assignment PIN_E16 -to FPGA_INTn
set_location_assignment PIN_F16 -to FPGA_FRAMEn
set_location_assignment PIN_C10 -to FPGA_BEn[0]
set_location_assignment PIN_C8 -to FPGA_BEn[1]
set_location_assignment PIN_M9 -to resetn
set_global_assignment -name VECTOR_WAVEFORM_FILE VME_BRIDGE.vwf
set_location_assignment PIN_H14 -to test_lines[16]
set_location_assignment PIN_G15 -to test_lines[17]
set_location_assignment PIN_G14 -to test_lines[18]
set_location_assignment PIN_F14 -to test_lines[19]
set_location_assignment PIN_F13 -to test_lines[20]
set_location_assignment PIN_E14 -to test_lines[21]
set_location_assignment PIN_E13 -to test_lines[22]
set_location_assignment PIN_D14 -to test_lines[23]
set_location_assignment PIN_C14 -to test_lines[24]
set_location_assignment PIN_D13 -to test_lines[25]
set_location_assignment PIN_C13 -to test_lines[26]
set_location_assignment PIN_B14 -to test_lines[27]
set_location_assignment PIN_C12 -to test_lines[28]
set_location_assignment PIN_B13 -to test_lines[29]
set_location_assignment PIN_D12 -to test_lines[30]
set_location_assignment PIN_C11 -to test_lines[31]
set_location_assignment PIN_B16 -to RSV1
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_A15 -to CPLD_prog_nCONFIG
set_location_assignment PIN_A13 -to CPLD_prog_DCLK
set_location_assignment PIN_B12 -to CPLD_prog_CONF_DONE
set_location_assignment PIN_A12 -to CPLD_prog_DATA
set_location_assignment PIN_B11 -to CPLD_PROG_nCE
set_location_assignment PIN_A11 -to CPLD_prog_nCS
set_location_assignment PIN_B10 -to CPLD_prog_ASDI
\ No newline at end of file
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/VME_controller.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
-- Created on Wed Sep 22 10:39:11 2004
LIBRARY IEEE ;
LIBRARY lpm ;
USE IEEE.std_logic_1164.all ;
USE IEEE.numeric_std.all;
USE lpm.lpm_components.ALL;
use work.Types.all;
-- Entity Declaration
ENTITY VME_CONTROLLER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
reset : in std_logic;
CLK : in std_logic; -- 50MHz PCI clock, same as for CPLD
-- VME signals
v_am : IN STD_LOGIC_VECTOR(5 downto 0);
n_v_ds : IN STD_LOGIC_VECTOR(1 downto 0);
n_v_as : IN STD_LOGIC;
n_v_lw : IN STD_LOGIC;
n_v_iackin : IN STD_LOGIC;
n_v_write : IN STD_LOGIC;
n_v_sys_res : IN STD_LOGIC;
v_dtack : OUT STD_LOGIC;
v_berr : OUT STD_LOGIC;
n_v_irq : OUT STD_LOGIC;
n_v_iackout : OUT STD_LOGIC;
v_ddir : OUT STD_LOGIC;
n_v_doe : OUT STD_LOGIC_VECTOR(1 downto 0);
va : IN STD_LOGIC_VECTOR(23 downto 1);
vd : INOUT STD_LOGIC_VECTOR(31 downto 0);
ModuleAddr : in std_logic_vector(7 downto 0 );
-- spi interface for accessing the processor and serial number chip
spi_CS : in std_logic; -- SPI slave select
SPI_SI : in std_logic; -- slave in
SPI_SO : out std_logic; -- slaveout
SPI_CLK : in std_logic; -- slave clock
SPI_INT : out std_logic; -- SPI command interrupt for AVR
CPLD_STAT : out std_logic; -- RS232 ifc indicator
EXT_out : OUT STD_LOGIC_VECTOR(9 downto 1);
test_out : OUT STD_LOGIC_VECTOR(31 downto 16);
RSV : OUT STD_LOGIC_VECTOR(6 downto 0);
-- fpga programming pins: active serial and passive serial
fpga_nconfig : out std_logic; -- nconfig pulled low forces configuration
fpga_nce : out std_logic; -- nce pulled high turns off the fpga
as_asdo : out std_logic; -- AS data out for the EPCS memory
as_data : in std_logic; -- AS data for the memory
as_dclk : out std_logic; -- AD data for the memory
as_ncs : out std_logic; -- chip select for activeserial memory
-- PCI-like multiplexed communication
-- address/data bus is 16 bit wide, BE0,BE1 are used as data strobes and command lines like in PCI
IRDYn : out std_logic; -- CPLD not ready
TRDYn : in std_logic; -- FPGA not ready
FRAMEn : out std_logic; -- start of transfer
AD : inout std_logic_vector(15 downto 0); -- muletiplexed PCI-like address and data
BEn : out std_logic_vector(1 downto 0); -- word strobes / command: 01- read, 11 - write
INTn : in std_logic --interrupt
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END VME_CONTROLLER;
-- Architecture Body
ARCHITECTURE VME_CONTROLLER_architecture OF VME_CONTROLLER IS
-------------------------------------------------------------------------------
-- declaration of components used
-------------------------------------------------------------------------------
-- as programmer
component as_programmer
port (
testout : out std_logic;
clk : in std_logic;
reset : in std_logic;
fpga_nconfig : out std_logic;
fpga_nce : out std_logic;
as_asdo : out std_logic; -- AS data out for the EPCS memory
as_data : in std_logic; -- AS data for the memory
as_dclk : out std_logic; -- AD data for the memory
as_ncs : out std_logic; -- chip select for activeserial memory
dataIn : in std_logic_vector(31 downto 0);
dataOut : out std_logic_vector(7 downto 0); -- every data read are just 8 bits
dataRdy : out std_logic;
startRead : in std_logic;
startWrite : in std_logic);
end component;
-- spi interface:
component spi_link
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
SCK : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
SCS : in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
command_out : out STD_LOGIC_VECTOR(7 downto 0);
write_en : out STD_LOGIC;
transfer_done : out STD_LOGIC;
byte_sel : out STD_LOGIC_VECTOR (3 downto 0);
addr_sel : out STD_LOGIC_VECTOR (1 downto 0);
testout : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
------------------------------------------------------------------------------
-- declaration of signals
-------------------------------------------------------------------------------
----------------------
-- Signal Declaration
----------------------
Constant setad : std_logic_vector(23 downto 0) := x"ff0000"; --board base address
-- VME Signals
SIGNAL v_adsel,
resetn : STD_LOGIC ;
SIGNAL valid_am,
blt,blt_flag : STD_LOGIC ;
SIGNAL valid_address : STD_LOGIC ;
SIGNAL ad_reg : STD_LOGIC_VECTOR (15 DOWNTO 0);
-- Internal Registers
SIGNAL int_ad_reg : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL data_reg : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL intbus : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- Readout signals
SIGNAL data_buffer_oe_0 : STD_LOGIC;
SIGNAL data_buffer_oe_1 : STD_LOGIC;
SIGNAL int_dtack,
data_wren : STD_LOGIC;
signal VME_BE_command : STD_LOGIC_VECTOR(4 downto 0);
SIGNAL IFC_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL IFC_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL IFC_valid_address : STD_LOGIC;
--SPI block signals
signal spi_data_in : std_logic_vector(7 downto 0);
signal spi_data_out,SPI_testout : std_logic_vector(7 downto 0);
signal spi_write_en, spi_transfer_done : std_logic;
signal spi_byte_sel : std_logic_vector(3 downto 0);
signal spi_addr_sel : std_logic_vector(1 downto 0);
signal spi_command_out : std_logic_vector(7 downto 0);
signal spi_address : std_logic_vector(15 downto 0);
signal SPI_data_o,SPI_data_i : std_logic_vector(31 downto 0);
SIGNAL Controlled_by_SPI, SPI_valid_address : STD_LOGIC ;
signal programmingFinished,
writeProgrammerData,
readProgrammerData : std_logic;
-- '1' announces that the operation of programmer is finished and thus
-- we can pull dtack low in order to finish the write operation
signal programmerData,ProgrammerData_in,
CPLD_Config,
CPLD_Status : std_logic_vector(31 downto 0);
-- address decoder signals
signal SERIALaddressed,
CPLD_CFG_addressed,
SPIaddressed,
ProgrammerAddressed,
n_v_write_synchr,
CPLD_addressed : std_logic;
signal n_v_ds_synchr : std_logic_vector(1 downto 0);
signal SPI_data : std_logic_vector(31 downto 0) ;
signal SERIAL_data,
FPGA_AD : std_logic_vector(31 downto 0) ;
--VME-PCI state machine
TYPE STATE_TYPE IS (
idle,
address_phase,
SPI_selected,
SPI_address_phase,
data_MSB_phase_WR,
data_LSB_phase_WR,
data_MSB_phase_RD,
data_LSB_phase_RD,
generate_DTACK,
go_burst
);
SIGNAL state: STATE_TYPE;
BEGIN
--------------------
-- Logic Section
--------------------
ad_reg(0) <= '0';
--controller responds to some subset of transfers only
valid_am <= '1' WHEN (( v_am (5 DOWNTO 0) = "111001" )
OR ( v_am (5 DOWNTO 0) = "111010" )
OR ( v_am (5 DOWNTO 0) = "111101" )
OR ( v_am (5 DOWNTO 0) = "111110" )
OR ( v_am (5 DOWNTO 0) = "111011" )
OR ( v_am (5 DOWNTO 0) = "111111" ))
ELSE '0';
--block transfer detection
blt <= '1' WHEN ((( v_am (5 DOWNTO 0) = "111011" ) OR ( v_am (5 DOWNTO 0) = "111111" ))) ELSE '0';
-- controller selected
v_adsel <= '1' WHEN (( va ( 23 DOWNTO 16 )) = (ModuleAddr(7 downto 0))) ELSE '0';
Address_gen : PROCESS (CLK, n_v_sys_res)
BEGIN
--address latching
IF n_v_sys_res = '0' THEN
valid_address <= '0';
ad_reg (15 DOWNTO 1) <= (OTHERS => '0');
ELSIF Rising_edge (CLK ) THEN
IF n_v_as ='0' AND valid_am = '1' AND v_adsel ='1' THEN
ad_reg (15 DOWNTO 1) <= va (15 DOWNTO 1);
END IF;
--valid address generation
IF ( n_v_as AND n_v_ds (1) AND n_v_ds (0)) = '1' THEN
valid_address <= '0';
ELSIF (not n_v_as AND valid_am AND v_adsel ) = '1' OR valid_address = '1' THEN
valid_address <= '1';
END IF;
-- block trnasfer flag genration
IF n_v_as = '1' THEN
blt_flag <= '0' ;
ELSIF ( blt AND v_adsel AND NOT n_v_as ) = '1' THEN
blt_flag <= '1';
END IF;
END IF;
END PROCESS Address_gen;
-- VME BERR Generation
v_berr <= '0';
-- VME IRQ Generation
n_v_irq <= '0';
n_v_iackout <= not n_v_iackin;
-------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------ VME-PCI state machine -----------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------------
--VME signals synchronisation:
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '0' THEN
n_v_ds_synchr <= n_v_ds;
n_v_write_synchr <= n_v_write;
end if;
end process;
PROCESS (clk,reset)
BEGIN
IF reset = '1' or IFC_valid_address = '0' THEN
--IF reset = '1' THEN
state <= idle;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle =>
IF valid_address = '1' and (n_v_ds_synchr(1) ='0' or n_v_ds_synchr(0) = '0') THEN
Controlled_by_SPI <= '0';
state <=address_phase;
elsif spi_addr_sel(0) = '1' then --start PCi transaction just after latching first address
Controlled_by_SPI <= '1';
state <=SPI_Selected;
END IF;
when address_phase =>
IF valid_address = '1' and (n_v_ds_synchr(1) ='0' or n_v_ds_synchr(0) = '0') and n_v_write_synchr = '0' THEN
state <=data_MSB_phase_WR; --start PCI write
ELSIF valid_address = '1' and (n_v_ds_synchr(1) ='0' or n_v_ds_synchr(0) = '0') and n_v_write_synchr = '1' THEN
state <=data_MSB_phase_RD; --start PCI read
ELSE
state <= idle;
END IF;
when SPI_Selected =>
if spi_command_out(7)= '0' or (spi_command_out(7)= '1' and spi_byte_sel(0) = '1' and spi_write_en = '1') then
state <= SPI_address_phase;
end if;
when SPI_address_phase =>
if spi_command_out(7)= '0' then
state <=data_MSB_phase_RD; --start PCI read
ELSe --make sure that all the data is latched
state <=data_MSB_phase_WR; --start PCI write
END IF;
----------------------------- PCI-like write trnsaction
when data_MSB_phase_WR =>
if CPLD_addressed = '1' then -- CPLD registers transfer - bypass all PCI transaction mechanism
state <= generate_DTACK;
elsIF TRDYn = '0' THEN --wait until target gets ready
state <=data_LSB_phase_WR;
ELSIF IFC_valid_address = '0' then
state <= idle;
END IF;
when data_LSB_phase_WR =>
IF IFC_valid_address = '0' then
state <= idle;
ELSif ProgrammerAddressed = '0' and TRDYn = '0' then
-- if ProgrammerAddressed = '0' and TRDYn = '0' then
state <= generate_DTACK;
elsif ProgrammerAddressed = '1' and programmingFinished = '1' then --hold data ACK until serial trnasfer is completed
state <= generate_DTACK;
END IF;
------------------------------- PCI-like read trnsaction
when data_MSB_phase_RD =>
if CPLD_addressed = '1' then -- CPLD registers transfer - bypass all PCI transaction mechanism
state <= generate_DTACK;
elsIF TRDYn = '0' THEN --wait until target gets ready
state <=data_LSB_phase_RD;
ELSIF IFC_valid_address = '0' then
state <= idle;
END IF;
when data_LSB_phase_RD =>
IF IFC_valid_address = '0' then
state <= idle;
ELSif (ProgrammerAddressed = '0' and TRDYn = '0') then
--if (ProgrammerAddressed = '0' and TRDYn = '0') then
state <= generate_DTACK;
elsif ProgrammerAddressed = '1' and programmingFinished = '1' then --hold data ACK until serial trnasfer is completed
state <= generate_DTACK;
END IF;
----------------------------- PCI-like transaction end or block trnasfers
when generate_DTACK =>
if Controlled_by_SPI = '1' then
state <= idle;
elsif IFC_valid_address = '0' then
state <= idle;
elsif (CPLD_addressed = '1' and n_v_ds_synchr(1) ='1' and n_v_ds_synchr(0) = '1') then -- CPLD transfer only
state <= idle;
elsif (n_v_ds_synchr(1) ='1' and n_v_ds_synchr(0) = '1') and blt_flag = '1' THEN --block transfers
state <= go_burst;
elsif (n_v_ds_synchr(1) ='1' and n_v_ds_synchr(0) = '1') THEN --non-block transfers
state <= idle;
END IF;
when go_burst => --block transfers only -wait for the next data cycle
IF IFC_valid_address = '1' and (n_v_ds_synchr(1) ='0' or n_v_ds_synchr(0) = '0') and n_v_write_synchr = '0' THEN
state <=data_MSB_phase_WR; --start PCI write
ELSIF IFC_valid_address = '1' and (n_v_ds_synchr(1) ='0' or n_v_ds_synchr(0) = '0') and n_v_write_synchr = '1' THEN
state <=data_MSB_phase_RD; --start PCI read
elsif IFC_valid_address = '0' then
state <= idle;
END IF;
when others =>
state <=idle;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
IRDYn <= '1' when address_phase,
'1' when SPI_address_phase,
'0' when data_MSB_phase_WR,
'0' when data_LSB_phase_WR,
'0' when data_MSB_phase_RD,
'0' when data_LSB_phase_RD,
'1' when go_burst,
'1' when others;
WITH state SELECT
FRAMEn <= '0' when address_phase,
'0' when SPI_address_phase,
'0' when data_MSB_phase_WR,
'0' when data_LSB_phase_WR,
'0' when data_MSB_phase_RD,
'0' when data_LSB_phase_RD,
'0' when generate_DTACK,
'0' when go_burst,
'1' when others;
WITH state SELECT
BEn <= (not n_v_write_synchr) & '1' when address_phase,
(spi_command_out(7)) & '1' when SPI_address_phase,
(not spi_command_out(7)) & '1' when SPI_Selected,
"01" when data_MSB_phase_WR,
"10" when data_LSB_phase_WR,
"01" when data_MSB_phase_RD,
"10" when data_LSB_phase_RD,
"11" when others;
WITH state SELECT
v_dtack <= '1' when generate_DTACK, --dtack is inverted (ext inverter)
'0' when others;
WITH state SELECT
data_wren <= '1' when data_MSB_phase_WR, --data strobe for VME registers
'0' when others;
WITH state SELECT
AD <= "00" & IFC_address(15 downto 2) when address_phase,
"00" & IFC_address(15 downto 2) when SPI_address_phase,
"00" & IFC_address(15 downto 2) when SPI_Selected,
IFC_data(31 downto 16) when data_MSB_phase_WR,
IFC_data(15 downto 0) when data_LSB_phase_WR,
(others => 'Z') when data_MSB_phase_RD,
(others => 'Z') when data_LSB_phase_RD,
(others => 'Z') when generate_DTACK,
(others => 'Z') when others;
-------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------ FPGA read data buffer -----------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
PROCESS (CLK, n_v_sys_res)
begin
if n_v_sys_res = '0' THEN
FPGA_AD <= (others => '0');
ELSIF Rising_edge ( CLK ) THEN
if state = data_MSB_phase_RD and TRDYn = '0' then
FPGA_AD(31 downto 16) <= AD;
elsif state = data_LSB_phase_RD and TRDYn = '0' then
FPGA_AD(15 downto 0) <= AD;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------ Data Buffer Chip Control -----------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- one CLK period delay od output enable lines to increase data hold time
process (clk, n_v_sys_res)
begin
if n_v_sys_res = '0' THEN
VME_BE_command <= (others => '1');
elsif rising_edge(clk) then
VME_BE_command <= n_v_ds(1) & n_v_ds(0) & va(1) & n_v_lw & n_v_write;
end if;
end process;
-- CPLD_3_state_buffer0_control:
with VME_BE_command select
data_buffer_oe_0 <= valid_address when "00011", --byte 01
valid_address when "00001", --bytes 0123
'0' when others;
-- CPLD_3_state_buffer1_control:
with VME_BE_command select
data_buffer_oe_1 <= valid_address when "00111", --byte 23
valid_address when "00001", --bytes 0123
'0' when others;
-- VME_card_3_state_buffer0_control:
with VME_BE_command(4 downto 1) select
n_v_doe (0) <= (not valid_address) when "0001", --byte 01
(not valid_address) when "0000", --bytes 0123
'1' when others;
-- VME_card_3_state_buffer1_control:
with VME_BE_command(4 downto 1) select
n_v_doe (1) <= (not valid_address) when "0011", --byte 23
(not valid_address) when "0000", --bytes 0123
'1' when others;
--VME buffers direction
v_ddir <= NOT n_v_write;
-- VME 3 state buffer
lo_data_bus_driver : lpm_bustri
GENERIC MAP (LPM_WIDTH => 16
)
PORT MAP (data => intbus ( 15 DOWNTO 0),
enableDT => data_buffer_oe_0,
enableTR => '1',
tridata => vd ( 15 DOWNTO 0)
);
hi_data_bus_driver : lpm_bustri
GENERIC MAP (LPM_WIDTH => 16
)
PORT MAP (data => intbus ( 31 DOWNTO 16),
enableDT => data_buffer_oe_1,
enableTR => '1',
tridata => vd ( 31 DOWNTO 16)
);
-------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------ SPI/VME multiplexer-----------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
IFC_data <= vd when Controlled_by_SPI = '0' else SPI_data_o;
IFC_address <= ad_reg when Controlled_by_SPI = '0' else SPI_address;
IFC_valid_address <= valid_address or not SPI_CS;
CPLD_STAT <= Controlled_by_SPI AND SPI_CS;
-------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------ address decoder --------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
SPIaddressed <= '1' WHEN IFC_valid_address = '1' AND "00" & IFC_address( 15 DOWNTO 2 ) = X"3FF0" ELSE '0'; --FFC0
ProgrammerAddressed <= '1' WHEN IFC_valid_address = '1' AND "00" & IFC_address( 15 DOWNTO 2 ) = X"3FF1" ELSE '0'; --FFC4
SERIALaddressed <= '1' WHEN IFC_valid_address = '1' AND "00" & IFC_address( 15 DOWNTO 2 ) = X"3FF2" ELSE '0'; --FFC8
CPLD_CFG_addressed <= '1' WHEN IFC_valid_address = '1' AND "00" & IFC_address( 15 DOWNTO 2 ) = X"3FF3" ELSE '0'; --FFCC
--skip PCI tranfer when CPLD registers are addressed
CPLD_addressed <= SPIaddressed or ProgrammerAddressed or SERIALaddressed or CPLD_CFG_addressed;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------- CPLD registers write -----------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
Wr_Regs : PROCESS ( n_v_sys_res, CLK )
BEGIN
IF n_v_sys_res = '0' THEN
SPI_data <= (OTHERS => '0');
-- SERIAL_data <= (OTHERS => '0');
-- ProgrammerData <= (OTHERS => '0');
CPLD_Config <= (OTHERS => '0');
ELSIF Rising_edge ( CLK) THEN
--writing VME data to registers
IF SPIaddressed = '1' AND data_wren='1' THEN
SPI_data <= IFC_data ;
END IF;
-- IF SERIALaddressed = '1' AND data_wren='1' THEN --read only
-- SERIAL_data <= IFC_data;
-- END IF;
IF CPLD_CFG_addressed = '1' AND data_wren='1' THEN
CPLD_Config <= IFC_data ;
END IF;
END IF;
END PROCESS Wr_Regs;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------- CPLD registers read -----------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
intbus (31 DOWNTO 0) <= SPI_data WHEN SPIaddressed = '1'
ELSE SERIAL_data WHEN SERIALaddressed = '1'
-- ELSE ProgrammerData_in WHEN ProgrammerAddressed = '1'
ELSE x"12345678" WHEN ProgrammerAddressed = '1'
ELSE CPLD_Status WHEN CPLD_CFG_addressed = '1'
ELSE FPGA_AD ; --all other transfers come from FPGA
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------- SPI block instantiation -----------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- spi memory interface accesible via VME
spi_link_1: spi_link
port map (
clk => clk,
reset => reset,
SCK => SPI_CLK,
SDI => SPI_SI,
SDO => SPI_SO ,
SCS => SPI_CS,
data_in => spi_data_in,
data_out => spi_data_out,
command_out => spi_command_out,
write_en => spi_write_en,
transfer_done => spi_transfer_done,
byte_sel => spi_byte_sel,
addr_sel => spi_addr_sel,
testout => SPI_testout );
--SPI_data_i <= x"12345677";
SPI_data_i <= intbus;
--SPi output data register write
process (reset,Clk)
begin
if reset='1' then
SPI_data_o <=(others => '0');
elsif rising_edge(Clk) then
--latch SPI data
if spi_byte_sel(0) = '1' and spi_write_en = '1' then
SPI_data_o(7 downto 0) <= spi_data_out;
elsif spi_byte_sel(1) = '1' and spi_write_en = '1' then
SPI_data_o(15 downto 8) <= spi_data_out;
elsif spi_byte_sel(2) = '1' and spi_write_en = '1' then
SPI_data_o(23 downto 16) <= spi_data_out;
elsif spi_byte_sel(3) = '1' and spi_write_en = '1' then
SPI_data_o(31 downto 24) <= spi_data_out;
end if;
--latch SPI address
if spi_addr_sel(0) = '1' then
SPI_address(7 downto 0) <= spi_data_out;
elsif spi_addr_sel(1) = '1' then
SPI_address(15 downto 8) <= spi_data_out;
end if;
end if;
end process;
--SPI COMMAND
with spi_byte_sel select
spi_data_in <= SPI_data_i(7 downto 0) when "0001",
SPI_data_i(15 downto 8) when "0010",
SPI_data_i(23 downto 16) when "0100",
SPI_data_i(31 downto 24) when others;
process (reset,Clk)
begin
if reset='1' then
SERIAL_data <=(others => '0');
elsif rising_edge(Clk) then
if SPI_address = X"FFC8" and spi_transfer_done = '1' and spi_command_out(7) = '1' then
SERIAL_data <= SPI_data_o;
end if;
end if;
end process;
SPI_INT <= not (SPIaddressed and not n_v_write);
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------- EPCS programmer block instantiation ----------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
resetn <= not reset;
writeProgrammerData <= ProgrammerAddressed and data_wren;
readProgrammerData <= ProgrammerAddressed and n_v_write;
-- active serial programmer interface:
as_programmer_2: as_programmer
port map (
testout => open,
clk => clk,
reset => resetn, -- not reset
fpga_nconfig => fpga_nconfig,
fpga_nce => fpga_nce,
dataIn => IFC_data,
dataOut => ProgrammerData_in(7 downto 0),
as_asdo => as_asdo,
as_data => as_data,
as_dclk => as_dclk,
as_ncs => as_ncs,
dataRdy => programmingFinished,
startRead => readProgrammerData,
startWrite => writeProgrammerData);
-- process to change the state signal and initialize
--internal signals
--test_out(23 downto 16) <= va(23 downto 16);
--test_out(31 downto 24) <= "00" & v_am (5 DOWNTO 0);
-- RSV(3) <=n_v_as ;
-- RSV(4) <=IFC_valid_address ;
-- RSV(5) <=v_adsel ;
-- RSV(6) <=valid_am ;
--test_out <= spi_data_in & spi_data_out;
--test_out(16) <= clk;
--test_out(17) <= SERIALaddressed;
--test_out(18) <= IFC_valid_address;
--test_out(19) <= valid_address;
--test_out(20) <= spi_byte_sel(0);
--test_out(21) <= spi_byte_sel(1);
--test_out(22) <= spi_byte_sel(2);
--test_out(23) <= spi_byte_sel(3);
--test_out(24) <= SPI_SI;
--test_out(25) <= SPI_CLK;
--test_out(26) <= Controlled_by_SPI;
--test_out(27) <= spi_write_en;
--test_out(31 downto 28) <= spi_testout(7 downto 4);
test_out(31 downto 16) <= IFC_address;
EXT_out(1) <= clk;
EXT_out(2) <= SERIALaddressed;
EXT_out(3) <= IFC_valid_address;
EXT_out(4) <= Controlled_by_SPI;
EXT_out(5) <= valid_am;
EXT_out(6) <= n_v_as;
EXT_out(7) <= valid_address;
EXT_out(8) <= v_adsel;
--EXT_out(8 downto 5) <= spi_testout(7 downto 4);
--EXT_out <= SERIAL_data(7 downto 0);
--EXT_out(8 downto 1) <= spi_testout;
--EXT_out <= CPLD_Config (7 downto 0);
CPLD_Status(7 downto 0) <= CPLD_Config (7 downto 0);
CPLD_Status(8) <= not SPI_CS;
END VME_CONTROLLER_architecture;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/as_programmer.vhd 0 → 100644
View file @ f7ea7ecc
-- works as follows: the last address from the register space (in our
-- case "111" is dedicated to the programming port. It consists of
-- 8 bit register + some signals. Programming is done by sending
-- multiple commands over the VME interface. The programming register
-- bits have following meaning:
-- X X X X X X X X X X X X X X X X X X X X X X X X 7 6 5 4 3 2 1 0
-- ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
-- | | | | | +-+-+-+-+-+-+-+---- DATA TO BE SHIFTED INTO THE MEMORY
-- | | | | +-------------------- FPGA nCE
-- | | | +---------------------- FPGA nCONFIG
-- | | +------------------------ DATA TO WRITE VALID
-- | +-------------------------- CONFIG TO WRITE VALID
-- +---------------------------- ACTIVE SERIAL MEMORY CHIP SELECT
-- the rest of the registers can be used as general purpose because
-- as long as 'DATA TO WRITE VALID' is '0', no action is taken. When
-- it contains '1', immediatelly after the data are got, it is written
-- into the memory.
-- The same concerns the 'CONFIG TO WRITE VALID', which handles the
-- nCONFIG and nCE signals
-- NOTE: THIS CODE DOESN"T SUPPORT READING FROM THE MEMORY. As this
-- function is not very useful when you program your stuff
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.Types.all;
entity as_programmer is
port (
testout : out std_logic;
clk : in std_logic; -- clock
reset : in std_logic; -- reset
-- fpga output pins
fpga_nconfig : out std_logic; -- nconfig is mapped into one register
-- bit
fpga_nce : out std_logic; -- chip enable mapped into one bit
as_asdo : out std_logic; -- AS data out for the EPCS memory
as_data : in std_logic; -- AS data for the memory
as_dclk : out std_logic; -- AS clock shifhed into EPCS device
as_ncs : out std_logic; -- AS chip enable, active low
dataIn : in VLong; -- data to be written into the AS interface
dataOut : out VByte; -- every data read are just 8 bits
dataRdy : out std_logic; -- when '1' then it announces that the
-- operation is finished
startRead : in std_logic; -- '1' pulse starts read process
startWrite : in std_logic); -- '1' pulse starts the write of the data into the stuff
end as_programmer;
architecture as_programmer of as_programmer is
-------------------------------------------------------------------------------
-- component declarations
-------------------------------------------------------------------------------
component clkdivider
generic (
divider : integer);
port (
clk : in std_logic;
reset : in std_logic;
clkenable : out std_logic);
end component;
-------------------------------------------------------------------------------
-- types
-------------------------------------------------------------------------------
type States is (Idle, WriteControl, FinishOperation, WriteData, WaitDataWritten, ReadData, WaitDataRead); -- defines states of the statemachine for programming
-------------------------------------------------------------------------------
-- signals
-------------------------------------------------------------------------------
-- clock enable for the processes interacting with active serial interface.
signal prgclkenable : std_logic;
signal CurrentState : States; -- current state of the machine
signal NextState : States; -- next state of the machine. These are asynchronous but registered
signal ShiftRegister : VByte; -- asynchronously loaded shift register
signal ShiftFinished : std_logic; -- '1' when finished shifting of the data
signal ShiftLoad : std_logic; -- '1' to force the loading of the register
signal ShiftCnt : std_logic_vector(3 downto 0); -- counter for shift
signal DataDirection : std_logic; -- '1' for shifting the data from the memory to the VME, '0' VME->MEMORY
signal as_asdo_in : std_logic; -- non-tristate copy of the signal
signal weAreMaster : std_logic; -- '1' when it is us who puts fpga into off state and requests the activeserial bus
signal dataOut_in : VByte; -- used to readback the data
signal Counter : std_logic_vector(1 downto 0); -- counter for clock output to memory
begin -- as_programmer
-------------------------------------------------------------------------------
-- instances of the components:
-------------------------------------------------------------------------------
clkdivider_1: clkdivider
generic map (
divider => 4)
port map (
clk => clk,
reset => reset,
clkenable => prgclkenable);
-------------------------------------------------------------------------------
-- asynchronous assignments
-------------------------------------------------------------------------------
testout <= weAreMaster;
as_dclk <= Counter(1) when weAreMaster = '1' else 'Z';
as_asdo <= as_asdo_in when (weAreMaster = '1' and DataDirection='0') else 'Z';
dataOut <= dataOut_in;
-------------------------------------------------------------------------------
-- processes
-------------------------------------------------------------------------------
-- shift register
process (clk, reset, ShiftLoad, dataIn, DataDirection)
begin -- process
-- asynchronous load and reset
if reset = '0' then -- asynchronous reset (active low)
as_asdo_in <= '0';
ShiftCnt <= "0000";
ShiftFinished <= '1';
elsif ShiftLoad = '1' then
-- this instruction is valid only for writing,
-- however it doesn't harm when reading!
ShiftRegister <= dataIn(ShiftRegister'range);
ShiftCnt <= "1000";
ShiftFinished <= '0';
-- synchronous process driven by slow clock
elsif clk'event and clk = '1' then -- rising clock edge
if prgclkenable = '1' and ShiftCnt /= "0000" then
-- this process is driven by slow clock
as_asdo_in <= ShiftRegister(ShiftRegister'left);
-- shift data in
dataOut_in <= dataOut_in (dataOut_in'left-1 downto 0) & as_data;
-- and out. But out goes through tristate buffer :)
ShiftRegister <= ShiftRegister(ShiftRegister'left-1 downto 0) & '0';
ShiftCnt <= ShiftCnt - '1';
elsif prgclkenable = '1' and ShiftCnt = "0000" then
ShiftFinished <= '1';
end if;
end if;
end process;
-- process generating dclk trigger. Simple counter used as divider, but
-- with count enable
process (clk, reset, ShiftLoad)
begin -- process
-- asynchronous reset is also linked to restart of counting when
-- sending/receiving next data, otherwise we could never assure
-- at which edge the clock starts
if reset = '0' or ShiftLoad = '1' then -- asynchronous reset (active low)
Counter <= STD_LOGIC_VECTOR(TO_UNSIGNED (0, Counter'length));
elsif clk'event and clk = '1' then -- rising clock edge
if ShiftFinished = '0' and ShiftCnt /= "1000"
then
-- clock is enabled, count to
Counter <= Counter - '1';
end if;
end if;
end process;
-- the state is changed on falling edge because all the inputs are read on
-- rising one
process (clk, reset)
begin -- process
if reset = '0' then -- asynchronous reset (active low)
CurrentState <= Idle;
elsif clk'event and clk = '0' then -- rising clock edge
CurrentState <= NextState;
end if;
end process;
process (CurrentState, startWrite, ShiftFinished, dataIn, startRead)
begin -- process
case CurrentState is
when Idle =>
if startWrite = '1' and dataIn(11) = '1' then
-- writing of nCONFIG and nCE and nCS
NextState <= WriteControl;
elsif startWrite = '1' and dataIn(10) = '1' then
-- writing of data present into the shift register
NextState <= WriteData;
elsif startRead = '1' then
-- reading from memory
NextState <= ReadData;
else
NextState <= Idle;
end if;
when ReadData =>
NextState <= WaitDataRead;
when WaitDataRead =>
-- wait till the operation is complete and shift register contains the
-- data
if ShiftFinished = '1' then
NextState <= FinishOperation;
else
NextState <= WaitDataRead;
end if;
when WriteData =>
NextState <= WaitDataWritten;
when WaitDataWritten =>
if ShiftFinished = '1' then
NextState <= FinishOperation;
else
NextState <= WaitDataWritten;
end if;
when WriteControl =>
NextState <= FinishOperation;
when others =>
NextState <= Idle;
end case;
end process;
process (clk, reset)
begin -- process
if reset = '0' then -- asynchronous reset (active low)
dataRdy <= '0';
fpga_nconfig <= 'Z'; -- config and CE is driven by pullup resistances
fpga_nce <= 'Z';
ShiftLoad <= '0';
as_ncs <= 'Z';
DataDirection <= '1'; -- read by default -> asdi tristated
weAreMaster <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case CurrentState is
when WriteControl =>
-- set the status of nCONFIG and nCE depending on
-- data pins. When the signal is inactive, we drive into
-- high impedance instead of logic level. This is because
-- there are pull-up/dn resistors installed on these pins
-- dataIn(8) corresponds to fpga chip select
if dataIn(8) = '1' then
fpga_nce <= '1';
else
fpga_nce <= 'Z' ;
end if;
-- dataIn(9) corresponds to fpga nconfig pin
if dataIn(9) = '0' then
fpga_nconfig <= '0';
else
fpga_nconfig <= 'Z';
end if;
-- dataIn(12) is chip select for the active serial memory
if dataIn(12) = '0' then
as_ncs <= '0';
else
as_ncs <= 'Z';
end if;
-- if fpga is inactive by our interaction, it is us who takes
-- the control over the activeserial bus, thus we indicate this
-- by bit flag, which turns off the tri-state buffer on dclk and
-- asdi.
if dataIn(8) = '1' and dataIn(9) = '0' then
weAreMaster <= '1';
else
weAreMaster <= '0';
end if;
when ReadData =>
ShiftLoad <= '1';
DataDirection <= '1';
when WriteData =>
-- we load the stuff into the shift register. Data are on the
-- fpga_ad bus so we have to store them into the register
ShiftLoad <= '1';
DataDirection <= '0';
when WaitDataWritten =>
ShiftLoad <= '0';
when FinishOperation =>
dataRdy <= '1';
when others =>
ShiftLoad <= '0';
dataRdy <= '0';
end case;
end if;
end process;
end as_programmer;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/clock_divider.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clkdivider is
generic (
divider : integer := 2); -- number of clocks to generate enable pulse
port (
clk : in std_logic; -- general clock
reset : in std_logic; -- async reset
clkenable : out std_logic); -- clock enable used to turn on the clock
end clkdivider;
architecture v1 of clkdivider is
begin -- v1
-- purpose: counts down to zero and when at zero, then it generates clkenable pulse which is exactly 1 tick lock
-- type : sequential
-- inputs : clk, reset
count: process (clk, reset)
variable counter : integer range divider downto 0;
-- counter stuff
begin -- process count
if reset = '0' then -- asynchronous reset (active low)
counter := divider; -- set the state to the divider val.
elsif clk'event and clk = '0' then -- rising clock edge
counter := counter - 1; -- decrease counts
if counter = 0 then
counter := divider;
clkenable <= '1';
else
clkenable <= '0';
end if;
end if;
end process count;
end v1;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/shiftreg.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: shiftreg.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY shiftreg IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
END shiftreg;
ARCHITECTURE SYN OF shiftreg IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC ;
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
shiftout <= sub_wire1;
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 8
)
PORT MAP (
enable => enable,
load => load,
sclr => sclr,
clock => clock,
data => data,
shiftin => shiftin,
q => sub_wire0,
shiftout => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_inst.vhd FALSE
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/spi_link.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity spi_link is
PORT
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
SCK : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
SCS : in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
command_out : out STD_LOGIC_VECTOR( 7 downto 0);
write_en : out STD_LOGIC;
transfer_done : out STD_LOGIC;
byte_sel : out STD_LOGIC_VECTOR (3 downto 0);
addr_sel : out STD_LOGIC_VECTOR (1 downto 0);
testout : out STD_LOGIC_VECTOR (7 downto 0)
);
end spi_link ;
architecture a of spi_link is
TYPE STATE_TYPE IS (
idle,
cs_low,
clk_h,
wait_clk_l,
clk_l,
latch_cmd,
latch_byte,
transfer_end
);
SIGNAL state: STATE_TYPE;
signal bit_count : integer range 0 to 8;
signal byte_count : integer range 0 to 7;
signal command : std_logic_vector(7 downto 0);
signal write_nread : std_logic;
signal shift_dat_in : std_logic_vector(7 downto 0);
signal shift_dat_out : std_logic_vector(7 downto 0);
signal shift_en : std_logic;
signal shift_load : std_logic;
signal shift_sclr,SCK_synch,SDI_synch,SCS_synch,
update_byte,
load_byte,
transfer_done_tmp,transfer_done_edge_det,
shift_din : std_logic;
signal byte_sel_tmp : std_logic_vector(3 downto 0);
component shiftreg
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enable : IN STD_LOGIC ;
load : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
end component;
begin -- a
--***********************************************************************************************************************************************
--******************************************* main control state machine *********************************************************************
--***********************************************************************************************************************************************
--input signals synchronisation
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
SCK_synch <= '0';
SDI_synch <= '0';
SCS_synch <= '0';
ELSIF clk'EVENT AND clk = '0' THEN
SCK_synch <= SCK;
SDI_synch <= SDI;
SCS_synch <= SCS;
end if;
end process;
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
state <= idle;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle =>
byte_count <= 0;
command <= (others => '0');
IF SCS_synch = '0' THEN
state <=cs_low;
END IF;
when cs_low =>
bit_count <= 8;
IF SCK_synch = '1' THEN
state <=clk_h;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when clk_h =>
bit_count <= bit_count - 1;
state <=wait_clk_l;
when wait_clk_l =>
IF SCK_synch = '0' THEN
state <=clk_l;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when clk_l =>
IF bit_count = 0 and byte_count = 0 THEN
state <=latch_cmd;
ELSIF bit_count = 0 and byte_count /= 0 THEN
state <=latch_byte;
ELSIF SCK_synch = '1' THEN
state <=clk_h;
ELSIF SCS_synch = '1' THEN
state <=idle;
END IF;
when latch_cmd =>
byte_count <= byte_count + 1 ;
command <= shift_dat_out;
state <=cs_low;
when latch_byte =>
byte_count <= byte_count + 1 ;
IF byte_count = 6 THEN
state <=transfer_end;
ELSIF SCS_synch = '1' THEN
state <=idle;
else
state <=cs_low;
END IF;
when transfer_end =>
IF SCS_synch = '1' THEN
state <=idle;
END IF;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
shift_sclr <= '1' when idle,
'0' when cs_low,
'0' when clk_h,
'0' when clk_l,
'0' when others;
WITH state SELECT
shift_en <= '0' when idle,
'1' when clk_h,
'1' when cs_low,
'0' when others;
WITH state SELECT
update_byte <= '0' when idle,
'1' when latch_byte,
'0' when others;
WITH state SELECT
load_byte <= '0' when idle,
'1' when cs_low,
'0' when others;
WITH state SELECT
transfer_done_tmp <= '0' when idle,
'1' when transfer_end,
'0' when others;
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
transfer_done_edge_det <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
transfer_done_edge_det <= transfer_done_tmp;
transfer_done <= transfer_done_tmp and not transfer_done_edge_det;
end if;
end process;
WITH byte_count SELECT
byte_sel_tmp <= "1000" when 3,
"0100" when 4,
"0010" when 5,
"0001" when 6,
"0000" when others;
byte_sel <= byte_sel_tmp;
addr_sel(1) <= '1' when state = latch_byte and byte_count = 1 else '0';
addr_sel(0) <= '1' when state = latch_byte and byte_count = 2 else '0';
write_nread <= command(7);
--read / write selection
shift_load <= '1' when load_byte = '1' and write_nread = '0' else '0';
write_en <= '1' when update_byte = '1' and write_nread = '1' else '0' ;
--shift_din <= SDI_synch when write_nread = '1' else '0' ;
shift_din <= SDI_synch when (write_nread = '1' or byte_count < 3) else '0' ;
command_out <= command;
shiftreg_1: shiftreg
port map (
clock => clk,
data => shift_dat_in,
enable => shift_en,
load => shift_load,
sclr => shift_sclr,
shiftin => shift_din,
q => shift_dat_out,
shiftout => SDO);
shift_dat_in <= data_in;
data_out <= shift_dat_out;
testout(0) <= shift_din;
testout(1) <= shift_en;
testout(2) <= shift_load;
testout(3) <= shift_sclr;
testout(7 downto 4) <= shift_dat_out (7 downto 4);
end a ;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/types.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package types is
-- std_logic_vector types - start with V
subtype VWord is std_logic_vector(15 downto 0); -- 16 bit word
subtype VQWord is std_logic_vector(23 downto 0); -- 24 bit vector
subtype SQWord is signed(23 downto 0); -- 24bit signed to use in arithmetics
subtype SWord is signed(15 downto 0); -- 16 bit signed stuff
subtype SByte is signed(7 downto 0); -- 8 bit signed
subtype VByte is std_logic_vector(7 downto 0); -- 8 bit unsigned vector
subtype VLong is std_logic_vector(31 downto 0); -- 32bit register
-- integer types start with I
subtype IUINT8 is integer range 0 to 255; -- integer range
subtype IUINT4 is integer range 0 to 15; -- 4 bit integer
subtype IADCAddr is integer range 6 downto 0; -- ADC address to read
subtype IQWord is integer range 0 to 16777215; -- 24 bits integer
subtype ISQWord is integer range -8388608 to 8388607; -- signed 24 bits number
-- array of vectors start with AV
type AVADCMEM is array (5 downto 0) of SWord; -- ADC memory registers
type AVACCUMULATOR is array (5 downto 0) of SQWord; -- averager
type AIACCUMULATOR is array (5 downto 0) of ISQWord; -- integer averager
type AVADCOFS is array (5 downto 0) of SWord; -- ADC offsets
type SHAREDREGISTERS is array (NATURAL range <>) of VLong;
end types;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/vme_bridge.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.Types.all;
entity vme_bridge is
port (
-- general part:
resetn : in std_logic; -- reset input, asynchronous
clk : in std_logic; -- 50MHz clk input
-- vme64x part:
xdata : inout std_logic_vector(31 downto 0); -- vme data bus
xaddr : in std_logic_vector(23 downto 1); -- vme address bus
xam : in std_logic_vector(5 downto 0); -- vme address modifier
xbufdir : out std_logic; -- vme buffer direction register
xiackoutn : out std_logic; -- interrupt acknowledge output
xiackinn : in std_logic; -- interrupt ack input
xiackn : in std_logic; -- interrupt acknowledge
xas : in std_logic; -- vme address strobe
xlwordn : in std_logic; -- lword of vme
xdsn : in std_logic_vector(1 downto 0); -- data strobes
xwriten : in std_logic; -- write from vme
xdtack : out std_logic; -- vme data acknowledge
xbufoen : out std_logic_vector(1 downto 0); -- vme buffers output enable
xirq : out std_logic; -- interrupt requesters
xsysreset : in std_logic; -- sysfail request out
-- cpld only stuff:
adrsel : in std_logic_vector(7 downto 0); -- address selector headers
-- put on cpld header conn.
-- test output:
C_EXT : out std_logic_vector(9 downto 1); -- for testing. to be erased later on
--reserved lines
CPLD_CLK : in std_logic; -- 212MHz clock
RSV3 : out std_logic;
RSV1 : out std_logic; --devsel
CPU_INT : out std_logic;
RVD1 : in std_logic;
RVD0 : in std_logic;
RVD11 : in std_logic;
RVD13 : in std_logic;
RVD12 : in std_logic;
test_lines : out std_logic_vector(31 downto 16);
PCI_CLK : out std_logic;
Main_CK_enable : out std_logic;
-- spi interface for accessing the EEPROM configuration memory + serial
-- number chip
spi_CS : IN std_logic; -- SPI slave select
SPI_SI : in std_logic; -- master in. We are master
SPI_SO : out std_logic; -- master out
SPI_SCK : in std_logic; -- we provide clock
-- fpga configuration stuff:
CPLD_prog_nCONFIG : out std_logic; -- active serial nconfig
CPLD_PROG_nCE : out std_logic; -- activeserial chip enable for fpga
CPLD_prog_CONF_DONE : in std_logic; -- activeserial CONF_DONE
CPLD_prog_DCLK : out std_logic; -- activeserial clock
CPLD_prog_DATA : in std_logic; -- activeserial output
CPLD_prog_ASDI : out std_logic; -- activeserial dataout
CPLD_prog_nCS : out std_logic; -- activeserial ncso
reconfig : in std_logic;
CPLD_STAT : out std_logic; -- LED on the front panel
FPGA_RESET : out std_logic; -- reset fpga signal
-- PCI-like multiplexed communication
-- address/data bus is 16 bit wide, BE0,BE1 are used as data strobes and command lines like in PCI
FPGA_IRDYn : out std_logic; -- CPLD not ready
FPGA_TRDYn : in std_logic; -- FPGA not ready
FPGA_FRAMEn : out std_logic; -- start of transfer
FPGA_AD : inout std_logic_vector(15 downto 0); -- muletiplexed PCI-like address and data
FPGA_BEn : out std_logic_vector(1 downto 0); -- word strobes / command: 01- read, 11 - write
FPGA_INTn : in std_logic --interrupt
);
end vme_bridge;
architecture V1 of vme_bridge is
-------------------------------------------------------------------------------
-- component definitions:
-------------------------------------------------------------------------------
-- generic vme interface
component VME_CONTROLLER
port (
reset : in std_logic;
CLK : in std_logic;
v_am : IN STD_LOGIC_VECTOR(5 downto 0);
n_v_ds : IN STD_LOGIC_VECTOR(1 downto 0);
n_v_as : IN STD_LOGIC;
n_v_lw : IN STD_LOGIC;
n_v_iackin : IN STD_LOGIC;
n_v_write : IN STD_LOGIC;
n_v_sys_res : IN STD_LOGIC;
v_dtack : OUT STD_LOGIC;
v_berr : OUT STD_LOGIC;
n_v_irq : OUT STD_LOGIC;
n_v_iackout : OUT STD_LOGIC;
v_ddir : OUT STD_LOGIC;
n_v_doe : OUT STD_LOGIC_VECTOR(1 downto 0);
va : IN STD_LOGIC_VECTOR(23 downto 1);
vd : INOUT STD_LOGIC_VECTOR(31 downto 0);
ModuleAddr : in std_logic_vector(7 downto 0);
spi_CS : in std_logic;
SPI_SI : in std_logic;
SPI_SO : out std_logic;
SPI_CLK : in std_logic;
SPI_INT : out std_logic;
EXT_out : OUT STD_LOGIC_VECTOR(9 downto 1);
test_out : OUT STD_LOGIC_VECTOR(31 downto 16);
fpga_nconfig : out std_logic;
fpga_nce : out std_logic;
as_asdo : out std_logic;
as_data : in std_logic;
as_dclk : out std_logic;
as_ncs : out std_logic;
IRDYn : out std_logic;
TRDYn : in std_logic;
FRAMEn : out std_logic;
AD : inout std_logic_vector(15 downto 0);
BEn : out std_logic_vector(1 downto 0);
INTn : in std_logic);
end component;
-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------
signal interrupts,
reset,
vbufdir,
vdtack : std_logic; -- just placeholder for irqs
signal vbufoen : std_logic_vector(1 downto 0);
signal vme_test : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- VME component instances:
-----------------------------------------------------------------------------
-- NOTE: FOR THE MOMENT THE INTERRUPT ENABLE IS DISABLED!!!!!!
reset <= not resetn;
FPGA_RESET <= reset;
VME_CONTROLLER_1: VME_CONTROLLER
port map (
reset => reset,
CLK => CLK,
--vme signals
v_am => xam,
n_v_ds => xdsn,
n_v_as => xas,
n_v_lw => xlwordn,
n_v_iackin => xiackinn,
n_v_write => xwriten,
n_v_sys_res => xsysreset,
v_dtack => vdtack,
v_berr => open,
n_v_irq => xirq,
n_v_iackout => xiackoutn,
v_ddir => vbufdir,
n_v_doe => vbufoen,
va => xaddr,
vd => xdata,
ModuleAddr => not adrsel,
--SPI signals
spi_CS => spi_CS,
SPI_SI => SPI_SI,
SPI_SO => SPI_SO,
SPI_CLK => SPI_SCK,
SPI_INT => CPU_INT,
EXT_out(8 downto 1) => C_EXT(8 downto 1),
test_out => test_lines,
--fpga config signals
fpga_nconfig => open,
fpga_nce => open,
as_asdo => open,
as_data => '0',
as_dclk => open,
as_ncs => open,
--PCI signals
IRDYn => FPGA_IRDYn,
TRDYn => FPGA_TRDYn,
FRAMEn => FPGA_FRAMEn,
AD => FPGA_AD,
BEn => FPGA_BEn,
INTn => FPGA_INTn);
--for debugging purposes - reading from OUT port (buffer type generates warnings)
xbufoen <= vbufoen;
xbufdir <= vbufdir;
xdtack <= vdtack;
CPLD_prog_nCONFIG <= 'Z';
CPLD_PROG_nCE <= 'Z';
CPLD_prog_DCLK <= 'Z';
CPLD_prog_ASDI <= 'Z';
CPLD_prog_nCS <= 'Z';
-----------------------------------------------------------------------------
-- I/O assignments:
-----------------------------------------------------------------------------
-- C_EXT(9 downto 2) <= (others => 'Z');
--C_EXT(9 downto 2) <= adrsel;
CPLD_STAT <= 'Z';
--reserved lines
-- CPLD_CLK <= 'Z'; -- 212MHz clock
RSV3 <= SPI_SI;
RSV1 <= SPI_SCK ;
--CPU_INT <= 'Z';
--RVD1 <= 'Z';
--RVD0 <= 'Z';
--RVD11 <= 'Z';
--RVD13 <= 'Z';
--RVD12 <= 'Z';
PCI_CLK <= 'Z';
Main_CK_enable <= '1';
-- test_lines(31 downto 16) <= (others => 'Z');
-- test_lines(31 downto 16)<= FPGA_AD(15 downto 0);
--test_lines(31 downto 16)<= xdata(15 downto 0);
-- test_lines(27 downto 24) <= vme_test(3 downto 0);
-- test_lines(25 downto 24) <= vbufoen ;
-- test_lines(26) <= vbufdir ;
-- test_lines(27) <= vdtack ;
-- test_lines(28) <= xwriten ;
-- test_lines(29) <= xas;
-- test_lines(31 downto 30) <= xdsn(1 downto 0);
-- test_lines(23 downto 16)<= xdata(23 downto 16);
end V1;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/vme_bridge_spi_full.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.Types.all;
entity vme_bridge is
-- polarities: when '1', the we have an inverting buffer in the way between cpld and VME connector
generic (
IrqPolarity : std_logic := '1';
DtackPolarity : std_logic := '1'
-- there is AC05 inverting buffer. FPGA has positive logic signal -> we need to invert.
-- this is the way:
);
port (
-- general part:
nreset : in std_logic; -- reset input, asynchronous
clk : in std_logic; -- 50MHz clk input
-- vme64x part:
xdata : inout std_logic_vector(31 downto 0); -- vme data bus
xaddr : in std_logic_vector(23 downto 1); -- vme address bus
xam : in std_logic_vector(5 downto 0); -- vme address modifier
xbufdir : out std_logic; -- vme buffer direction register
xiackoutn : out std_logic; -- interrupt acknowledge output
xiackinn : in std_logic; -- interrupt ack input
xiackn : in std_logic; -- interrupt acknowledge
xas : in std_logic; -- vme address strobe
xlwordn : in std_logic; -- lword of vme
xdsn : in std_logic_vector(1 downto 0); -- data strobes
xwriten : in std_logic; -- write from vme
xdtack : out std_logic; -- vme data acknowledge
xbufoen : out std_logic_vector(1 downto 0); -- vme buffers output enable
xirq : out std_logic; -- interrupt requesters
xsysreset : in std_logic; -- sysfail request out
-- cpld only stuff:
adrsel : in std_logic_vector(7 downto 0); -- address selector headers
-- put on cpld header conn.
-- test output:
C_EXT : out std_logic_vector(9 downto 1); -- for testing. to be erased later on
--reserved lines
CPLD_CLK : in std_logic; -- 212MHz clock
RSV3 : in std_logic;
CPU_INT : out std_logic;
RVD1 : in std_logic;
RVD0 : in std_logic;
RVD11 : in std_logic;
RVD13 : in std_logic;
RVD12 : in std_logic;
PCI_CLK : out std_logic;
BE : in std_logic_vector(2 downto 0);
Main_CK_enable : out std_logic;
-- spi interface for accessing the EEPROM configuration memory + serial
-- number chip
spi_CS : IN std_logic; -- SPI slave select
SPI_SI : in std_logic; -- master in. We are master
SPI_SO : out std_logic; -- master out
SPI_SCK : in std_logic; -- we provide clock
-- fpga communication stuff:
fpga_write : out std_logic; -- write strobe to fpga
fpga_read : out std_logic; -- read strobe to fpga
fpga_as : out std_logic; -- fpga address strobe (H=adr, L=dat)
fpga_ad : inout std_logic_vector(31 downto 0); -- multiplexed address
-- data bus.
fpga_drdy : in std_logic; -- when '1', the data are ready to be
-- read from FPGA. This is sort of handshaking signal
fpga_userirq : in std_logic; -- '0' is interrupt request cycle
fpga_irqdone: out std_logic; -- informs fpga about the end of IRQ cycle
AS_NCONFIG : out std_logic; -- active serial nconfig
AS_NCE : out std_logic; -- activeserial chip enable for fpga
AS_NSTATUS : out std_logic; -- activeserial nstatus
AS_DCLK : out std_logic; -- activeserial clock
AS_DATA : in std_logic; -- activeserial output
AS_ASDO : out std_logic; -- activeserial dataout
AS_NCSO : out std_logic; -- activeserial ncso
reconfig : in std_logic;
CPLD_STAT : out std_logic; -- LED on the front panel
FPGA_RESET : out std_logic); -- reset fpga signal
signal spi_data_in : std_logic_vector(7 downto 0);
signal spi_data_out : std_logic_vector(7 downto 0);
signal spi_address_out : std_logic_vector(7 downto 0);
signal spi_write_en : std_logic;
signal spi_byte_sel : std_logic_vector(7 downto 0);
end vme_bridge;
architecture V1 of vme_bridge is
-------------------------------------------------------------------------------
-- component definitions:
-------------------------------------------------------------------------------
-- generic vme interface
component vme_decoder is
generic (
AddrWidth : integer;
BaseAddrWidth : integer;
DataWidth : integer;
DirSamePolarity : std_logic;
InterruptEn : std_logic);
port (
ResetNA : in std_logic;
Clk : in std_logic;
VmeAddrA : in std_logic_vector(AddrWidth-1 downto 1 );
VmeAsNA : in std_logic;
VmeDs1NA : in std_logic;
VmeDs0NA : in std_logic;
VmeData : inout std_logic_vector(DataWidth-1 downto 0 );
VmeDir : out std_logic;
VmeDirFloat : out std_logic;
VmeBufOeN : out std_logic;
VmeWriteNA : in std_logic;
VmeLwordNA : in std_logic;
VmeIackNA : in std_logic;
IackOutNA : out std_logic;
IackInNA : in std_logic;
VmeIntReqN : out std_logic;
vmeDtackN : out std_logic;
ModuleAddr : in std_logic_vector(BaseAddrWidth-1 downto 0 );
VmeAmA : in std_logic_vector(4 downto 0 );
IntProcessed : out std_logic;
UserIntReqN : in std_logic;
UserBlocks : in std_logic;
-- spi interface for accessing the EEPROM configuration memory + serial
-- number chip
spi_CS : in std_logic; -- SPI slave select
SPI_SI : in std_logic; -- slave in
SPI_SO : out std_logic; -- slaveout
SPI_CLK : in std_logic; -- slave clock
--
--
testoutput : out std_logic; -- for testing. to be erased later on
-- fpga programming pins:
fpga_nconfig : out std_logic; -- nconfig pulled low forces configuration
fpga_nce : out std_logic; -- nce pulled high turns off the fpga
as_asdo : out std_logic; -- AS data out for the EPCS memory
as_data : in std_logic; -- AS data for the memory
as_dclk : out std_logic; -- AD data for the memory
as_ncs : out std_logic; -- chip select for activeserial memory
-- we put the fpga memory interface signals:
-- these are multiplexed communication
fpga_write : out std_logic; -- write strobe to fpga
fpga_read : out std_logic; -- read strobe to fpga
fpga_as : out std_logic; -- address/data strobe ('H' = data
fpga_ad : inout VLong; -- multiplexed address/data bus
fpga_drdy : in std_logic -- '1' when data are ready to be taken
);
end component vme_decoder;
component spi_link
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
SCK : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
SCS : in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
address_out : out STD_LOGIC_VECTOR(7 downto 0);
write_en : out STD_LOGIC;
byte_sel : out STD_LOGIC_VECTOR (3 downto 0));
end component;
-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------
signal clk1us : std_logic; -- 1us clock enable derived from main clock
signal interrupts : std_logic; -- just placeholder for irqs
signal ams : std_logic_vector(4 downto 0); -- to make correct assignment
signal dtack_in : std_logic; -- copy of the signal to be able to negate it in the case
signal IntProcessed : std_logic;
signal UserIntReqN : std_logic;
signal UserBlocks,
xbuf_O_en : std_logic;
signal reset : std_logic := '0'; -- reset - positive level
begin -- V1
-----------------------------------------------------------------------------
-- asynchronous assignments:
-----------------------------------------------------------------------------
-- all others to high impedance:
AS_NCSO <= 'Z';
AS_NSTATUS <= 'Z';
-- interrupt controller is always composed of 6 bits (not 7), so the
-- most significant is '1' (as it's negative driven)
IrqPolarity0: if IrqPolarity='0' generate
xirq <= interrupts;
end generate IrqPolarity0;
IrqPolarity1: if IrqPolarity='1' generate
xirq <= not interrupts;
end generate IrqPolarity1;
DtackPolarity0: if DtackPolarity='0' generate
xdtack <= dtack_in;
end generate DtackPolarity0;
DtackPolarity1: if DtackPolarity='1' generate
xdtack <= not dtack_in;
end generate DtackPolarity1;
-- do not block any VME actions:
UserBlocks <= '0';
-- vme interface doesn't use am2, so we don't take it into account
ams(4) <= xam(5);
ams(3) <= xam(4);
ams(2) <= xam(3);
ams(1) <= xam(1);
ams(0) <= xam(0);
-- fpga reset is for the moment driven by our reset:
-- fpga reset in hiimp mode, otherwise we cannot do anything
reset <= not nreset;
FPGA_RESET <= reset;
-----------------------------------------------------------------------------
-- VME component instances:
-----------------------------------------------------------------------------
-- NOTE: FOR THE MOMENT THE INTERRUPT ENABLE IS DISABLED!!!!!!
-- VME interface
Vme_intfce_1: vme_decoder
generic map (
AddrWidth => 24,
BaseAddrWidth => 8,
DataWidth => 32,
DirSamePolarity => '0', -- polarity of buffer direction pin
InterruptEn => '0')
port map (
-- reset and clock
ResetNA => reset,
Clk => clk,
-- vme signals
-- address
VmeAddrA => xaddr,
-- address selectors:
VmeAsNA => xas,
VmeDs1NA => xdsn(1),
VmeDs0NA => xdsn(0),
VmeLwordNA => xlwordn,
VmeWriteNA => xwriten,
vmeDtackN => dtack_in,
VmeAmA => ams,
-- data bus vme:
VmeData => xdata,
-- buffers for VME bus:
VmeDir => xbufdir,
VmeBufOeN => xbuf_O_en ,
-- interupt requesters:
VmeIackNA => xiackn,
IackOutNA => xiackoutn,
IackInNA => xiackinn,
VmeIntReqN => interrupts,
-- module address is given by switches
ModuleAddr => adrsel,
-- EEPROM SPI interface
spi_CS => spi_CS,
SPI_SO => SPI_SO,
SPI_SI => SPI_SI,
SPI_CLK => SPI_SCK,
-- test output
testoutput => C_EXT(1),
-- interrupt requests routed to fpga:
UserIntReqN => fpga_userirq,
IntProcessed => fpga_irqdone,
-- programming pins of activeserial
fpga_nconfig => AS_NCONFIG,
fpga_nce => AS_NCE,
as_data => AS_DATA,
as_dclk => AS_DCLK,
as_ncs => AS_NCSO,
as_asdo => AS_ASDO,
-- connection of cpld-fpga
fpga_write => fpga_write,
fpga_read => fpga_read,
fpga_as => fpga_as,
fpga_ad => fpga_ad,
fpga_drdy => fpga_drdy,
UserBlocks => UserBlocks);
spi_link_1: spi_link
port map (
clk => clk,
reset => reset,
SCK => SPI_SCK,
SDI => SPI_SI,
SDO => SPI_SO ,
SCS => spi_CS,
data_in => spi_data_in,
data_out => spi_data_out,
address_out => spi_address_out,
write_en => spi_write_en,
byte_sel => spi_byte_sel);
-----------------------------------------------------------------------------
-- I/O assignments:
-----------------------------------------------------------------------------
xbufoen(0) <= xbuf_O_en ;
xbufoen(1) <= xbuf_O_en ;
C_EXT(9 downto 2) <= (others => 'Z');
CPLD_STAT <= 'Z';
--reserved lines
-- CPLD_CLK <= 'Z'; -- 212MHz clock
--RSV3 <= 'Z';
CPU_INT <= 'Z';
--RVD1 <= 'Z';
--RVD0 <= 'Z';
--RVD11 <= 'Z';
--RVD13 <= 'Z';
--RVD12 <= 'Z';
PCI_CLK <= 'Z';
Main_CK_enable <= '1';
end V1;
trunk/VHDL/ADC_CPLD/ADC_CPLD_v0.98/vme_package.vhd 0 → 100644
View file @ f7ea7ecc
--***************************************************************************
-----------------------------------------------------------------------------
-------------- VmePackage.vhdl ----------------------------------------------
-----------------------------------------------------------------------------
--***************************************************************************
-----------------------------------------------------------------------------
--
------------------------------------------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vme is
------------------------
-- START VME INTERFACE
--
------------------------
-- selects the interrupt number the VME module
-- answer when VmeIackNA cycle is going on
subtype VmeAddressType is std_logic_vector(23 downto 1);
subtype VmeDataType is std_logic_vector(31 downto 0);
subtype ModuleAddrType is std_logic_vector(3 downto 0);
subtype ModuleAddrLType is std_logic_vector(23 downto 23 + ModuleAddrType'right - ModuleAddrType'left);
subtype SlaveAddrOutType is std_logic_vector(ModuleAddrLType'right - 1 downto 0);
subtype VmeAddresModType is std_logic_vector(5 downto 0);
subtype VmeIntLevelType is std_logic_vector(2 downto 0);
constant MODULE_ADDRESS_C : ModuleAddrLType := (23 => '1', 20 => '1', others => '0');
constant module_am : VmeAddresModType := "111001";
constant ZEROVMEADDRESS : VmeAddressType := (others => '0');
constant ONEVMEADDRESS : VmeAddressType := (ZEROVMEADDRESS'right => '1', others => '0');
constant STDNONPRIVPROGACC : VmeAddresModType := "111001";
type VmeCellType is
record
Address : VmeAddressType;
Data : VmeDataType;
Am : VmeAddresModType;
end record VmeCellType;
type VmeAddAmType is
record
Address : VmeAddressType;
Am : VmeAddresModType;
end record VmeAddAmType;
type IntAddDataType is
record
Address : integer;
Data : VmeDataType;
end record IntAddDataType;
type VmeBusOutRecord is
record
-- clk : std_logic;
VmeAddrA : VmeAddressType;
VmeAsNA : std_logic;
VmeAmA : VmeAddresModType;
VmeDs1NA : std_logic;
VmeDs0NA : std_logic;
VmeLwordNA: std_logic;
VmeWriteNA : std_logic;
VmeIackNA : std_logic;
IackInNA : std_logic;
-- ModuleAddr : std_logic_vector(4 downto 0);
-- DataFromMemValid : std_logic;
-- DataFromMem: VmeDataType;
-- data_writen_valid : std_logic;
-- ResetNA : std_logic;
-- UserIntReqN : std_logic;
-- UserBlocks : std_logic;
VmeData : VmeDataType;
writeFinished : boolean;
readFinished : boolean;
takeControl : boolean;
end record VmeBusOutRecord;
type VmeBusOutRecordArray is array (natural range <>) of VmeBusOutRecord;
type VmeBusInRecord is
record
VmeData : VmeDataType;
VmeDir : std_logic;
VmeBufOeN : std_logic;
IackOutNA: std_logic;
VmeAsNA : std_logic;
VmeIntReqN : std_logic_vector(7 downto 0);
dtack_n : std_logic;
end record VmeBusInRecord;
--type StdLogVecArray is array (natural range <>) of Std_logic_vector;
-- Interrupt vector to be put on data bus during
-- the VME interrupt cycle
function PullUpStdLogVec(input1, input2 : Std_logic_vector) return Std_logic_vector;
function PullUpStdLog(input1, input2 : Std_logic) return Std_logic ;
function PullUpVmeBusOut(inputs : VmeBusOutRecordArray) return VmeBusOutRecord;
--function PullUpStdLog (inputs : std_logic_vector) return
end;
package body vme is
function PullUpStdLogVec(input1, input2 : Std_logic_vector) return Std_logic_vector is
variable vStdLogVec : Std_logic_vector(31 downto 0);
begin
vStdLogVec := (others => 'U');
for M in input2'range loop
case input2(M) is
when 'U' |'X' | 'W' => if input1(M) = '0' or input1(M) = 'L' then
vStdLogVec(M) := '0';
end if;
-- when 'X' => vStdLog := 'U';
when '0' => vStdLogVec(M) := '0';
when '1' => vStdLogVec(M) := input1(M);
when 'Z' => vStdLogVec(M) := input1(M);
-- when 'W' => vStdLogVec(M) := 'U';
when 'L' => vStdLogVec(M) := '0';
when 'H' => vStdLogVec(M) := input1(M);
when others => null;
end case;
end loop;
return vStdLogVec(input2'range);
end;
function PullUpStdLog(input1, input2 : Std_logic) return Std_logic is
variable vStdLog : Std_logic;
begin
vStdLog := 'U';
case input2 is
when 'U' |'X' | 'W' => if input1 = '0' or input1 = 'L' then
vStdLog := '0';
end if;
-- when 'X' => vStdLog := 'U';
when '0' => vStdLog := '0';
when '1' => vStdLog := input1;
when 'Z' => vStdLog := input1;
-- when 'W' => vStdLog := 'U';
when 'L' => vStdLog := '0';
when 'H' => vStdLog := input1;
-- when '-' => vStdLog := 'U';
when others => null;
end case;
return vStdLog;
end;
function PullUpVmeBusOut(inputs : VmeBusOutRecordArray) return VmeBusOutRecord is
variable vVmeBusOut : VmeBusOutRecord;
begin
vVmeBusOut.VmeAddrA := (others => '1');
vVmeBusOut.VmeAsNA := '1';
vVmeBusOut.VmeAmA := (others => '1');
vVmeBusOut.VmeDs1NA := '1';
vVmeBusOut.VmeDs0NA := '1';
vVmeBusOut.VmeLwordNA:= '1';
vVmeBusOut.VmeWriteNA := '1';
vVmeBusOut.VmeIackNA := '1';
vVmeBusOut.IackInNA := '1';
vVmeBusOut.VmeData := (others => 'Z');
vVmeBusOut.writeFinished := false;
vVmeBusOut.readFinished := false;
for I in inputs'range loop
if inputs(I).takeControl then
vVmeBusOut.VmeAddrA := inputs(I).VmeAddrA;
vVmeBusOut.VmeAsNA := inputs(I).VmeAsNA ;
vVmeBusOut.VmeAmA := inputs(I).VmeAmA;
vVmeBusOut.VmeDs1NA := inputs(I).VmeDs1NA ;
vVmeBusOut.VmeDs0NA := inputs(I).VmeDs0NA ;
vVmeBusOut.VmeLwordNA:= inputs(I).VmeLwordNA;
vVmeBusOut.VmeWriteNA := inputs(I).VmeWriteNA ;
vVmeBusOut.VmeIackNA := inputs(I).VmeIackNA ;
vVmeBusOut.IackInNA := inputs(I).IackInNA ;
vVmeBusOut.VmeData := inputs(I).VmeData ;
vVmeBusOut.writeFinished := inputs(I).writeFinished;
vVmeBusOut.readFinished := inputs(I).readFinished;
end if;
end loop;
return vVmeBusOut;
end;
end;
trunk/VHDL/ADC_Card_FPGA/AD7656_readout.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
-- Created on Tue Aug 28 10:52:58 2007
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
--USE std.textio.all;
-- Entity Declaration
ENTITY AD7656_readout IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
BUSY : IN STD_LOGIC;
ADC_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
ARM : IN STD_LOGIC;
sampling_freq : IN STD_LOGIC_VECTOR(15 downto 0);
software_trigger : IN STD_LOGIC;
sampling_clk_source : IN STD_LOGIC;
trig_select : IN STD_LOGIC;
TRIG1 : IN STD_LOGIC;
TRIG2 : IN STD_LOGIC;
clk25 : IN STD_LOGIC;
sample_clk_ext : IN STD_LOGIC;
Single_Channel_Mode_Channel_number : IN STD_LOGIC_VECTOR(5 downto 0);
Single_Channel_Mode : IN STD_LOGIC;
num_of_measurements : IN STD_LOGIC_VECTOR(15 downto 0);
result_wr_en : OUT STD_LOGIC;
measurement_done : OUT STD_LOGIC;
ADC_CONVST_A : OUT STD_LOGIC;
ADC_CONVST_B : OUT STD_LOGIC;
ADC_CONVST_C : OUT STD_LOGIC;
ADC_CS : OUT STD_LOGIC;
ADC_RD : OUT STD_LOGIC;
BUF_CLK : OUT STD_LOGIC;
status : OUT STD_LOGIC_VECTOR(7 downto 0);
data_WR : OUT STD_LOGIC_VECTOR(15 downto 0);
BUF_SEL : OUT STD_LOGIC_VECTOR(2 downto 0);
ADC_OE : OUT STD_LOGIC;
ADC_RST : OUT STD_LOGIC;
sample_clk_out : OUT STD_LOGIC;
armed : OUT STD_LOGIC;
DPRAM_WR_ADDR : OUT STD_LOGIC_VECTOR(12 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END AD7656_readout;
-- Architecture Body
ARCHITECTURE AD7656_readout_architecture OF AD7656_readout IS
TYPE STATE_TYPE IS (
idle,
wait_trigger,
wait_sample_pulse1,
wait_sample_pulse2,
wait_sample_pulse3,
wait_sample_pulse4,
wait_sample_pulse5,
wait_convst,
wait_busy_1,
wait_busy_2,
wait_busy_3,
wait_busy_4,
read_ADCsl_1,
read_ADCsl_2,
read_ADCsh,
scan_outputs,
conversion_done,
meas_done
);
SIGNAL state: STATE_TYPE;
signal ADC_count, Channel_count : std_logic_vector(2 downto 0);
signal ADC_number : STD_LOGIC_VECTOR(7 downto 0);
signal Acq36_cnt : STD_LOGIC_VECTOR(12 downto 0);
signal ADC_CHANNEL, ADC_CHANNEL_tmp : STD_LOGIC_VECTOR(5 downto 0);
signal edge_regi,edge_rege : STD_LOGIC_VECTOR(3 downto 0);
signal data_WR1,timer,addr_cnt: STD_LOGIC_VECTOR(15 downto 0);
signal addr_36ch_dpram : STD_LOGIC_VECTOR(12 downto 0);
signal measurements_counter : STD_LOGIC_VECTOR(15 downto 0);
signal ADC_count_en,Channel_count_en,
str_temp,
CS_temp,
RD_temp,
ADC_RST_temp,
latch_adc_result,
ADC_sample,
result_wr_en_temp,
result_wr_en_temp1,
OE_temp,
ADC_count_rst,
timer_init,
Channel_count_rst,
sample_clk_int,
sample,
BUSY_SYNCH,
trigger,
meas_num_rst,
meas_num_count_en,
meas_num_done,
trigger_ext,
trigger_int,
addr_cnt_rst,
addr_cnt_en,
addr_cnt_en_temp,
Acq36_cnt_en,
reset_capt_logic : std_logic ;
BEGIN
--***********************************************************************************************************************************************
--******************************************* data transfer state machine *********************************************************************
--***********************************************************************************************************************************************
--STATE MACHINE INPUT SYNCHRONISATION
process(clk)
begin
if clk'event and clk='0' then
BUSY_SYNCH<= BUSY;
end if;
end process;
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
state <= idle;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle =>
if ARM = '1' then
state <=wait_trigger;
end if;
when wait_trigger =>
if trigger = '1' then
state <=wait_Sample_pulse1;
elsif ARM = '0' then
state <= idle;
end if;
when wait_Sample_pulse1 =>
if sample = '1' then
state <=wait_Sample_pulse2;
end if;
when wait_Sample_pulse2 =>
state <= wait_Sample_pulse3;
when wait_Sample_pulse3 =>
state <= wait_Sample_pulse4;
when wait_Sample_pulse4 =>
state <= wait_Sample_pulse5;
when wait_Sample_pulse5 =>
state <= wait_busy_1;
when wait_convst =>
if sample = '1' then
state <=wait_busy_1;
end if;
when wait_busy_1 =>
state <= wait_busy_2;
when wait_busy_2 =>
state <= wait_busy_3;
when wait_busy_3 =>
state <= wait_busy_4;
when wait_busy_4 =>
if BUSY_SYNCH = '0' then
state <=read_ADCsl_1;
elsif ARM = '0' then
state <= idle;
end if;
when read_ADCsl_1 =>
state<=read_ADCsl_2;
when read_ADCsl_2 =>
state<=read_ADCsh;
when read_ADCsh =>
state<=scan_outputs;
when scan_outputs =>
if Channel_count = "110" and ADC_count = "110" then
state <= conversion_done;
elsif ADC_count = "110" then
state<=read_ADCsl_1;
elsif ARM = '0' then
state <= idle;
end if;
when conversion_done =>
if meas_num_done = '1' then
state <= meas_done;
elsif sample = '0' and ARM = '1' then
state <=wait_convst;
elsif ARM = '0' then
state <= idle;
end if;
when meas_done =>
if arm = '0' then
state <= idle;
end if;
when others =>
state<=idle;
END CASE;
end if;
END PROCESS;
WITH state SELECT
ADC_count_en <= '0' when idle,
'1' when scan_outputs,
'0' when others;
WITH state SELECT
ADC_RST_temp <= '1' when idle,
'0' when others;
WITH state SELECT
Channel_count_en <= '0' when idle,
'1' when read_ADCsl_1,
'0' when others;
WITH state SELECT
CS_temp <= '1' when idle,
'1' when wait_trigger,
'1' when wait_Sample_pulse1,
'1' when wait_Sample_pulse2,
'1' when wait_Sample_pulse3,
'1' when wait_Sample_pulse4,
'1' when wait_Sample_pulse5,
'1' when wait_convst,
'0' when read_ADCsl_1,
'0' when read_ADCsl_2,
'0' when read_ADCsh,
'0' when scan_outputs,
'1' when conversion_done,
'1' when others;
WITH state SELECT
RD_temp <= '1' when idle,
'0' when read_ADCsl_1,
'0' when read_ADCsl_2,
'1' when others;
WITH state SELECT
buf_clk <= '1' when idle, --clk when scan_outputs,
'1' when conversion_done,
'1' when others;
WITH state SELECT
measurement_done <= '0' when idle,
'1' when meas_done,
'0' when others;
WITH state SELECT
Acq36_cnt_en <= '0' when idle,
'1' when conversion_done,
'0' when others;
WITH state SELECT
result_wr_en_temp1 <= '0' when idle,
'1' when scan_outputs,
'0' when others;
WITH state SELECT
latch_adc_result <= '0' when idle,
'1' when scan_outputs,
'0' when others;
WITH state SELECT
ADC_sample <= '1' when idle,
'1' when wait_trigger,
'0' when wait_convst,
'0' when wait_Sample_pulse1,
'0' when wait_Sample_pulse2,
'0' when wait_Sample_pulse3,
'0' when wait_Sample_pulse4,
'0' when wait_Sample_pulse5,
'1' when wait_busy_1,
'1' when wait_busy_2,
'1' when wait_busy_3,
'1' when wait_busy_4,
'1' when read_ADCsl_1,
'1' when read_ADCsl_2,
'1' when read_ADCsh,
'1' when scan_outputs,
'1' when conversion_done,
'1' when meas_done,
'0' when others;
WITH state SELECT
OE_temp <= '1' when idle,
'0' when read_ADCsl_1,
'0' when read_ADCsl_2,
'0' when read_ADCsh,
'0' when scan_outputs,
'1' when conversion_done,
'1' when others;
WITH state SELECT
ADC_count_rst <= '0' when idle,
'1' when read_ADCsh,
'0' when scan_outputs,
'0' when conversion_done,
'0' when others;
WITH state SELECT
timer_init <= '1' when idle, -- TO GET RID OF "1" ON adc SAMPLE INPUTS
'1' when wait_trigger,
'0' when others;
WITH state SELECT
addr_cnt_rst <= '1' when idle,
'0' when read_ADCsh,
'0' when scan_outputs,
'0' when conversion_done,
'0' when others;
WITH state SELECT
Channel_count_rst <= '1' when idle,
'1' when wait_convst,
'1' when wait_busy_3,
'0' when others;
with state select
armed <= '0' when idle,
'1' when wait_trigger,
'0' when conversion_done,
'1' when others;
with state select
meas_num_rst <= '1' when idle,
'1' when wait_trigger,
'0' when others;
with state select
meas_num_count_en <= '0' when idle,
'1' when conversion_done,
'0' when others;
ADC_CONVST_A <= ADC_sample; --or sample;
ADC_CONVST_B <= ADC_sample; --or sample;
ADC_CONVST_C <= ADC_sample; --or sample;
--generation of glitch-free signals
process(clk,reset)
begin
if clk'event and clk='0' then
ADC_CS <= CS_temp;
ADC_RD <= RD_temp;
BUF_SEL <= ADC_count;
ADC_OE <=OE_temp;
ADC_RST <= ADC_RST_temp;
end if;
end process;
--ADC_RST <= reset;
addr_cnt_en_temp <= result_wr_en_temp when (Single_Channel_Mode = '0'and result_wr_en_temp1 = '1') else
result_wr_en_temp when (Single_Channel_Mode_Channel_number = ADC_CHANNEL) and Single_Channel_Mode = '1'
else '0' ;
-- delay address count and wrte strobe by 1 clk cycle
process(clk,reset)
begin
if clk'event and clk='1' then
addr_cnt_en <= addr_cnt_en_temp;
result_wr_en_temp<= result_wr_en_temp1;
result_wr_en <= addr_cnt_en_temp;
end if;
end process;
process(clk,reset)
begin
if clk'event and clk='1' then
if addr_cnt_rst = '1' then
addr_cnt <= (others => '0');
elsif addr_cnt_en = '1' then
addr_cnt<=addr_cnt + '1';
end if;
end if;
end process;
--for 36 channel operation, do the channel sorting and proper layout in the memory.
--delay address by one clock cycle to align it with ADC data correctly
process(clk,reset)
begin
if clk'event and clk='1' then
addr_36ch_dpram <= Acq36_cnt + ADC_CHANNEL;
end if;
end process;
DPRAM_WR_ADDR <= addr_cnt(12 downto 0) when Single_Channel_Mode = '1' else addr_36ch_dpram;
process(clk,reset)
begin
if clk'event and clk='1' then
if meas_num_rst = '1' then
measurements_counter <= (others => '0');
meas_num_done <= '0';
elsif meas_num_count_en = '1' and meas_num_done = '0' then
measurements_counter<=measurements_counter + '1';
end if;
if measurements_counter = (num_of_measurements - '1') then
--DEBUG
--
meas_num_done <= '1';
--
--
end if;
end if;
end process;
-- data set counter, counts number of 36-channel acqusitions
process(clk,addr_cnt_rst)
begin
if clk'event and clk='1' then
if addr_cnt_rst = '1' then
Acq36_cnt <= (others => '0');
elsif Acq36_cnt_en = '1' then
Acq36_cnt <=Acq36_cnt+ std_logic_vector(to_signed(36,8));
end if;
end if;
end process;
-- currently read ADC counter
process(clk,reset)
begin
if clk'event and clk='1' then
if ADC_count_rst = '1' then
ADC_count <= (others => '0');
elsif ADC_count_en='1' then
ADC_count <=ADC_count+'1';
end if;
end if;
end process;
--currently read ADC channel
process(clk,reset)
begin
if clk'event and clk='1' then
if Channel_count_rst = '1' then
Channel_count <= (others => '0');
elsif Channel_count_en='1' then
Channel_count <=Channel_count+'1';
end if;
end if;
end process;
--currently read ADC channel
process(clk,reset)
begin
if clk'event and clk='0' then
data_WR1 <= ADC_DATA;
end if;
end process;
process(clk,reset)
begin
if clk'event and clk='1' then
if latch_adc_result = '1' then
-- data_WR1 <= "000" & addr_cnt(12 downto 0);
data_WR <= data_WR1;
end if;
end if;
end process;
--***************************************************************************************************
--*************************************** ADC sorting look-up-table *******************************
--***************************************************************************************************
--subtract 1 since both counters cout from 1 to 6
ADC_number <= '0' & (Channel_count - '1') & '0' & (ADC_count - std_logic_vector(to_signed(1,3)));
ADC_CH_SORT: with ADC_number select
ADC_CHANNEL <= std_logic_vector(to_signed(35,6)) when x"00",
std_logic_vector(to_signed(23,6)) when x"01",
std_logic_vector(to_signed(2,6)) when x"02",
std_logic_vector(to_signed(5,6)) when x"03",
std_logic_vector(to_signed(20,6)) when x"04",
std_logic_vector(to_signed(17,6)) when x"05",
std_logic_vector(to_signed(34,6)) when x"10",
std_logic_vector(to_signed(31,6)) when x"11",
std_logic_vector(to_signed(10,6)) when x"12",
std_logic_vector(to_signed(13,6)) when x"13",
std_logic_vector(to_signed(28,6)) when x"14",
std_logic_vector(to_signed(25,6)) when x"15",
std_logic_vector(to_signed(33,6)) when x"20",
std_logic_vector(to_signed(0,6)) when x"21",
std_logic_vector(to_signed(3,6)) when x"22",
std_logic_vector(to_signed(6,6)) when x"23",
std_logic_vector(to_signed(21,6)) when x"24",
std_logic_vector(to_signed(18,6)) when x"25",
std_logic_vector(to_signed(32,6)) when x"30",
std_logic_vector(to_signed(8,6)) when x"31",
std_logic_vector(to_signed(11,6)) when x"32",
std_logic_vector(to_signed(14,6)) when x"33",
std_logic_vector(to_signed(29,6)) when x"34",
std_logic_vector(to_signed(26,6)) when x"35",
std_logic_vector(to_signed(16,6)) when x"40",
std_logic_vector(to_signed(1,6)) when x"41",
std_logic_vector(to_signed(4,6)) when x"42",
std_logic_vector(to_signed(7,6)) when x"43",
std_logic_vector(to_signed(22,6)) when x"44",
std_logic_vector(to_signed(19,6)) when x"45",
std_logic_vector(to_signed(24,6)) when x"50",
std_logic_vector(to_signed(9,6)) when x"51",
std_logic_vector(to_signed(12,6)) when x"52",
std_logic_vector(to_signed(15,6)) when x"53",
std_logic_vector(to_signed(30,6)) when x"54",
std_logic_vector(to_signed(27,6)) when x"55",
std_logic_vector(to_signed(36,6)) when others; -- write nowhere - this position will be overwritten anyway and should never happen1
--***************************************************************************************************
--*************************************** trigger edge detection *******************************
--***************************************************************************************************
edge_rege(0)<= TRIG1 when trig_select = '0' else TRIG2 ;
edge_regi(0) <= software_trigger;
process (clk)
begin
if rising_edge(clk) then
--ext trigger
edge_rege(1)<=edge_rege(0);
edge_rege(2)<=edge_rege(1);
edge_rege(3)<=edge_rege(2);
--int software trigger
edge_regi(1)<=edge_regi(0);
edge_regi(2)<=edge_regi(1);
edge_regi(3)<=edge_regi(2);
end if;
end process;
trigger_ext <= (not edge_rege(3)) and (not edge_rege(2)) and edge_rege(1)and edge_rege(0) ;
trigger_int <= (not edge_regi(3)) and (not edge_regi(2)) and edge_regi(1)and edge_regi(0) ;
trigger <= trigger_int or trigger_ext;
--*************************************************************************************************************
--sample clock generator
--*************************************************************************************************************
process (clk25, reset)
begin -- process count
if reset = '1' or timer_init = '1' then -- asynchronous reset (active high)
timer <= x"0001"; -- set the timer to 1 in order to generate mesurmeent one cycle after trigger
sample_clk_int <= '0';
elsif clk25'event and clk25 = '1' then -- rising clock edge
timer <= timer - '1'; -- decrease counts
if timer = x"0000" then
timer <= sampling_freq;
sample_clk_int <= '1';
else
sample_clk_int <= '0';
end if;
end if;
end process count;
sample <= sample_clk_ext when sampling_clk_source = '1' else sample_clk_int;
sample_clk_out <= sample;
END AD7656_readout_architecture;
trunk/VHDL/ADC_Card_FPGA/ADC_CARD.qsf 0 → 100644
View file @ f7ea7ecc
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# ADC_CARD_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name DEVICE EP2C8Q208C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY ADC_CARD
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:12:01 JANUARY 25, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name VHDL_FILE AD7656_readout.vhd
set_global_assignment -name BDF_FILE ADC_CARD.bdf
set_global_assignment -name SOURCE_FILE altpll0.cmp
set_global_assignment -name VHDL_FILE altpll0.vhd
set_global_assignment -name VHDL_FILE analyser.vhd
set_global_assignment -name SOURCE_FILE clk_pll.cmp
set_global_assignment -name VHDL_FILE clk_pll.vhd
set_global_assignment -name VHDL_FILE clkdivider.vhd
set_global_assignment -name SOURCE_FILE DPRAM.cmp
set_global_assignment -name VHDL_FILE DPRAM.vhd
set_global_assignment -name SOURCE_FILE dpram_32x32.cmp
set_global_assignment -name VHDL_FILE dpram_32x32.vhd
set_global_assignment -name VHDL_FILE hct4094.vhd
set_global_assignment -name VHDL_FILE indicators.vhd
set_global_assignment -name SOURCE_FILE lpm_or0.cmp
set_global_assignment -name VHDL_FILE lpm_or0.vhd
set_global_assignment -name VHDL_FILE onchip_mem.vhd
set_global_assignment -name VHDL_FILE PCI_SLAVE.vhd
set_global_assignment -name VHDL_FILE REGISTERS.vhd
set_global_assignment -name VHDL_FILE sdram.vhd
set_global_assignment -name SOURCE_FILE SPRAM1kx32.cmp
set_global_assignment -name VHDL_FILE SPRAM1kx32.vhd
set_global_assignment -name VHDL_FILE types.vhd
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_location_assignment PIN_3 -to PCI_AD[15]
set_location_assignment PIN_207 -to RESET
set_location_assignment PIN_208 -to PCI_AD[12]
set_location_assignment PIN_206 -to PCI_BEn[0]
set_location_assignment PIN_203 -to PCI_BEn[1]
set_location_assignment PIN_4 -to PCI_AD[14]
set_location_assignment PIN_5 -to PCI_AD[13]
set_location_assignment PIN_6 -to PCI_AD[11]
set_location_assignment PIN_8 -to PCI_AD[10]
set_location_assignment PIN_10 -to PCI_AD[9]
set_location_assignment PIN_11 -to PCI_AD[8]
set_location_assignment PIN_12 -to PCI_AD[7]
set_location_assignment PIN_13 -to PCI_AD[6]
set_location_assignment PIN_14 -to PCI_AD[5]
set_location_assignment PIN_15 -to PCI_AD[4]
set_location_assignment PIN_30 -to PCI_AD[3]
set_location_assignment PIN_31 -to PCI_AD[2]
set_location_assignment PIN_33 -to PCI_AD[1]
set_location_assignment PIN_34 -to PCI_AD[0]
set_location_assignment PIN_37 -to PCI_IRDYn
set_location_assignment PIN_39 -to PCI_TRDYn
set_location_assignment PIN_41 -to PCI_INTn
set_location_assignment PIN_43 -to PCI_FRAMEn
set_location_assignment PIN_46 -to RXD
set_location_assignment PIN_45 -to TXD
set_location_assignment PIN_44 -to XCK
set_location_assignment PIN_47 -to SDA
set_location_assignment PIN_48 -to SCL
set_location_assignment PIN_82 -to SDRAM_WEn
set_location_assignment PIN_80 -to SDRAM_RASn
set_location_assignment PIN_77 -to SDRAM_CSn
set_location_assignment PIN_63 -to SDRAM_A[11]
set_location_assignment PIN_76 -to SDRAM_BA[0]
set_location_assignment PIN_75 -to SDRAM_BA[1]
set_location_assignment PIN_74 -to SDRAM_A[10]
set_location_assignment PIN_72 -to SDRAM_A[0]
set_location_assignment PIN_70 -to SDRAM_A[1]
set_location_assignment PIN_69 -to SDRAM_A[2]
set_location_assignment PIN_68 -to SDRAM_A[3]
set_location_assignment PIN_56 -to SDRAM_A[4]
set_location_assignment PIN_57 -to SDRAM_A[5]
set_location_assignment PIN_58 -to SDRAM_A[6]
set_location_assignment PIN_59 -to SDRAM_A[7]
set_location_assignment PIN_60 -to SDRAM_A[8]
set_location_assignment PIN_61 -to SDRAM_A[9]
set_location_assignment PIN_67 -to SDRAM_CLK
set_location_assignment PIN_143 -to LED_STR
set_location_assignment PIN_141 -to LED_CLK
set_location_assignment PIN_142 -to LED_DAT
set_location_assignment PIN_150 -to TRIG_in1
set_location_assignment PIN_96 -to SDRAM_DQM[1]
set_location_assignment PIN_118 -to SDRAM_DQM[3]
set_location_assignment PIN_117 -to SDRAM_DQM[2]
set_location_assignment PIN_84 -to SDRAM_DQM[0]
set_location_assignment PIN_95 -to SDRAM_D[0]
set_location_assignment PIN_94 -to SDRAM_D[1]
set_location_assignment PIN_92 -to SDRAM_D[2]
set_location_assignment PIN_90 -to SDRAM_D[3]
set_location_assignment PIN_89 -to SDRAM_D[4]
set_location_assignment PIN_88 -to SDRAM_D[5]
set_location_assignment PIN_87 -to SDRAM_D[6]
set_location_assignment PIN_86 -to SDRAM_D[7]
set_location_assignment PIN_97 -to SDRAM_D[8]
set_location_assignment PIN_99 -to SDRAM_D[9]
set_location_assignment PIN_101 -to SDRAM_D[10]
set_location_assignment PIN_105 -to SDRAM_D[15]
set_location_assignment PIN_106 -to SDRAM_D[14]
set_location_assignment PIN_104 -to SDRAM_D[13]
set_location_assignment PIN_103 -to SDRAM_D[12]
set_location_assignment PIN_102 -to SDRAM_D[11]
set_location_assignment PIN_107 -to SDRAM_D[16]
set_location_assignment PIN_108 -to SDRAM_D[17]
set_location_assignment PIN_110 -to SDRAM_D[18]
set_location_assignment PIN_112 -to SDRAM_D[19]
set_location_assignment PIN_113 -to SDRAM_D[20]
set_location_assignment PIN_114 -to SDRAM_D[21]
set_location_assignment PIN_115 -to SDRAM_D[22]
set_location_assignment PIN_116 -to SDRAM_D[23]
set_location_assignment PIN_127 -to SDRAM_D[24]
set_location_assignment PIN_128 -to SDRAM_D[25]
set_location_assignment PIN_139 -to SDRAM_D[31]
set_location_assignment PIN_138 -to SDRAM_D[30]
set_location_assignment PIN_135 -to SDRAM_D[28]
set_location_assignment PIN_134 -to SDRAM_D[27]
set_location_assignment PIN_133 -to SDRAM_D[26]
set_location_assignment PIN_137 -to SDRAM_D[29]
set_location_assignment PIN_23 -to CLK50
set_location_assignment PIN_81 -to SDRAM_CASn
set_location_assignment PIN_145 -to RS485_TXEN
set_location_assignment PIN_40 -to PCI_RESET
set_location_assignment PIN_199 -to ADC_DATA[15]
set_location_assignment PIN_198 -to ADC_DATA[14]
set_location_assignment PIN_197 -to ADC_DATA[13]
set_location_assignment PIN_195 -to ADC_DATA[12]
set_location_assignment PIN_193 -to ADC_DATA[11]
set_location_assignment PIN_192 -to ADC_DATA[10]
set_location_assignment PIN_191 -to ADC_DATA[9]
set_location_assignment PIN_189 -to ADC_DATA[8]
set_location_assignment PIN_188 -to ADC_DATA[7]
set_location_assignment PIN_187 -to ADC_DATA[6]
set_location_assignment PIN_185 -to ADC_DATA[5]
set_location_assignment PIN_182 -to ADC_DATA[4]
set_location_assignment PIN_181 -to ADC_DATA[3]
set_location_assignment PIN_180 -to ADC_DATA[2]
set_location_assignment PIN_179 -to ADC_DATA[1]
set_location_assignment PIN_176 -to ADC_DATA[0]
set_location_assignment PIN_175 -to ADC_SEL[0]
set_location_assignment PIN_173 -to ADC_SEL[1]
set_location_assignment PIN_171 -to ADC_SEL[2]
set_location_assignment PIN_170 -to ADC_OE
set_location_assignment PIN_169 -to BUF_CLK
set_location_assignment PIN_168 -to ADC_RD
set_location_assignment PIN_165 -to CONVST_C
set_location_assignment PIN_164 -to CONVST_B
set_location_assignment PIN_163 -to CONVST_A
set_location_assignment PIN_162 -to ADC_RST
set_location_assignment PIN_161 -to dig_IO2
set_location_assignment PIN_160 -to dig_IO1
set_location_assignment PIN_200 -to BUSY
set_location_assignment PIN_152 -to SAMPLE_CLK
set_location_assignment PIN_151 -to TRIG_in2
set_location_assignment PIN_149 -to RS232_RXD
set_location_assignment PIN_147 -to RS232_TXD
set_location_assignment PIN_146 -to RS485_RX
set_location_assignment PIN_144 -to RS485_TX
set_location_assignment PIN_64 -to SDRAM_A[12]
set_location_assignment PIN_130 -to CLK_50
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name SIGNALTAP_FILE ADC.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE io.stp
set_global_assignment -name FMAX_REQUIREMENT "25 MHz"
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clk
set_instance_assignment -name CLOCK_SETTINGS clk -to CLK50
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name SIGNALTAP_FILE PCI.stp
set_global_assignment -name SIGNALTAP_FILE CPLD.stp
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name SIGNALTAP_FILE basic.stp
set_global_assignment -name SIGNALTAP_FILE ADC_sampler.stp
set_global_assignment -name SIGNALTAP_FILE adc_precise_timings.stp
set_global_assignment -name TEXT_FILE adc_sort_table.txt
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name SIGNALTAP_FILE io.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLK50 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to SAMPLE_CLK -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to TRIG_in1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to TRIG_in2 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to SAMPLE_CLK -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to TRIG_in1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to TRIG_in2 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=3" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=3" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=33" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=12772" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=38782" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
\ No newline at end of file
trunk/VHDL/ADC_Card_FPGA/DPRAM.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: DPRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY DPRAM IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END DPRAM;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 8192,
numwords_b => 4096,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 13,
widthad_b => 12,
width_a => 16,
width_b => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL rdaddress[11..0]
-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL wraddress[12..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
-- Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
trunk/VHDL/ADC_Card_FPGA/PCI_SLAVE.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sat Nov 13 01:28:56 2004
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all ;
USE ieee.numeric_std.ALL;
-- Entity Declaration
ENTITY PCI_SLAVE IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
( --global clk and reset
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
-- RW register access port
REGS_RW_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
REGS_RW_DAT_WRITE : OUT STD_LOGIC_VECTOR(31 downto 0);
REGS_RW_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
REGS_RW_WREN : OUT STD_LOGIC;
--read only register access port
REGS_R_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
REGS_R_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
-- dual port read-write ram acess
DPRAM0_RW_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM0_RW_DAT_WRITE : OUT STD_LOGIC_VECTOR(31 downto 0);
DPRAM0_RW_ADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
DPRAM0_RW_WREN : OUT STD_LOGIC;
-- dual port result ram acess
DPRAM1_R_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM1_R_ADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
-- analyser DPRAM2 access
DPRAM2_R_DATA : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM2_R_ADDR : OUT STD_LOGIC_VECTOR(10 downto 0);
-- analyser DPRAM3 access
DPRAM3_R_DATA : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM3_R_ADDR : OUT STD_LOGIC_VECTOR(10 downto 0);
DPRAM_ADDR_RST : IN STD_LOGIC;
--PCI-like lines
PCI_FRAMEn : IN STD_LOGIC;
PCI_BEn : IN STD_LOGIC_VECTOR(1 downto 0);
PCI_IRDYn : IN STD_LOGIC;
PCI_TRDYn : buffer STD_LOGIC;
PCI_INTn : OUT STD_LOGIC;
PCI_AD : INOUT STD_LOGIC_VECTOR(15 downto 0);
--interrupt in
INT_IN : IN STD_LOGIC;
--test lines
TEST1 : OUT STD_LOGIC_VECTOR(31 downto 0);
TEST2 : OUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END PCI_SLAVE;
-- Architecture Body
ARCHITECTURE PCI_SLAVE_architecture OF PCI_SLAVE IS
TYPE STATE_TYPE IS (
IDLE,
write_dat_MSB,
write_dat_LSB,
deselect,
set_trdy,
read_dat_MSB,
read_dat_LSB
);
SIGNAL state: STATE_TYPE;
SIGNAL count_enable,
count_enable_main,
header_end,
latch_base_address,
load_counter,
force_count,
latch_MSB,
dpram_count_enable : std_logic;
signal regs_rw_sel,
regs_r_sel,
dpram0_sel,
dpram1_sel,
dpram2_sel,
dpram3_sel,
write_en : std_logic;
signal dpram_addr_count : std_logic_vector(10 downto 0);
signal addr_count : std_logic_vector(15 downto 0);
signal mem_sel : std_logic_vector(1 downto 0);
signal base_ad : std_logic_vector(15 downto 0);
signal dat_MSB : std_logic_vector(15 downto 0);
signal mem_data_wr, mem_data_rd : std_logic_vector(31 downto 0);
BEGIN
---***********************************************************************************************************************************************
---*********************************************** PCI SLAVE state machine ********************************************************
---***********************************************************************************************************************************************
PROCESS (clk,reset)
BEGIN
if reset='1'then
state<=IDLE;
elsif clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN IDLE =>
if PCI_FRAMEn = '0' and PCI_BEn = "11" then
state <= write_dat_MSB;
elsif PCI_FRAMEn = '0' and PCI_BEn = "01" then
state <= set_trdy;
else
state <= IDLE;
end if;
WHEN write_dat_MSB =>
if PCI_FRAMEn = '1' then
state <= deselect;
elsif PCI_IRDYn = '0' and PCI_BEn(1) = '0' then
state <= write_dat_LSB;
end if;
WHEN write_dat_LSB =>
if PCI_FRAMEn = '1' then
state <= deselect;
elsif PCI_IRDYn = '0' and PCI_BEn(0) = '0' then
state <= write_dat_MSB;
end if;
WHEN deselect =>
state <= IDLE;
WHEN set_trdy =>
if PCI_FRAMEn = '1' then
state <= deselect;
elsif PCI_IRDYn = '0' and PCI_BEn(1) = '0' then
state <= read_dat_MSB;
end if;
WHEN read_dat_MSB =>
if PCI_FRAMEn = '1' then
state <= deselect;
elsif PCI_IRDYn = '0' then
state <= read_dat_LSB;
end if;
WHEN read_dat_LSB =>
if PCI_FRAMEn = '1' then
state <= deselect;
else
state <= set_trdy;
end if;
WHEN others =>
state <= IDLE;
END CASE;
END IF;
END PROCESS;
---***********************************************************************************************************************************************
---***********************************************************************************************************************************************
----------- state machine output signals assignments
---***********************************************************************************************************************************************
---***********************************************************************************************************************************************
WITH state SELECT
PCI_TRDYn <= '1' when IDLE,
'0' when write_dat_MSB,
'0' when write_dat_LSB,
'1' when deselect,
'1' when set_trdy,
'0' when read_dat_MSB,
'0' when read_dat_LSB,
'1' when others;
WITH state SELECT
PCI_AD <= mem_data_rd(15 downto 0) when read_dat_LSB,
mem_data_rd(31 downto 16) when read_dat_MSB,
(others => 'Z') when others;
with state select
count_enable_main <= '0' when IDLE,
'0' when write_dat_MSB,
'1' when write_dat_LSB,
'0' when deselect,
'0' when set_trdy,
'0' when read_dat_MSB,
'1' when read_dat_LSB,
'0' when others;
with state select
load_counter <= '1' when IDLE,
'0' when others;
with state select
latch_base_address <= '1' when IDLE,
'0' when others;
with state select
write_en <= '1' when write_dat_LSB,
'0' when others;
---***********************************************************************************************************************************************
----------- address counter
---***********************************************************************************************************************************************
count_enable <= count_enable_main and (not PCI_TRDYn) and (not PCI_IRDYn) and (not PCI_BEn(0));
process(clk,reset)
begin
if reset = '1' then
addr_count <= (others => '0');
elsif clk'event and clk = '1' then
if load_counter = '1' then
addr_count(15 downto 0) <= PCI_AD(15 downto 0);
elsif count_enable = '1' then
addr_count <= addr_count+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if latch_base_address = '1' then
base_ad(15 downto 0) <= PCI_AD(15 downto 0);
end if;
end if;
end process;
---***********************************************************************************************************************************************
----------- analyser DPRAM address coutner
---***********************************************************************************************************************************************
dpram_count_enable <= count_enable_main and (not PCI_TRDYn) and (not PCI_IRDYn) and (not PCI_BEn(0)) and ( dpram2_sel or dpram3_sel);
process(clk,reset,DPRAM_ADDR_RST)
begin
if reset = '1' or DPRAM_ADDR_RST = '1' then
dpram_addr_count <= (others => '0');
elsif clk'event and clk = '1' then
if dpram_count_enable = '1' then
dpram_addr_count <= dpram_addr_count+1;
end if;
end if;
end process;
---***********************************************************************************************************************************************
----- memory select address decoder
---***********************************************************************************************************************************************
-- number of 32 bit location!!! --ADDRESS
regs_rw_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(0,9)) else '0'; --0x0000 --0x0000
regs_r_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(1,9)) else '0'; --0x0080 --0x0200
dpram0_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(2,9)) else '0'; --0x0100 --0x0400
dpram1_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(3,9)) else '0'; --0x0180 --0x0600
dpram2_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(4,9)) else '0'; --0x0200 --0x0800
dpram3_sel <= '1' when base_ad(15 downto 7) = std_logic_vector(to_unsigned(5,9)) else '0'; --0x0280 --0x0A00
---***********************************************************************************************************************************************
----------- RAM write enables generation
---***********************************************************************************************************************************************
REGS_RW_WREN <= regs_rw_sel and (not PCI_TRDYn) and (not PCI_IRDYn) and write_en;
DPRAM0_RW_WREN <= dpram0_sel and (not PCI_TRDYn) and (not PCI_IRDYn) and write_en;
---***********************************************************************************************************************************************
----------- RAM address generation
---***********************************************************************************************************************************************
REGS_RW_ADDR <= addr_count(4 downto 0);
REGS_R_ADDR <= addr_count(4 downto 0);
DPRAM0_RW_ADDR <= addr_count(6 downto 0);
DPRAM1_R_ADDR <= addr_count(6 downto 0);
DPRAM2_R_ADDR <= dpram_addr_count;
DPRAM3_R_ADDR <= dpram_addr_count;
---***********************************************************************************************************************************************
----------- RAM data assignment
---***********************************************************************************************************************************************
latch_MSB <= '1' when PCI_IRDYn = '0' and PCI_TRDYn = '0' and state = write_dat_MSB else '0' ;
--latches MSB of PCI transfer to form 32 bit memory word
process(clk)
begin
if clk'event and clk = '1' then
if latch_MSB = '1' then
dat_MSB(15 downto 0) <= PCI_AD(15 downto 0);
end if;
end if;
end process;
mem_data_wr<= dat_MSB & PCI_AD; -- compose final memory data
REGS_RW_DAT_WRITE <= mem_data_wr;
DPRAM0_RW_DAT_WRITE <= mem_data_wr;
---***********************************************************************************************************************************************
----------- RAM data out assignment
---***********************************************************************************************************************************************
mem_data_rd <= REGS_RW_DAT_READ when regs_rw_sel = '1' else
REGS_R_DAT_READ when regs_r_sel = '1' else
DPRAM0_RW_DAT_READ when dpram0_sel = '1' else
DPRAM1_R_DAT_READ when dpram1_sel = '1' else
DPRAM2_R_DATA when dpram2_sel = '1' else
DPRAM3_R_DATA when dpram3_sel = '1' else
x"00000000" ;
PCI_INTn <= not INT_IN;
TEST1(7 downto 0) <= latch_MSB & write_en & addr_count(5 downto 0);
TEST1(31 downto 8) <= (others => '0');
TEST2 <= mem_data_wr;
END PCI_SLAVE_architecture;
trunk/VHDL/ADC_Card_FPGA/REGISTERS.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
-- Created on Wed Sep 22 10:39:11 2004
LIBRARY IEEE ;
LIBRARY lpm ;
USE IEEE.std_logic_1164.all ;
USE IEEE.numeric_std.all;
USE lpm.lpm_components.ALL;
use ieee.std_logic_unsigned.all;
use work.types.all;
-- Entity Declaration
ENTITY REGISTERS IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK : IN STD_LOGIC;
reset : IN STD_LOGIC;
status : IN STD_LOGIC_VECTOR(7 downto 0);
PCI_BEn : IN STD_LOGIC_VECTOR(1 downto 0);
PCI_FRAMEn : IN STD_LOGIC;
PCI_IRDYn : IN STD_LOGIC;
PCI_CLK : IN STD_LOGIC;
PCI_RESET : IN STD_LOGIC;
DPRAM_D : IN STD_LOGIC_VECTOR(31 downto 0);
measurement_done : IN STD_LOGIC;
armed : IN STD_LOGIC;
sample : IN STD_LOGIC;
EXT_out : OUT STD_LOGIC_VECTOR(15 downto 1);
STAT_LED : OUT STD_LOGIC_VECTOR(7 downto 0);
PCI_TRDYn : OUT STD_LOGIC;
PCI_INTn : OUT STD_LOGIC;
pci_test : OUT STD_LOGIC_VECTOR(7 downto 0);
sampling_freq : OUT STD_LOGIC_VECTOR(15 downto 0);
ARM : OUT STD_LOGIC;
software_trigger : OUT STD_LOGIC;
sampling_clk_source : OUT STD_LOGIC;
trig_select : OUT STD_LOGIC;
Single_Channel_Mode_Channel_number : OUT STD_LOGIC_VECTOR(5 downto 0);
Single_Channel_Mode : OUT STD_LOGIC;
DPRAM_A : OUT STD_LOGIC_VECTOR(11 downto 0);
num_of_measurements : OUT STD_LOGIC_VECTOR(15 downto 0);
PCI_AD : INOUT STD_LOGIC_VECTOR(15 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END REGISTERS;
-- Architecture Body
ARCHITECTURE REGISTERS_architecture OF REGISTERS IS
----------------------
-- Signal Declaration
----------------------
-- Internal Registers
signal VME_R_registers : SHAREDREGISTERS(15 downto 0); -- this is an array of VLong
signal VME_RW_registers : SHAREDREGISTERS(15 downto 0); -- this is an array of VLong
signal INT_IN : std_logic; --interrupt reguest to PCI slave
signal relays : std_logic_vector(7 downto 0);
signal write_result0_dpram,write_result1_dpram, write_result_synchr, write_offset_synchr : std_logic;
--DPRAm access signals from PCI slave
signal REGS_RW_DAT_READ : STD_LOGIC_VECTOR(31 downto 0);
signal REGS_RW_DAT_WRITE : STD_LOGIC_VECTOR(31 downto 0);
signal REGS_RW_ADDR : STD_LOGIC_VECTOR(4 downto 0);
signal REGS_RW_WREN : STD_LOGIC;
signal REGS_R_DAT_READ : STD_LOGIC_VECTOR(31 downto 0);
signal REGS_R_ADDR : STD_LOGIC_VECTOR(4 downto 0);
signal DPRAM0_RW_DAT_READ : STD_LOGIC_VECTOR(31 downto 0);
signal DPRAM0_RW_DAT_WRITE : STD_LOGIC_VECTOR(31 downto 0);
signal DPRAM0_RW_ADDR : STD_LOGIC_VECTOR(6 downto 0);
signal DPRAM0_RW_WREN : STD_LOGIC;
signal DPRAM1_R_DAT_READ : STD_LOGIC_VECTOR(31 downto 0);
signal DPRAM1_R_ADDR : STD_LOGIC_VECTOR(6 downto 0);
signal DPRAM2_R_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal DPRAM2_R_ADDR : STD_LOGIC_VECTOR(10 downto 0);
signal DPRAM3_R_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal DPRAM3_R_ADDR : STD_LOGIC_VECTOR(10 downto 0);
--DPRAM access signals from integrator state machine
signal PARAM_DPRAM0_RD_ADDRESS : STD_LOGIC_VECTOR(6 downto 0);
signal PARAM_DPRAM0_RD_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal RESULT_DPRAM1_W_ADDRESS : STD_LOGIC_VECTOR(6 downto 0);
signal RESULT_DPRAM1_W_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal RESULT_DPRAM1_W_WREN : STD_LOGIC;
signal synchr_result1,synchr_result2 : STD_LOGIC_VECTOR(31 downto 0);
signal Result_ready,clear_ADC_flags : STD_LOGIC;
signal ADC_busy : STD_LOGIC;
signal DPRAM_ADDR_RST : std_logic;
signal test_sig : STD_LOGIC_VECTOR(31 downto 0);
component PCI_SLAVE
port (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
REGS_RW_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
REGS_RW_DAT_WRITE : OUT STD_LOGIC_VECTOR(31 downto 0);
REGS_RW_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
REGS_RW_WREN : OUT STD_LOGIC;
REGS_R_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
REGS_R_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0);
DPRAM0_RW_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM0_RW_DAT_WRITE : OUT STD_LOGIC_VECTOR(31 downto 0);
DPRAM0_RW_ADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
DPRAM0_RW_WREN : OUT STD_LOGIC;
DPRAM1_R_DAT_READ : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM1_R_ADDR : OUT STD_LOGIC_VECTOR(6 downto 0);
DPRAM2_R_DATA : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM2_R_ADDR : OUT STD_LOGIC_VECTOR(10 downto 0);
DPRAM3_R_DATA : IN STD_LOGIC_VECTOR(31 downto 0);
DPRAM3_R_ADDR : OUT STD_LOGIC_VECTOR(10 downto 0);
DPRAM_ADDR_RST : IN STD_LOGIC;
PCI_FRAMEn : IN STD_LOGIC;
PCI_BEn : IN STD_LOGIC_VECTOR(1 downto 0);
PCI_IRDYn : IN STD_LOGIC;
PCI_TRDYn : buffer STD_LOGIC;
PCI_INTn : OUT STD_LOGIC;
PCI_AD : INOUT STD_LOGIC_VECTOR(15 downto 0);
INT_IN : IN STD_LOGIC;
TEST1 : OUT STD_LOGIC_VECTOR(31 downto 0);
TEST2 : OUT STD_LOGIC_VECTOR(31 downto 0));
end component;
signal reset_data_set : std_logic;
signal data_set_count : std_logic_vector (4 downto 0);
--***********************************************************************************************************************************************
--********************************************* Signal analyser *********************************************************
--***********************************************************************************************************************************************
component analyser
port (
clk : in std_logic;
reset : in std_logic;
ANA_record_len : in std_logic_vector(9 downto 0);
ANA_addr_pointer : out std_logic_vector(9 downto 0);
ANA_RD_addr : in std_logic_vector(10 downto 0);
ANA_RD_DAT : out std_logic_vector(31 downto 0);
ANA_slope : in std_logic;
ANA_ARM : in std_logic;
ANA_timer_en : in std_logic;
ANA_DATA_ACQUIRED : out std_logic;
ANA_ARMED : out std_logic;
ANA_trig : in std_logic_vector(7 downto 0);
data_0 : in std_logic_vector(31 downto 0);
data_1 : in std_logic_vector(31 downto 0);
data_2 : in std_logic_vector(31 downto 0);
data_3 : in std_logic_vector(31 downto 0);
ANA_trig_src : in std_logic_vector(2 downto 0);
ANA_CH1_src : in std_logic_vector(1 downto 0);
ANA_CH2_src : in std_logic_vector(1 downto 0);
ANA_timer : in std_logic_vector(23 downto 0);
ANA_delay : in std_logic_vector(31 downto 0);
ANA_tick_out : out std_logic);
end component;
signal ANA_record_len : std_logic_vector(9 downto 0);
signal ANA_addr_pointer : std_logic_vector(9 downto 0);
signal ANA_RD_addr : std_logic_vector(10 downto 0);
signal ANA_RD_DAT : std_logic_vector(31 downto 0);
signal ANA_slope : std_logic;
signal ANA_ARM : std_logic;
signal ANA_timer_en : std_logic;
signal ANA_DATA_ACQUIRED : std_logic;
signal ANA_ARMED : std_logic;
signal ANA_trig : std_logic_vector(7 downto 0);
signal data_0 : std_logic_vector(31 downto 0);
signal data_1 : std_logic_vector(31 downto 0);
signal data_2 : std_logic_vector(31 downto 0);
signal data_3 : std_logic_vector(31 downto 0);
signal ANA_trig_src : std_logic_vector(2 downto 0);
signal ANA_CH1_src : std_logic_vector(1 downto 0);
signal ANA_CH2_src : std_logic_vector(1 downto 0);
signal ANA_timer : std_logic_vector(23 downto 0);
signal ANA_delay : std_logic_vector(31 downto 0);
signal ANA_tick_out : std_logic;
constant glitch_capt : integer := 13;
signal data_pulse_capt : std_logic_vector(glitch_capt-1 downto 0);
signal ANA_DAT : std_logic_vector(glitch_capt-1 downto 0);
BEGIN
--***********************************************************************************************************************************************
--********************************************* PCI SLAVE intefrace mapping *********************************************************
--***********************************************************************************************************************************************
INT_IN <= '0';
PCI_SLAVE_1: PCI_SLAVE
port map (
CLK => PCI_CLK,
RESET => RESET,
REGS_RW_DAT_READ => REGS_RW_DAT_READ,
REGS_RW_DAT_WRITE => REGS_RW_DAT_WRITE,
REGS_RW_ADDR => REGS_RW_ADDR,
REGS_RW_WREN => REGS_RW_WREN,
REGS_R_DAT_READ => REGS_R_DAT_READ,
REGS_R_ADDR => REGS_R_ADDR,
DPRAM0_RW_DAT_READ => x"00000000",
DPRAM0_RW_DAT_WRITE => open,
DPRAM0_RW_ADDR => open,
DPRAM0_RW_WREN => open,
DPRAM1_R_DAT_READ => DPRAM_D,--adc buffer data
--debug
--debug
--debug
--DPRAM1_R_DAT_READ => x"12345678",--adc buffer data
--debug
--debug
--debug
DPRAM1_R_ADDR => DPRAM_A(6 downto 0),--adc buffer address
DPRAM2_R_DATA => x"00000000",
DPRAM2_R_ADDR => open,
DPRAM3_R_DATA => x"00000000",
DPRAM3_R_ADDR => open,
DPRAM_ADDR_RST => DPRAM_ADDR_RST,
PCI_FRAMEn => PCI_FRAMEn,
PCI_BEn => PCI_BEn,
PCI_IRDYn => PCI_IRDYn,
PCI_TRDYn => PCI_TRDYn,
PCI_INTn => PCI_INTn,
PCI_AD => PCI_AD,
INT_IN => INT_IN,
TEST1 => test_sig,
TEST2 => open);
pci_test<= test_sig(7 downto 0);
--***********************************************************************************************************************************************
--********************************************* status bit generation **********************************************************
--***********************************************************************************************************************************************
process(CLK, reset)
begin
if rising_edge(CLK) then
if reset = '1' then
Result_ready <= '0';
ADC_busy <= '0';
elsif measurement_done = '1' then
Result_ready <= '1';
ADC_busy <= '0';
elsif sample = '1' then
ADC_busy <= '1';
elsif clear_ADC_flags = '1' then
Result_ready <= '0';
ADC_busy <= '0';
end if;
end if;
end process;
--***********************************************************************************************************************************************
--********************************************* Registers PCI read/write *********************************************************
--***********************************************************************************************************************************************
--RW registers write
process(PCI_CLK, reset)
begin
if rising_edge(PCI_CLK) then
if REGS_RW_WREN = '1' then
VME_RW_registers (TO_INTEGER(UNSIGNED(REGS_RW_ADDR))) <= REGS_RW_DAT_WRITE;
end if;
end if;
end process;
--RW registers read
REGS_RW_DAT_READ <= VME_RW_registers (TO_INTEGER(UNSIGNED(REGS_RW_ADDR)));
--R registers read
REGS_R_DAT_READ <= VME_R_registers (TO_INTEGER(UNSIGNED(REGS_R_ADDR)));
--***********************************************************************************************************************************************
--********************************************* measurement result write *********************************************************
--***********************************************************************************************************************************************
Wr_Regs : PROCESS ( reset, PCI_CLK )
BEGIN
IF reset = '1' THEN
VME_R_registers(0) <= (OTHERS => '0');
VME_R_registers(1) <= (OTHERS => '0');
VME_R_registers(2) <= (OTHERS => '0');
VME_R_registers(3) <= (OTHERS => '0');
VME_R_registers(4) <= (OTHERS => '0');
-- VME_R_registers(5) <= (OTHERS => '0');
-- VME_R_registers(6) <= (OTHERS => '0');
-- VME_R_registers(7) <= (OTHERS => '0');
VME_R_registers(8) <= (OTHERS => '0');
VME_R_registers(9) <= (OTHERS => '0');
VME_R_registers(10) <= (OTHERS => '0');
VME_R_registers(11) <= (OTHERS => '0');
VME_R_registers(12) <= (OTHERS => '0');
VME_R_registers(13) <= (OTHERS => '0');
VME_R_registers(14) <= (OTHERS => '0');
VME_R_registers(15) <= (OTHERS => '0');
ELSIF Rising_edge ( PCI_CLK) THEN
end if;
end process;
-- regs_rw_sel --0x0000
-- regs_r_sel --0x0080
-- dpram0_sel --0x0100
-- dpram1_sel --0x0180
-- dpram2_sel --0x0200
-- dpram3_sel --0x0280
--***********************************************************************************************************************************************
--********************************************* RW registers mapping *********************************************************
--***********************************************************************************************************************************************
--control registers
--0x0000
clear_ADC_flags <= VME_RW_registers(0)(0);
ARM <= VME_RW_registers(0)(1);
software_trigger <= VME_RW_registers(0)(2);
sampling_clk_source <= VME_RW_registers(0)(3);
trig_select <= VME_RW_registers(0)(4);
sampling_freq <= VME_RW_registers(1)(15 downto 0); --0x0004
num_of_measurements <= VME_RW_registers(2)(15 downto 0); --0x0008
--0x000C
Single_Channel_Mode_Channel_number <= VME_RW_registers(3)(9 downto 4);
Single_Channel_Mode <= VME_RW_registers(3)(0);
--0x000F
DPRAM_A(11 downto 7) <= VME_RW_registers(4)(4 downto 0);
--status registers
VME_R_registers(5)(0) <= Result_ready;
VME_R_registers(5)(1) <= ADC_busy;
VME_R_registers(5)(2) <= armed;
VME_R_registers(5)(3) <= measurement_done;
VME_R_registers(5)(4) <= '1';
--***********************************************************************************************************************************************
--********************************************* relays and LEDs mapping *********************************************************
--***********************************************************************************************************************************************
STAT_LED(0) <= VME_RW_registers(0)(0); --clear_ADC_flags;
STAT_LED(1) <= VME_RW_registers(0)(1); --ARM
STAT_LED(2) <= VME_RW_registers(0)(2); --software_trigger
STAT_LED(3) <= VME_RW_registers(0)(3); --sampling_clk_source
STAT_LED(4) <= VME_R_registers(5)(0); --result_ready;
STAT_LED(5) <= VME_R_registers(5)(1); --ADC_busy
STAT_LED(6) <= VME_R_registers(5)(2); --armed
STAT_LED(7) <= VME_R_registers(5)(3); --measurement_done
END REGISTERS_architecture;
trunk/VHDL/ADC_Card_FPGA/SPRAM1kx32.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: SPRAM1kx32.vhd
-- Megafunction Name(s):
-- altsyncram
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SPRAM1kx32 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END SPRAM1kx32;
ARCHITECTURE SYN OF spram1kx32 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SPRAM1kx32_inst.vhd TRUE
trunk/VHDL/ADC_Card_FPGA/altpll0.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 6,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 40000,
intended_device_family => "Cyclone II",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "6"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
trunk/VHDL/ADC_Card_FPGA/analyser.vhd 0 → 100644
View file @ f7ea7ecc
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:31:32 03/13/06
-- Design Name:
-- Module Name: control_unit - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity analyser is
Port (
clk : in std_logic;
reset : in std_logic;
ANA_record_len : in std_logic_vector(9 downto 0);
ANA_addr_pointer : out std_logic_vector(9 downto 0);
ANA_RD_addr : in std_logic_vector(10 downto 0);
ANA_RD_DAT : out std_logic_vector(31 downto 0);
ANA_slope : in std_logic;
ANA_ARM : in std_logic;
ANA_timer_en : in std_logic;
ANA_DATA_ACQUIRED : out std_logic;
ANA_ARMED : out std_logic;
ANA_trig : in std_logic_vector(7 downto 0);
data_0 : in std_logic_vector(31 downto 0);
data_1 : in std_logic_vector(31 downto 0);
data_2 : in std_logic_vector(31 downto 0);
data_3 : in std_logic_vector(31 downto 0);
ANA_trig_src : in std_logic_vector(2 downto 0);
ANA_CH1_src : in std_logic_vector(1 downto 0);
ANA_CH2_src : in std_logic_vector(1 downto 0);
ANA_timer : in std_logic_vector(23 downto 0);
ANA_delay : in std_logic_vector(31 downto 0);
ANA_tick_out : out std_logic
);
end analyser;
architecture Behavioral of analyser is
--counters signals
signal addr_cnt,RAM_addr,
sample_cnt : std_logic_vector(9 downto 0);
signal addr_cnt_en,
sample_cnt_en,
sample_cnt_end,
sample_cnt_load : std_logic;
signal delay_cnt : std_logic_vector(31 downto 0) ;
signal delay_cnt_en,
delay_cnt_load,
delay_cnt_end : std_logic;
signal RAM1_rd_dat,
RAM2_rd_dat,
CH1_din,
CH2_din : std_logic_vector(31 downto 0) ;
signal clk_en,clock_enable : std_logic;
signal timer : std_logic_vector(23 downto 0) ;
signal trig_sel,
RAM_wren : std_logic;
signal trig_edge_det : std_logic_vector(3 downto 0) ;
signal trig_edge_r : std_logic;
signal trig_edge_f : std_logic;
signal trig_edge : std_logic;
TYPE STATE_TYPE IS (idle,wait_trig,capture,completed,trig_delay);
SIGNAL state: STATE_TYPE;
component SPRAM1kx32
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
--***************************************************************************************************
--*************************************** data input selector *******************************
--***************************************************************************************************
with ANA_CH2_src select
CH2_din <= data_0 when "00",
data_1 when "01",
data_2 when "10",
data_3 when others;
with ANA_CH1_src select
CH1_din <= data_0 when "00",
data_1 when "01",
data_2 when "10",
data_3 when others;
--***************************************************************************************************
--*************************************** trigger input selector *******************************
--***************************************************************************************************
with ANA_trig_src select
trig_sel <= ANA_trig(0) when "000",
ANA_trig(1) when "001",
ANA_trig(2) when "010",
ANA_trig(3) when "011",
ANA_trig(4) when "100",
ANA_trig(5) when "101",
ANA_trig(6) when "110",
ANA_trig(7) when others;
--***************************************************************************************************
--*************************************** trigger edge detection *******************************
--***************************************************************************************************
process (clk)
begin
if rising_edge(clk) then
trig_edge_det(0)<= trig_sel;
trig_edge_det(1)<=trig_edge_det(0);
trig_edge_det(2)<=trig_edge_det(1);
trig_edge_det(3)<=trig_edge_det(2);
end if;
end process;
trig_edge_f <= (not trig_edge_det(0)) and (not trig_edge_det(1)) and trig_edge_det(2)and trig_edge_det(3) ;
trig_edge_r <= (not trig_edge_det(3)) and (not trig_edge_det(2)) and trig_edge_det(1)and trig_edge_det(0) ;
trig_edge <= trig_edge_r when ANA_slope = '0' else trig_edge_f;
--***************************************************************************************************
--*************************************** main state machine *******************************
--***************************************************************************************************
PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
state <= idle;
ELSIF rising_edge(clk) THEN
CASE state IS
WHEN idle =>
IF ANA_ARM ='1' THEN
state <= wait_trig;
END IF;
WHEN wait_trig=>
IF trig_edge ='1' THEN
state <= trig_delay;
END IF;
WHEN trig_delay =>
IF delay_cnt_end='1' THEN
state <= capture;
END IF;
WHEN capture=>
IF sample_cnt_end ='1' THEN
state <= completed;
END IF;
WHEN completed=>
IF ANA_ARM ='0' THEN
state <= idle;
END IF;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
delay_cnt_en <= '1' WHEN trig_delay,
'0' WHEN others;
WITH state SELECT
delay_cnt_load <= '1' WHEN wait_trig,
'0' WHEN others;
WITH state SELECT
addr_cnt_en <= '0' WHEN completed, --register data all the time except reading sequence
clock_enable WHEN others;
WITH state SELECT
sample_cnt_en <= '1' WHEN capture,
'0' WHEN others;
WITH state SELECT
sample_cnt_load <= '1' WHEN trig_delay,
'0' WHEN others;
WITH state SELECT
RAM_wren <= '0' WHEN completed, --register data all the time except reading sequence
clock_enable WHEN others;
WITH state SELECT
ANA_DATA_ACQUIRED <= '1' WHEN completed,
'0' WHEN others;
WITH state SELECT
ANA_ARMED <= '0' WHEN idle,
'1' WHEN others;
--***************************************************************************************************
--*************************************** bufer memories *******************************
--***************************************************************************************************
--switching address bus between writes/reads
RAM_addr <= ANA_RD_addr(9 downto 0) when (state = completed) else addr_cnt;
buffer1 : SPRAM1kx32 PORT MAP
(
address => RAM_addr,
clock => clk,
data => CH1_din,
wren => RAM_wren,
q => RAM1_rd_dat
);
buffer2 : SPRAM1kx32 PORT MAP
(
address => RAM_addr,
clock => clk,
data => CH2_din,
wren => RAM_wren,
q => RAM2_rd_dat
);
--switching RAM READ data bus between 2 memories depending on MSB READ address bit.
ANA_RD_DAT <= RAM1_rd_dat when ANA_RD_addr(10) = '0' else RAM2_rd_dat;
--***************************************************************************************************
--*************************************** counters *******************************
--***************************************************************************************************
--DPRAM address counter
process(clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
addr_cnt <= (others=>'0');
elsif addr_cnt_en = '1' then
addr_cnt <= addr_cnt+'1';
end if;
end if;
end process;
--trigger delay counter
process(clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
delay_cnt <= (others=>'0');
elsif delay_cnt_load = '1' then
delay_cnt <= ANA_delay;
elsif delay_cnt_en = '1' then
delay_cnt <= delay_cnt - '1';
end if;
if delay_cnt = x"FFFFFFFF" then
delay_cnt_end <= '1';
else
delay_cnt_end <= '0';
end if;
end if;
end process;
--sample number counter
process(clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
sample_cnt <= (others=>'0');
elsif sample_cnt_load = '1' then
sample_cnt <= ANA_record_len;
elsif sample_cnt_en = '1' then
sample_cnt <= sample_cnt - '1';
end if;
if sample_cnt = "0000001" then
sample_cnt_end <= '1';
else
sample_cnt_end <= '0';
end if;
end if;
end process;
--data address pointer latch
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
ANA_addr_pointer <= (others=>'0');
elsif state = completed then
ANA_addr_pointer <= addr_cnt;
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------
--CLK generator
------------------------------------------------------------------------------------------------------
process(clk,reset,timer)
begin
if reset='1' then
timer<=x"000100";
elsif clk'event and clk ='0' then
if clk_en = '1' then
timer <= ANA_timer ;
else
timer <=timer -'1';
end if;
end if;
if timer = "000000" then
clk_en<='1';
else
clk_en<='0';
end if;
end process;
clock_enable <= clk_en when ANA_timer_en = '1' else '1';
ANA_tick_out <= clk_en;
end Behavioral;
trunk/VHDL/ADC_Card_FPGA/clk_pll.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.1 Build 156 04/30/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END clk_pll;
ARCHITECTURE SYN OF clk_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "20833",
compensate_clock => "CLK0",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "504.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "20833"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll.ppf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_pll_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
trunk/VHDL/ADC_Card_FPGA/clkdivider.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clkdivider is
generic (
divider : integer := 50); -- number of clocks to generate enable pulse
port (
clk : in std_logic; -- general clock
reset : in std_logic; -- async reset
clkenable : out std_logic); -- clock enable used to turn on the clock
end clkdivider;
architecture v1 of clkdivider is
begin -- v1
-- purpose: counts down to zero and when at zero, then it generates clkenable pulse which is exactly 1 tick lock
-- type : sequential
-- inputs : clk, reset
count: process (clk, reset)
variable counter : integer range divider downto 0;
-- counter stuff
begin -- process count
if reset = '1' then -- asynchronous reset (active high)
counter := divider; -- set the state to the divider val.
elsif clk'event and clk = '1' then -- rising clock edge
counter := counter - 1; -- decrease counts
if counter = 0 then
counter := divider;
clkenable <= '1';
else
clkenable <= '0';
end if;
end if;
end process count;
end v1;
trunk/VHDL/ADC_Card_FPGA/dpram_32x32.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram_32x32.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.1 Build 156 04/30/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram_32x32 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dpram_32x32;
ARCHITECTURE SYN OF dpram_32x32 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 5,
widthad_b => 5,
width_a => 32,
width_b => 32,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0]
-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32x32_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
trunk/VHDL/ADC_Card_FPGA/hct4094.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2003 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Generated by Quartus II Version 2.2 (Build Build 191 03/31/2003)
-- Created on Wed Nov 19 12:02:12 2003
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY hct4094 IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
GENERIC (
data_len : integer := 24;
glitch_capt : integer := 16
);
PORT
(
clk : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
reset : IN STD_LOGIC;
data_in: IN STD_LOGIC_VECTOR(data_len-1 downto 0);
test1 : OUT STD_LOGIC;
test2 : OUT STD_LOGIC;
test3 : OUT STD_LOGIC;
test4 : OUT STD_LOGIC;
str : OUT STD_LOGIC;
data : OUT STD_LOGIC;
sck : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END hct4094;
-- Architecture Body
ARCHITECTURE a OF hct4094 IS
TYPE STATE_TYPE IS (
idle,
sync_l,
sync_h,
data_l,
data_h,
data_end,
next_tx
);
SIGNAL state: STATE_TYPE;
signal shift_count : integer range 2*data_len downto 0;
signal shiftreg,data_shift : std_logic_vector (data_len-1 downto 0);
signal shift_enable,
shifter_load,
sck_temp,sck_buffer,
str_temp,
shift_reset,
data_temp,
stop_shift,
str_del,
reset_capt_logic : std_logic ;
BEGIN
--***********************************************************************************************************************************************
--******************************************* short pulse capture *********************************************************************
--***********************************************************************************************************************************************
glitch_capture_logic:
FOR i IN 0 to glitch_capt-1 GENERATE
begin
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
data_shift(i) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
if reset_capt_logic = '1' then
data_shift(i) <= '0';
elsif data_in(i) = '1' then
data_shift(i) <= '1';
end if;
END IF;
END PROCESS;
END GENERATE;
non_glitch_capture_logic:
FOR i IN glitch_capt to data_len-1 GENERATE
data_shift(i) <= data_in(i);
END GENERATE;
--***********************************************************************************************************************************************
--******************************************* data transfer state machine *********************************************************************
--***********************************************************************************************************************************************
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
state <= idle;
ELSIF clk'EVENT AND clk = '1' THEN
if clk_en = '1' then
CASE state IS
WHEN idle =>
state <=sync_l;
when sync_l =>
state<=sync_h;
when sync_h =>
state<=data_l;
when data_l =>
if stop_shift = '1' then
state <= data_end;
else
state<=data_h;
end if;
when data_h =>
state<=data_l;
when data_end =>
state<=next_tx;
when next_tx=>
state<=idle;
when others=>
state<=idle;
END CASE;
end if;
END IF;
END PROCESS;
WITH state SELECT
shift_reset <= '1' when idle,
'1' when sync_l,
'1' when sync_h,
'0' when data_l,
'0' when data_h,
'0' when data_end,
'0' when next_tx;
WITH state SELECT
sck_temp <= '0' when idle,
'0' when sync_l,
'0' when sync_h,
'0' when data_l,
'1' when data_h,
'0' when data_end,
'0' when next_tx;
WITH state SELECT
shift_enable <= '0' when idle,
'0' when sync_l,
'0' when sync_h,
'1' when data_l,
'1' when data_h,
'0' when data_end,
'0' when next_tx;
WITH state SELECT
shifter_load <= '0' when idle,
'1' when sync_l,
'1' when sync_h,
'0' when data_l,
'0' when data_h,
'0' when data_end,
'0' when next_tx;
WITH state SELECT
str_temp <= '0' when idle,
'0' when sync_l,
'0' when sync_h,
'0' when data_l,
'0' when data_h,
'1' when data_end,
'1' when next_tx;
process(clk)
begin
if clk'event and clk='1' then
if clk_en = '1' then
if state = sync_h then
reset_capt_logic <= '1';
else
reset_capt_logic <= '0';
end if;
end if;
end if;
end process;
process(clk,shift_count)
begin
if clk'event and clk='1' then
if clk_en = '1' then
if shift_reset='1' or reset = '1' then
shift_count<=0;
stop_shift <= '0';
elsif stop_shift='0' then
shift_count <=shift_count+1;
end if;
end if;
end if;
if shift_count = (2*data_len) then
stop_shift<='1';
else
stop_shift<='0';
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if clk_en = '1' then
sck_buffer<=sck_temp;
sck<=sck_buffer;
str_del<=str_temp;
str<=str_del;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
data<=data_temp;
end if;
end process;
Process (clk)
begin
if clk'event and clk='1' then
if clk_en = '1' then
if shifter_load = '1' then
shiftreg <= data_shift;
elsif sck_buffer='0' then
if (shift_enable) = '1' THEN
shiftreg(data_len-1 downto 0) <= shiftreg(data_len-2 downto 0) & '0';
data_temp <=shiftreg(data_len-1);
end if;
end if;
end if;
end if;
end process;
test1<= shifter_load;
test2<=reset_capt_logic;
test3<=shift_reset;
test4<=shift_enable;
END a;
trunk/VHDL/ADC_Card_FPGA/indicators.vhd 0 → 100644
View file @ f7ea7ecc
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 6.0 (Build Build 202 06/20/2006)
-- Created on Wed May 02 11:27:03 2007
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY indicators IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
STAT_REGS_IN : IN STD_LOGIC_VECTOR(7 downto 0);
sck : OUT STD_LOGIC;
sdat : OUT STD_LOGIC;
strobe : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END indicators;
-- Architecture Body
ARCHITECTURE indicators_architecture OF indicators IS
signal LED_data : STD_LOGIC_VECTOR(7 downto 0);
component hct4094
generic (
data_len : integer;
glitch_capt : integer);
port (
clk : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
reset : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(data_len-1 downto 0);
test1 : OUT STD_LOGIC;
test2 : OUT STD_LOGIC;
test3 : OUT STD_LOGIC;
test4 : OUT STD_LOGIC;
str : OUT STD_LOGIC;
data : OUT STD_LOGIC;
sck : OUT STD_LOGIC);
end component;
BEGIN
LED_data(7 downto 0) <= STAT_REGS_IN;
hct4094_1: hct4094
generic map (
data_len => 8,
glitch_capt => 8)
port map (
clk => clk,
clk_en => clk_en,
-- clk_en => '1',
reset => reset,
data_in => LED_data,
test1 => open,
test2 => open,
test3 => open,
test4 => open,
str => strobe,
data => sdat,
sck => sck);
END indicators_architecture;
trunk/VHDL/ADC_Card_FPGA/lpm_or0.vhd 0 → 100644
View file @ f7ea7ecc
-- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: lpm_or0.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.1 Build 156 04/30/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_or0 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_or0;
ARCHITECTURE SYN OF lpm_or0 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
sub_wire3 <= data0x(7 DOWNTO 0);
result <= sub_wire0(7 DOWNTO 0);
sub_wire1 <= data1x(7 DOWNTO 0);
sub_wire2(1, 0) <= sub_wire1(0);
sub_wire2(1, 1) <= sub_wire1(1);
sub_wire2(1, 2) <= sub_wire1(2);
sub_wire2(1, 3) <= sub_wire1(3);
sub_wire2(1, 4) <= sub_wire1(4);
sub_wire2(1, 5) <= sub_wire1(5);
sub_wire2(1, 6) <= sub_wire1(6);
sub_wire2(1, 7) <= sub_wire1(7);
sub_wire2(0, 0) <= sub_wire3(0);
sub_wire2(0, 1) <= sub_wire3(1);
sub_wire2(0, 2) <= sub_wire3(2);
sub_wire2(0, 3) <= sub_wire3(3);
sub_wire2(0, 4) <= sub_wire3(4);
sub_wire2(0, 5) <= sub_wire3(5);
sub_wire2(0, 6) <= sub_wire3(6);
sub_wire2(0, 7) <= sub_wire3(7);
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_OR",
lpm_width => 8
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "8"
-- Retrieval info: PRIVATE: nInput NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
trunk/VHDL/ADC_Card_FPGA/onchip_mem.vhd 0 → 100644
View file @ f7ea7ecc
--Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity onchip_mem is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clken : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity onchip_mem;
architecture europa of onchip_mem is
--synthesis translate_off
component altsyncram is
GENERIC (
byte_size : NATURAL;
lpm_type : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL
);
PORT (
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal clocken0 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- component altsyncram is
--GENERIC (
-- byte_size : NATURAL;
-- init_file : STRING;
-- lpm_type : STRING;
-- maximum_depth : NATURAL;
-- numwords_a : NATURAL;
-- operation_mode : STRING;
-- outdata_reg_a : STRING;
-- ram_block_type : STRING;
-- read_during_write_mode_mixed_ports : STRING;
-- width_a : NATURAL;
-- width_byteena_a : NATURAL;
-- widthad_a : NATURAL
-- );
-- PORT (
-- signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal wren_a : IN STD_LOGIC;
-- signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-- signal clock0 : IN STD_LOGIC;
-- signal address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
-- signal clocken0 : IN STD_LOGIC;
-- signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
-- end component altsyncram;
--synthesis read_comments_as_HDL off
signal internal_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren : STD_LOGIC;
begin
wren <= chipselect AND write;
--s1, which is an e_avalon_slave
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
--synthesis translate_off
the_altsyncram : altsyncram
generic map(
byte_size => 8,
lpm_type => "altsyncram",
maximum_depth => 1024,
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_reg_a => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_byteena_a => 4,
widthad_a => 10
)
port map(
address_a => address,
byteena_a => byteenable,
clock0 => clk,
clocken0 => clken,
data_a => writedata,
q_a => internal_readdata,
wren_a => wren
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- the_altsyncram : altsyncram
-- generic map(
-- byte_size => 8,
-- init_file => "UNUSED",
-- lpm_type => "altsyncram",
-- maximum_depth => 1024,
-- numwords_a => 1024,
-- operation_mode => "SINGLE_PORT",
-- outdata_reg_a => "UNREGISTERED",
-- ram_block_type => "AUTO",
-- read_during_write_mode_mixed_ports => "DONT_CARE",
-- width_a => 32,
-- width_byteena_a => 4,
-- widthad_a => 10
-- )
-- port map(
-- address_a => address,
-- byteena_a => byteenable,
-- clock0 => clk,
-- clocken0 => clken,
-- data_a => writedata,
-- q_a => internal_readdata,
-- wren_a => wren
-- );
--
--synthesis read_comments_as_HDL off
end europa;
trunk/VHDL/ADC_Card_FPGA/sdram.vhd 0 → 100644
View file @ f7ea7ecc
--Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sdram_input_efifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal rd : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wr : IN STD_LOGIC;
signal wr_data : IN STD_LOGIC_VECTOR (58 DOWNTO 0);
-- outputs:
signal almost_empty : OUT STD_LOGIC;
signal almost_full : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal full : OUT STD_LOGIC;
signal rd_data : OUT STD_LOGIC_VECTOR (58 DOWNTO 0)
);
end entity sdram_input_efifo_module;
architecture europa of sdram_input_efifo_module is
signal entries : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal entry_0 : STD_LOGIC_VECTOR (58 DOWNTO 0);
signal entry_1 : STD_LOGIC_VECTOR (58 DOWNTO 0);
signal internal_empty : STD_LOGIC;
signal internal_full : STD_LOGIC;
signal rd_address : STD_LOGIC;
signal rdwr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wr_address : STD_LOGIC;
begin
rdwr <= Std_Logic_Vector'(A_ToStdLogicVector(rd) & A_ToStdLogicVector(wr));
internal_full <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries)) = std_logic_vector'("00000000000000000000000000000010")));
almost_full <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries))>=std_logic_vector'("00000000000000000000000000000001")));
internal_empty <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries)) = std_logic_vector'("00000000000000000000000000000000")));
almost_empty <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (entries))<=std_logic_vector'("00000000000000000000000000000001")));
process (entry_0, entry_1, rd_address)
begin
case rd_address is -- synthesis parallel_case full_case
when std_logic'('0') =>
rd_data <= entry_0;
-- when std_logic'('0')
when std_logic'('1') =>
rd_data <= entry_1;
-- when std_logic'('1')
when others =>
-- when others
end case; -- rd_address
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
wr_address <= std_logic'('0');
rd_address <= std_logic'('0');
entries <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
case rdwr is -- synthesis parallel_case full_case
when std_logic_vector'("01") =>
-- Write data
if std_logic'(NOT(internal_full)) = '1' then
entries <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (entries)) + std_logic_vector'("000000000000000000000000000000001")), 2);
wr_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) + std_logic_vector'("000000000000000000000000000000001")))));
end if;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
-- Read data
if std_logic'(NOT(internal_empty)) = '1' then
entries <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (entries)) - std_logic_vector'("000000000000000000000000000000001")), 2);
rd_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) + std_logic_vector'("000000000000000000000000000000001")))));
end if;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
wr_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(wr_address))) + std_logic_vector'("000000000000000000000000000000001")))));
rd_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) = std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rd_address))) + std_logic_vector'("000000000000000000000000000000001")))));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- rdwr
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
--Write data
if std_logic'((wr AND NOT(internal_full))) = '1' then
case wr_address is -- synthesis parallel_case full_case
when std_logic'('0') =>
entry_0 <= wr_data;
-- when std_logic'('0')
when std_logic'('1') =>
entry_1 <= wr_data;
-- when std_logic'('1')
when others =>
-- when others
end case; -- wr_address
end if;
end if;
end process;
--vhdl renameroo for output signals
empty <= internal_empty;
--vhdl renameroo for output signals
full <= internal_full;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port (
-- inputs:
signal az_addr : IN STD_LOGIC_VECTOR (21 DOWNTO 0);
signal az_be_n : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal az_cs : IN STD_LOGIC;
signal az_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal az_rd_n : IN STD_LOGIC;
signal az_wr_n : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal za_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal za_valid : OUT STD_LOGIC;
signal za_waitrequest : OUT STD_LOGIC;
signal zs_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal zs_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_cas_n : OUT STD_LOGIC;
signal zs_cke : OUT STD_LOGIC;
signal zs_cs_n : OUT STD_LOGIC;
signal zs_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal zs_dqm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal zs_ras_n : OUT STD_LOGIC;
signal zs_we_n : OUT STD_LOGIC
);
end entity sdram;
architecture europa of sdram is
component sdram_input_efifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal rd : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wr : IN STD_LOGIC;
signal wr_data : IN STD_LOGIC_VECTOR (58 DOWNTO 0);
-- outputs:
signal almost_empty : OUT STD_LOGIC;
signal almost_full : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal full : OUT STD_LOGIC;
signal rd_data : OUT STD_LOGIC_VECTOR (58 DOWNTO 0)
);
end component sdram_input_efifo_module;
signal CODE : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal ack_refresh_request : STD_LOGIC;
signal active_addr : STD_LOGIC_VECTOR (21 DOWNTO 0);
signal active_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal active_cs_n : STD_LOGIC;
signal active_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal active_dqm : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal active_rnw : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal bank_match : STD_LOGIC;
signal cas_addr : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal clk_en : STD_LOGIC;
signal cmd_all : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal cmd_code : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal cs_n : STD_LOGIC;
signal csn_decode : STD_LOGIC;
signal csn_match : STD_LOGIC;
signal f_addr : STD_LOGIC_VECTOR (21 DOWNTO 0);
signal f_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal f_cs_n : STD_LOGIC;
signal f_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal f_dqm : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal f_empty : STD_LOGIC;
signal f_pop : STD_LOGIC;
signal f_rnw : STD_LOGIC;
signal f_select : STD_LOGIC;
signal fifo_read_data : STD_LOGIC_VECTOR (58 DOWNTO 0);
signal i_addr : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal i_cmd : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal i_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_next : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_refs : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal i_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal init_done : STD_LOGIC;
signal internal_za_waitrequest : STD_LOGIC;
signal m_addr : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m_bank : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal m_cmd : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal m_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal m_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal m_dqm : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal m_next : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal m_state : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal module_input : STD_LOGIC;
signal module_input1 : STD_LOGIC_VECTOR (58 DOWNTO 0);
signal oe : STD_LOGIC;
signal pending : STD_LOGIC;
signal rd_strobe : STD_LOGIC;
signal rd_valid : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal refresh_counter : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal refresh_request : STD_LOGIC;
signal rnw_match : STD_LOGIC;
signal row_match : STD_LOGIC;
signal txt_code : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal za_cannotrefresh : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of m_addr : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_bank : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_cmd : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_data : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of m_dqm : signal is "FAST_OUTPUT_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of za_data : signal is "FAST_INPUT_REGISTER=ON";
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
(zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n) <= m_cmd;
zs_addr <= m_addr;
zs_cke <= clk_en;
zs_dq <= A_WE_StdLogicVector((std_logic'(oe) = '1'), m_data, A_REP(std_logic'('Z'), 32));
zs_dqm <= m_dqm;
zs_ba <= m_bank;
f_select <= f_pop AND pending;
f_cs_n <= std_logic'('0');
cs_n <= A_WE_StdLogic((std_logic'(f_select) = '1'), f_cs_n, active_cs_n);
csn_decode <= cs_n;
(f_rnw, f_addr(21), f_addr(20), f_addr(19), f_addr(18), f_addr(17), f_addr(16), f_addr(15), f_addr(14), f_addr(13), f_addr(12), f_addr(11), f_addr(10), f_addr(9), f_addr(8), f_addr(7), f_addr(6), f_addr(5), f_addr(4), f_addr(3), f_addr(2), f_addr(1), f_addr(0), f_dqm(3), f_dqm(2), f_dqm(1), f_dqm(0), f_data(31), f_data(30), f_data(29), f_data(28), f_data(27), f_data(26), f_data(25), f_data(24), f_data(23), f_data(22), f_data(21), f_data(20), f_data(19), f_data(18), f_data(17), f_data(16), f_data(15), f_data(14), f_data(13), f_data(12), f_data(11), f_data(10), f_data(9), f_data(8), f_data(7), f_data(6), f_data(5), f_data(4), f_data(3), f_data(2), f_data(1), f_data(0)) <= fifo_read_data;
--the_sdram_input_efifo_module, which is an e_instance
the_sdram_input_efifo_module : sdram_input_efifo_module
port map(
almost_empty => almost_empty,
almost_full => almost_full,
empty => f_empty,
full => internal_za_waitrequest,
rd_data => fifo_read_data,
clk => clk,
rd => f_select,
reset_n => reset_n,
wr => module_input,
wr_data => module_input1
);
module_input <= ((NOT az_wr_n OR NOT az_rd_n)) AND NOT(internal_za_waitrequest);
module_input1 <= Std_Logic_Vector'(A_ToStdLogicVector(az_wr_n) & az_addr & A_WE_StdLogicVector((std_logic'(az_wr_n) = '1'), std_logic_vector'("0000"), az_be_n) & az_data);
f_bank <= Std_Logic_Vector'(A_ToStdLogicVector(f_addr(21)) & A_ToStdLogicVector(f_addr(8)));
-- Refresh/init counter.
process (clk, reset_n)
begin
if reset_n = '0' then
refresh_counter <= std_logic_vector'("1001110001000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("0000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000") then
refresh_counter <= std_logic_vector'("0001100001101");
else
refresh_counter <= A_EXT (((std_logic_vector'("0") & (refresh_counter)) - (std_logic_vector'("0000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 13);
end if;
end if;
end process;
-- Refresh request signal.
process (clk, reset_n)
begin
if reset_n = '0' then
refresh_request <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
refresh_request <= (((to_std_logic((((std_logic_vector'("0000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR refresh_request)) AND NOT ack_refresh_request) AND init_done;
end if;
end if;
end process;
-- Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
process (clk, reset_n)
begin
if reset_n = '0' then
za_cannotrefresh <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
za_cannotrefresh <= to_std_logic((((std_logic_vector'("0000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000")))) AND refresh_request;
end if;
end if;
end process;
-- Initialization-done flag.
process (clk, reset_n)
begin
if reset_n = '0' then
init_done <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
init_done <= init_done OR to_std_logic(((i_state = std_logic_vector'("101"))));
end if;
end if;
end process;
-- **** Init FSM ****
process (clk, reset_n)
begin
if reset_n = '0' then
i_state <= std_logic_vector'("000");
i_next <= std_logic_vector'("000");
i_cmd <= std_logic_vector'("1111");
i_addr <= A_REP(std_logic'('1'), 12);
i_count <= A_REP(std_logic'('0'), 3);
elsif clk'event and clk = '1' then
i_addr <= A_REP(std_logic'('1'), 12);
case i_state is -- synthesis parallel_case full_case
when std_logic_vector'("000") =>
i_cmd <= std_logic_vector'("1111");
i_refs <= std_logic_vector'("000");
--Wait for refresh count-down after reset
if (std_logic_vector'("0000000000000000000") & (refresh_counter)) = std_logic_vector'("00000000000000000000000000000000") then
i_state <= std_logic_vector'("001");
end if;
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
i_state <= std_logic_vector'("011");
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("010"));
i_count <= std_logic_vector'("000");
i_next <= std_logic_vector'("010");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("001"));
i_refs <= A_EXT (((std_logic_vector'("0") & (i_refs)) + (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
i_state <= std_logic_vector'("011");
i_count <= std_logic_vector'("011");
-- Count up init_refresh_commands
if i_refs = std_logic_vector'("001") then
i_next <= std_logic_vector'("111");
else
i_next <= std_logic_vector'("010");
end if;
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
--WAIT til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (i_count))>std_logic_vector'("00000000000000000000000000000001") then
i_count <= A_EXT (((std_logic_vector'("0") & (i_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
i_state <= i_next;
end if;
-- when std_logic_vector'("011")
when std_logic_vector'("101") =>
i_state <= std_logic_vector'("101");
-- when std_logic_vector'("101")
when std_logic_vector'("111") =>
i_state <= std_logic_vector'("011");
i_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("000"));
i_addr <= A_REP(std_logic'('0'), 2) & A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("00") & std_logic_vector'("011") & std_logic_vector'("0000");
i_count <= std_logic_vector'("100");
i_next <= std_logic_vector'("101");
-- when std_logic_vector'("111")
when others =>
i_state <= std_logic_vector'("000");
-- when others
end case; -- i_state
end if;
end process;
active_bank <= Std_Logic_Vector'(A_ToStdLogicVector(active_addr(21)) & A_ToStdLogicVector(active_addr(8)));
csn_match <= to_std_logic((std_logic'(active_cs_n) = std_logic'(f_cs_n)));
rnw_match <= to_std_logic((std_logic'(active_rnw) = std_logic'(f_rnw)));
bank_match <= to_std_logic((active_bank = f_bank));
row_match <= to_std_logic((active_addr(20 DOWNTO 9) = f_addr(20 DOWNTO 9)));
pending <= (((csn_match AND rnw_match) AND bank_match) AND row_match) AND NOT(f_empty);
cas_addr <= A_EXT (A_WE_StdLogicVector((std_logic'(f_select) = '1'), (A_REP(std_logic'('0'), 4) & f_addr(7 DOWNTO 0)), (A_REP(std_logic'('0'), 4) & active_addr(7 DOWNTO 0))), 8);
-- **** Main FSM ****
process (clk, reset_n)
begin
if reset_n = '0' then
m_state <= std_logic_vector'("000000001");
m_next <= std_logic_vector'("000000001");
m_cmd <= std_logic_vector'("1111");
m_bank <= std_logic_vector'("00");
m_addr <= std_logic_vector'("000000000000");
m_data <= std_logic_vector'("00000000000000000000000000000000");
m_dqm <= std_logic_vector'("0000");
m_count <= std_logic_vector'("000");
ack_refresh_request <= std_logic'('0');
f_pop <= std_logic'('0');
oe <= std_logic'('0');
elsif clk'event and clk = '1' then
f_pop <= std_logic'('0');
oe <= std_logic'('0');
case m_state is -- synthesis parallel_case full_case
when std_logic_vector'("000000001") =>
--Wait for init-fsm to be done...
if std_logic'(init_done) = '1' then
--Hold bus if another cycle ended to arf.
if std_logic'(refresh_request) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
else
m_cmd <= std_logic_vector'("1111");
end if;
ack_refresh_request <= std_logic'('0');
--Wait for a read/write request.
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("001000000");
m_next <= std_logic_vector'("010000000");
m_count <= std_logic_vector'("000");
active_cs_n <= std_logic'('1');
elsif std_logic'(NOT(f_empty)) = '1' then
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= std_logic_vector'("000000010");
end if;
else
m_addr <= i_addr;
m_state <= std_logic_vector'("000000001");
m_next <= std_logic_vector'("000000001");
m_cmd <= i_cmd;
end if;
-- when std_logic_vector'("000000001")
when std_logic_vector'("000000010") =>
m_state <= std_logic_vector'("000000100");
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("011"));
m_bank <= active_bank;
m_addr <= active_addr(20 DOWNTO 9);
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= std_logic_vector'("001");
m_next <= A_WE_StdLogicVector((std_logic'(active_rnw) = '1'), std_logic_vector'("000001000"), std_logic_vector'("000010000"));
-- when std_logic_vector'("000000010")
when std_logic_vector'("000000100") =>
-- precharge all if arf, else precharge csn_decode
if m_next = std_logic_vector'("010000000") then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("111"));
else
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
end if;
--Count down til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (m_count))>std_logic_vector'("00000000000000000000000000000001") then
m_count <= A_EXT (((std_logic_vector'("0") & (m_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
m_state <= m_next;
end if;
-- when std_logic_vector'("000000100")
when std_logic_vector'("000001000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("101"));
m_bank <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_bank, active_bank);
m_dqm <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_dqm, active_dqm);
m_addr <= std_logic_vector'("0000") & (cas_addr);
--Do we have a transaction pending?
if std_logic'(pending) = '1' then
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("010");
else
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end if;
else
--correctly end RD spin cycle if fifo mt
if std_logic'((NOT pending AND f_pop)) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
end if;
m_state <= std_logic_vector'("100000000");
end if;
-- when std_logic_vector'("000001000")
when std_logic_vector'("000010000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("100"));
oe <= std_logic'('1');
m_data <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_data, active_data);
m_dqm <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_dqm, active_dqm);
m_bank <= A_WE_StdLogicVector((std_logic'(f_select) = '1'), f_bank, active_bank);
m_addr <= std_logic_vector'("0000") & (cas_addr);
--Do we have a transaction pending?
if std_logic'(pending) = '1' then
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("001");
else
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end if;
else
--correctly end WR spin cycle if fifo empty
if std_logic'((NOT pending AND f_pop)) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
oe <= std_logic'('0');
end if;
m_state <= std_logic_vector'("100000000");
end if;
-- when std_logic_vector'("000010000")
when std_logic_vector'("000100000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
--Count down til safe to Proceed...
if (std_logic_vector'("00000000000000000000000000000") & (m_count))>std_logic_vector'("00000000000000000000000000000001") then
m_count <= A_EXT (((std_logic_vector'("0") & (m_count)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
else
m_state <= std_logic_vector'("001000000");
m_count <= std_logic_vector'("000");
end if;
-- when std_logic_vector'("000100000")
when std_logic_vector'("001000000") =>
m_state <= std_logic_vector'("000000100");
m_addr <= A_REP(std_logic'('1'), 12);
-- precharge all if arf, else precharge csn_decode
if std_logic'(refresh_request) = '1' then
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("010"));
else
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("010"));
end if;
-- when std_logic_vector'("001000000")
when std_logic_vector'("010000000") =>
ack_refresh_request <= std_logic'('1');
m_state <= std_logic_vector'("000000100");
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & std_logic_vector'("001"));
m_count <= std_logic_vector'("011");
m_next <= std_logic_vector'("000000001");
-- when std_logic_vector'("010000000")
when std_logic_vector'("100000000") =>
m_cmd <= Std_Logic_Vector'(A_ToStdLogicVector(csn_decode) & std_logic_vector'("111"));
--if we need to ARF, bail, else spin
if std_logic'(refresh_request) = '1' then
m_state <= std_logic_vector'("000000100");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("001");
--wait for fifo to have contents
elsif std_logic'(NOT(f_empty)) = '1' then
--Are we 'pending' yet?
if std_logic'((((csn_match AND rnw_match) AND bank_match) AND row_match)) = '1' then
m_state <= A_WE_StdLogicVector((std_logic'(f_rnw) = '1'), std_logic_vector'("000001000"), std_logic_vector'("000010000"));
f_pop <= std_logic'('1');
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
else
m_state <= std_logic_vector'("000100000");
m_next <= std_logic_vector'("000000001");
m_count <= std_logic_vector'("001");
end if;
end if;
-- when std_logic_vector'("100000000")
when others =>
m_state <= m_state;
m_cmd <= std_logic_vector'("1111");
f_pop <= std_logic'('0');
oe <= std_logic'('0');
-- when others
end case; -- m_state
end if;
end process;
rd_strobe <= to_std_logic((m_cmd(2 DOWNTO 0) = std_logic_vector'("101")));
--Track RD Req's based on cas_latency w/shift reg
process (clk, reset_n)
begin
if reset_n = '0' then
rd_valid <= A_REP(std_logic'('0'), 3);
elsif clk'event and clk = '1' then
rd_valid <= (A_SLL(rd_valid,std_logic_vector'("00000000000000000000000000000001"))) OR (A_REP(std_logic'('0'), 2) & A_ToStdLogicVector(rd_strobe));
end if;
end process;
-- Register dq data.
process (clk, reset_n)
begin
if reset_n = '0' then
za_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then
za_data <= zs_dq;
end if;
end if;
end process;
-- Delay za_valid to match registered data.
process (clk, reset_n)
begin
if reset_n = '0' then
za_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
if true then
za_valid <= rd_valid(2);
end if;
end if;
end process;
cmd_code <= m_cmd(2 DOWNTO 0);
cmd_all <= m_cmd;
--vhdl renameroo for output signals
za_waitrequest <= internal_za_waitrequest;
--synthesis translate_off
txt_code <= A_WE_StdLogicVector(((cmd_code = std_logic_vector'("000"))), std_logic_vector'("010011000100110101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("001"))), std_logic_vector'("010000010101001001000110"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("010"))), std_logic_vector'("010100000101001001000101"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("011"))), std_logic_vector'("010000010100001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("100"))), std_logic_vector'("001000000101011101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("101"))), std_logic_vector'("001000000101001001000100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("110"))), std_logic_vector'("010000100101001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("111"))), std_logic_vector'("010011100100111101010000"), std_logic_vector'("010000100100000101000100")))))))));
CODE <= A_WE_StdLogicVector((std_logic'(and_reduce(((cmd_all OR std_logic_vector'("0111"))))) = '1'), std_logic_vector'("010010010100111001001000"), txt_code);
--synthesis translate_on
end europa;
trunk/VHDL/ADC_Card_FPGA/types.vhd 0 → 100644
View file @ f7ea7ecc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package types is
-- std_logic_vector types - start with V
subtype VWord is std_logic_vector(15 downto 0); -- 16 bit word
subtype VQWord is std_logic_vector(23 downto 0); -- 24 bit vector
subtype SQWord is signed(23 downto 0); -- 24bit signed to use in arithmetics
subtype SWord is signed(15 downto 0); -- 16 bit signed stuff
subtype SByte is signed(7 downto 0); -- 8 bit signed
subtype VByte is std_logic_vector(7 downto 0); -- 8 bit unsigned vector
subtype VLong is std_logic_vector(31 downto 0); -- 32bit register
-- integer types start with I
subtype IUINT8 is integer range 0 to 255; -- integer range
subtype IUINT4 is integer range 0 to 15; -- 4 bit integer
subtype IADCAddr is integer range 6 downto 0; -- ADC address to read
subtype IQWord is integer range 0 to 16777215; -- 24 bits integer
subtype ISQWord is integer range -8388608 to 8388607; -- signed 24 bits number
-- array of vectors start with AV
type AVADCMEM is array (5 downto 0) of SWord; -- ADC memory registers
type AVACCUMULATOR is array (5 downto 0) of SQWord; -- averager
type AIACCUMULATOR is array (5 downto 0) of ISQWord; -- integer averager
type AVADCOFS is array (5 downto 0) of SWord; -- ADC offsets
type SHAREDREGISTERS is array (NATURAL range <>) of VLong;
end types;
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