Skip to content

V
VME SBC A25 PCIe to VME bridge
Commit 035b97d1 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

A25_top: simplify the logic

parent e6f37e44
Hide whitespace changes
Inline Side-by-side
Showing with 68 additions and 53 deletions
hdl/top/A25_top.vhd
View file @ 035b97d1
......@@ -184,7 +184,6 @@ END COMPONENT;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_bar : std_logic_vector(6 downto 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
......@@ -373,64 +372,80 @@ pll: pll_pcie
locked => pll_locked
);
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
wbmo_0_cyc_int (0) <= '1' when wbmo_0_cyc_bar(0) = '1' AND wbmo_0.adr(17 DOWNTO 9) = "000000000" else '0';
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
wbmo_0_cyc_int (1) <= '1' when wbmo_0_cyc_bar(0) = '1' AND wbmo_0.adr(17 DOWNTO 5) = "0000000010000" else '0';
-- 16z002-01 VME regs - cycle 2 - offset 10000 - size 10000 --
wbmo_0_cyc_int (2) <= '1' when wbmo_0_cyc_bar(0) = '1' AND wbmo_0.adr(17 DOWNTO 16) = "01" else '0';
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
wbmo_0_cyc_int (3) <= '1' when wbmo_0_cyc_bar(0) = '1' AND wbmo_0.adr(17 DOWNTO 16) = "10" else '0';
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
wbmo_0_cyc_int (4) <= '1' when wbmo_0_cyc_bar(0) = '1' AND wbmo_0.adr(17 DOWNTO 16) = "11" else '0';
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
wbmo_0_cyc_int (5) <= wbmo_0_cyc_bar (1);
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
wbmo_0_cyc_int (6) <= '1' when wbmo_0_cyc_bar(2) = '1' AND wbmo_0.adr(24) = '0' else '0';
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
wbmo_0_cyc_int (7) <= '1' when wbmo_0_cyc_bar(2) = '1' AND wbmo_0.adr(24) = '1' else '0';
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
wbmo_0_cyc_int (8) <= wbmo_0_cyc_bar (3);
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
wbmo_0_cyc_int (9) <= wbmo_0_cyc_bar (4);
-- +-Module Name--------------+-dst-+---offset-+------size-+-bar-+
-- | Chameleon Table | cam | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | flh | 200 | 20 | 0 |
-- |16z002-01 VME REGS | vme | 10000 | 200 | 0 |
-- |16z002-01 VME IACK | vme | 10200 | 200 | 0 |
-- |16z002-01 VME A16D16 | vme | 20000 | 1_0000 | 0 |
-- |16z002-01 VME A16D32 | vme | 30000 | 1_0000 | 0 |
-- | 16z002-01 VME SRAM | ram | 0 | 10_0000 | 1 |
-- |16z002-01 VME A24D16 | vme | 0 | 100_0000 | 2 |
-- |16z002-01 VME A24D32 | vme | 1000000 | 100_0000 | 2 |
-- | 16z002-01 VME A32 | vme | 0 | 2000_0000 | 3 |
-- |16z002-01 VME CR/CSR | vme | 0 | 100_0000 | 4 |
-- +--------------------------+-----+----------+-----------+-----+
process (wbmo_0_cyc_bar, wbmo_0)
begin
wbmo_0_cyc <= "0000";
wbmo_0.tga(6 DOWNTO 0) <= (others => 'X');
if wbmo_0_cyc_bar(0) = '1' then
case wbmo_0.adr(17 DOWNTO 16) is
when "00" =>
if wbmo_0.adr(15 DOWNTO 9) = "0000000" then
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
wbmo_0_cyc <= "0001";
elsif wbmo_0.adr(15 DOWNTO 5) = "00000010000" then
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
wbmo_0_cyc <= "0010";
end if;
when "01" =>
wbmo_0_cyc <= "0100";
if wbmo_0.adr(8) = '1' then
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_IACK;
else
-- 16z002-01 VME regs - cycle 2 - offset 10000 - size 10000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_REGS;
end if;
when "10" =>
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D16;
when "11" =>
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D32;
when others =>
null;
end case;
elsif wbmo_0_cyc_bar (1) = '1' then
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
wbmo_0_cyc <= "1000";
elsif wbmo_0_cyc_bar (2) = '1' then
wbmo_0_cyc <= "0100";
if wbmo_0.adr(24) = '0' then
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D16;
else
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D32;
end if;
elsif wbmo_0_cyc_bar (3) = '1' then
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A32D32;
elsif wbmo_0_cyc_bar (4) = '1' then
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_CRCSR;
end if;
end process;
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
"0100" WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 200 | 0 |
"0100" WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
"1000" WHEN wbmo_0_cyc_int(5) = '1' ELSE -- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
"0100" WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(8) = '1' ELSE -- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
"0100" WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CR/CSR | 9 | 0 | 01000000 | 4 |
"0000"; -- +--------------------------+-----+----------+----------+-----+
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
wbmo_0.tga(6 DOWNTO 0) <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
CONST_VME_A24D16 WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
CONST_VME_A16D16 WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
CONST_VME_A16D32 WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
CONST_VME_IACK WHEN wbmo_0_cyc_int(2) = '1'
AND wbmo_0.adr(8) = '1' ELSE -- |16z002-01 VME IACK | 2 | 10100 | 10 | 0 |
CONST_VME_REGS WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 100 | 0 |
CONST_VME_A32D32 WHEN wbmo_0_cyc_int(8) = '1' ELSE -- |16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
CONST_VME_A24D32 WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: entity work.ip_16z091_01_top
GENERIC MAP (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment