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VME SBC A25 PCIe to VME bridge
Commit 0897e59c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '11-hdl-simplify' into 'master' 

Resolve "HDL: simplify"

Closes #11

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!7
parents 5c7ee107 523c14ee
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Showing with 52 additions and 2901 deletions
hdl/16z091-01_src/Manifest.py
View file @ 0897e59c
......@@ -20,7 +20,6 @@ files = [
"Source/tx_ctrl.vhd",
"Source/tx_module.vhd",
"Source/tx_put_data.vhd",
# "Source/z091_01_wb_adr_dec.vhd",
"Source/z091_01_wb_master.vhd",
"Source/z091_01_wb_slave.vhd",
"Synthesis/z91_01_tmg_con.sdc",
......
hdl/16z091-01_src/README.rst
View file @ 0897e59c
......@@ -17,126 +17,6 @@ architecture of this IP core can be found in
Integration advice
------------------
Wishbone address decoder
~~~~~~~~~~~~~~~~~~~~~~~~
As you might need several PCIe instances the 16z091-01 IP core supports the
usage of configurations. This means that you can use one address decoding file,
z091_01_wb_adr_dec.vhd, which contains several architectures, one for each PCIe
instance. In your top-level file you generate a configuration statement that
combines the PCIe instances with the correct z091_01_wb_adr_dec.vhd
architecture.
Example:
--------
16z091-01 Wishbone address decoder (z091_01_wb_adr_dec.vhd):
entity z091_01_wb_adr_dec is
...
end entity z091_01_wb_adr_dec;
architecture xy of z091_01_wb_adr_dec is
<what ever>
end architecture xy;
Wishbone address decoder generated by chameleon table (wb_adr_dec.vhd):
Comment out the ENTITY of wb_adr_dec.vhd
--entity wb_adr_dec is
-- ...
--end entity wb_adr_dec;
Change the ENTITY Name in the ARCHITECTURE (from wb_adr_dec to z091_01_wb_adr_dec) and define your ARCHITECTURE name (for example: a21_arch)
architecture a21_arch of z091_01_wb_adr_dec is
<content generated from chameleon tool>
end architecture a21_arch;
A21 top file (a21_top.vhd):
entity a21_top is
...
end entity;
architecture a21_top_arch of a21_top is
<16z091-01 component declaration>
<other components, functions, signals etc.>
begin
...
pcie : ip_16z091_01_top
generic map(...)
port map(...);
<other component instantiations>
end architecture a21_top_arch;
CONFIGURATION:
NOTE: PCIe module hierarchy
-ip_16z091_01_top
-ip_16z091_01
-z091_01_wb_master
->(z091_01_wb_adr_dec is located in z091_01_wb_master) => therefore 4 CONFIGURATIONS are needed
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a21_arch); <-- choose the correct architecture for the address decoder here
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION a21_cfg OF A21_top IS
FOR A21_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg; <-- map the PCIe top-level instance to the correct address
END FOR; decoding configuration here
END FOR;
END CONFIGURATION a21_cfg;
NOTE that if you want to simulate this with ModelSim you need to specify the configuration instead of the entity for vsim:
vsim work.a21_cfg (can also be done by a CONFIGURATION in your test bench)
A21 test bench (tb_A21_top.vhd):
ENTITY tb_A21_top IS
END tb_A21_top;
ARCHITECTURE tb_A21_top_arch OF tb_A21_top IS
<A21_top component declaration>
<other components, functions, signals etc.>
BEGIN
...
dut: A21_top
generic map(...)
port map(...);
<other component instantiations>
END ARCHITECTURE tb_A21_top_arch;
CONFIGURATION:
CONFIGURATION tb_A21_top_conf of tb_A21_top IS
FOR tb_A21_top_arch
FOR dut : A21_top
USE CONFIGURATION work.a21_cfg;
END FOR;
END FOR;
END CONFIGURATION tb_A21_top_conf;
+------------------+
| Generic settings |
+------------------+
......
hdl/16z091-01_src/Source/init.vhd
View file @ 0897e59c
......@@ -87,10 +87,6 @@ signal ctl_bus_qqq : std_logic;
signal ctl_msi_q : std_logic;
signal ctl_msi_qq : std_logic;
signal ctl_msi_qqq : std_logic;
signal bus_dev_func_int : std_logic_vector(15 downto 0);
signal max_read_int : std_logic_vector(2 downto 0);
signal max_payload_int : std_logic_vector(2 downto 0);
signal cfg_msicsr_int : std_logic_vector(15 downto 0);
signal sample : std_logic;
signal get_sample : std_logic;
signal tl_cfg_ctl_wr_q : std_logic;
......
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @ 0897e59c
This diff is collapsed.
hdl/16z091-01_src/Source/rx_module.vhd
View file @ 0897e59c
......@@ -107,87 +107,6 @@ architecture rx_module_arch of rx_module is
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component rx_ctrl
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
sop_q_i : in std_logic;
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end component;
component rx_get_data
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
......@@ -241,7 +160,7 @@ begin
-- | process section
-- +----------------------------------------------------------------------------
-- registers to remembe the type and fmt for the last received TLP
process(rst, clk)
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
......@@ -252,7 +171,7 @@ begin
end if;
end process;
process(rst, clk)
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
......@@ -334,7 +253,7 @@ begin
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
rx_ctrl_comp : rx_ctrl
rx_ctrl_comp : entity work.rx_ctrl
port map(
clk_i => clk,
rst_i => rst,
......@@ -360,7 +279,7 @@ begin
len_cntr_val_i => int_len_cntr_val
);
rx_get_data_comp : rx_get_data
rx_get_data_comp : entity work.rx_get_data
port map(
clk_i => clk,
rst_i => rst,
......@@ -389,7 +308,7 @@ begin
);
c_fifo_comp : generic_dcfifo_mixedw
c_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
......@@ -410,7 +329,7 @@ begin
wrfull => int_c_wr_full,
wrusedw => int_rx_wrusedw_c);
wr_fifo_comp : generic_dcfifo_mixedw
wr_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
......
hdl/16z091-01_src/Source/tx_module.vhd
View file @ 0897e59c
......@@ -157,159 +157,10 @@ signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c_out : std_logic_vector (9 downto 0);
signal tx_wrusedw_w_out : std_logic_vector (9 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component tx_ctrl
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic;
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0);
send_addr : out std_logic_vector(31 downto 0);
payload_loop : out std_logic;
first_last_full : out std_logic_vector(1 downto 0);
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end component;
component tx_put_data
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0);
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end component;
component tx_compl_timeout
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- RxModule
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
tx_ctrl_comp : tx_ctrl
tx_ctrl_comp : entity work.tx_ctrl
port map(
clk => clk,
rst => rst,
......@@ -371,7 +222,7 @@ begin
max_payload => max_payload
);
tx_put_data_comp : tx_put_data
tx_put_data_comp : entity work.tx_put_data
port map(
clk => clk,
rst => rst,
......@@ -408,7 +259,7 @@ begin
orig_addr => orig_addr_int
);
tx_compl_timeout_comp : tx_compl_timeout
tx_compl_timeout_comp : entity work.tx_compl_timeout
generic map(
CLOCK_TIME => 8 ns, -- clock cycle time
TIMEOUT_TIME => 25
......@@ -431,7 +282,7 @@ begin
);
------------------------------------------------
tx_c_header_fifo : generic_dcfifo_mixedw
tx_c_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
......@@ -452,7 +303,7 @@ begin
wrfull => tx_fifo_c_head_full,
wrusedw => open);
tx_wr_header_fifo : generic_dcfifo_mixedw
tx_wr_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
......@@ -474,7 +325,7 @@ begin
wrusedw => tx_fifo_wr_head_usedw);
------------------------------------------------
tx_c_data_fifo : generic_dcfifo_mixedw
tx_c_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
......@@ -495,7 +346,7 @@ begin
wrfull => tx_fifo_c_data_full,
wrusedw => tx_wrusedw_c);
tx_w_data_fifo : generic_dcfifo_mixedw
tx_w_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
......
hdl/16z091-01_src/Source/z091_01_wb_adr_dec.vhd deleted 100644 → 0
View file @ 5c7ee107
-- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : 16z091-01 specific Wishbone bus
-- Project :
-------------------------------------------------------------------------------
-- File : z091_01_wb_adr_dec.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2012-12-19
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Special address decoder that can be used with configurations
-- to enable multiple instances of the 16z091-01 IP core
-- that can have their unique address decoder
-------------------------------------------------------------------------------
-- Hierarchy:
-- ip_16z091_01_top
-- ip_16z091_01
-- Hard_IP
-- * z091_01_wb_adr_dec
--
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity z091_01_wb_adr_dec is
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port(
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end z091_01_wb_adr_dec;
-------------------------------------------------------------------------
-- sim_test_arch implements a sample pcie address decoder to enable
-- the simulation iram models
-------------------------------------------------------------------------
architecture sim_test_arch of z091_01_wb_adr_dec is
signal zero : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
zero <= (others => '0');
process(wbm_adr_o_q, pci_cyc_i, zero)
variable wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
wbm_cyc_o_int := (others => '0');
-- iram 1 - cycle 0 - offset 00000000 - size 1000 --
if pci_cyc_i(0) = '1' then
wbm_cyc_o_int(0) := '1';
else
wbm_cyc_o_int(0) := '0';
end if;
-- iram 2 - cycle 1 - offset 00000000 - size 2000 --
if pci_cyc_i(1) = '1' then
wbm_cyc_o_int(1) := '1';
else
wbm_cyc_o_int(1) := '0';
end if;
-- iram 2 - cycle 2 - offset 00000000 - size 1000 --
if pci_cyc_i(2) = '1' then
wbm_cyc_o_int(2) := '1';
else
wbm_cyc_o_int(2) := '0';
end if;
--if pci_cyc_i /= zero and wbm_cyc_o_int = "000" then
if pci_cyc_i /= "0000000" and wbm_cyc_o_int = zero then
wbm_cyc_o_int(0) := '1';
end if;
wbm_cyc_o <= wbm_cyc_o_int;
end process;
end sim_test_arch;
hdl/16z091-01_src/Source/z091_01_wb_master.vhd
View file @ 0897e59c
......@@ -101,20 +101,6 @@ end entity z091_01_wb_master;
-- ****************************************************************************
architecture z091_01_wb_master_arch of z091_01_wb_master is
component z091_01_wb_adr_dec
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port (
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end component;
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREPARE_FIFO, IDLE, GET_HEADER_0, GET_HEADER_1, GET_HEADER_2, GET_WR_DATA, START_TRANS,
......@@ -170,7 +156,7 @@ signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
z091_01_wb_adr_dec_comp : entity work.z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
......@@ -635,7 +621,7 @@ begin
end if;
end process fsm_out;
-------------------------------------------------------------------------------
data_path : process(wb_clk, wb_rst, wbm_ack)
data_path : process(wb_clk, wb_rst)
begin
if(wb_rst = '1') then
......@@ -658,8 +644,7 @@ begin
bar_dec_int <= (others => '0');
io_wr_int <= '0';
else
if(wb_clk'event and wb_clk = '1') then
elsif(wb_clk'event and wb_clk = '1') then
if(decode_header = "01") then
-- decode which BAR was hit
......@@ -782,7 +767,6 @@ begin
else
tx_fifo_c_head_in <= (others => '0');
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
......
hdl/syn/Manifest.py
View file @ 0897e59c
......@@ -20,11 +20,6 @@ quartus_preflow = "scripts/quartus_preflow.tcl"
quartus_postmodule = "scripts/gen_programming_files.tcl"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../dependencies"
files = [
"A25_top.sdc",
]
......
hdl/top/A25_top.vhd
View file @ 0897e59c
This diff is collapsed.
hdl/top/Manifest.py
View file @ 0897e59c
......@@ -2,6 +2,11 @@
#
# SPDX-License-Identifier: CERN-OHL-S-2.0+
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../dependencies"
modules = {
"local" : [
"../16z000-00_src/",
......@@ -19,7 +24,6 @@ modules = {
files = [
"A25_top.vhd",
"sram.vhd",
"wb_adr_dec.vhd",
"wb_bus.vhd",
"wb_pkg.vhd",
"z091_01_wb_adr_dec.vhd",
......
hdl/top/wb_adr_dec.vhd deleted 100644 → 0
View file @ 5c7ee107
-- SPDX-FileCopyrightText: 2017, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Adress decoder for whisbone bus
-- Project : <A025-00>
---------------------------------------------------------------
-- File : wb_adr_dec.vhd
-- Author : Chameleon_V2.exe
-- Email : michael.ernst@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2017/6/1 - 12:2:21
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-- Simulator :
-- Synthesis :
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-- Description : Created with Chameleon_V2.exe
-- v1.18
-- 2016-06-14
--
--
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 10 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 200 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- | 16z002-01 VME CR/CSR | 9 | 0 | 1000000 | 4 |
-- +-------------------------------+-----+----------+----------+-----+
--
--
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-- Hierarchy:
--
--
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-- History
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-- $Revision: $
--
-- $Log: $
--
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
ENTITY wb_adr_dec IS
PORT (
pci_cyc_i : IN std_logic_vector(4 DOWNTO 0);
wbm_adr_o_q : IN std_logic_vector(31 DOWNTO 2);
wbm_cyc_o : OUT std_logic_vector(9 DOWNTO 0)
);
END wb_adr_dec;
ARCHITECTURE wb_adr_dec_arch OF wb_adr_dec IS
SIGNAL zero : std_logic_vector(4 DOWNTO 0);
BEGIN
zero <= (OTHERS => '0');
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(9 DOWNTO 0);
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 10 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 4) = "00000000100000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "010000000" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CR/CSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF pci_cyc_i /= zero AND wbm_cyc_o_int = "0000000000" THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
END wb_adr_dec_arch;
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