Add and use internal sram

2e4162ad · Tristan Gingold · Tristan Gingold · f489f076 · 2e4162ad · 2e4162ad
Commit 2e4162ad authored Dec 13, 2023 by Tristan Gingold Committed by Tristan Gingold Dec 13, 2023
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A25_top.vhd hdl/top/A25_top.vhd +3 -0

sram.vhd hdl/top/sram.vhd +48 -2

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--- a/hdl/top/A25_top.vhd
+++ b/hdl/top/A25_top.vhd
@@ -1185,6 +1185,9 @@ END A25_top_arch;
       FOR pcie : ip_16z091_01_top          
         USE CONFIGURATION work.ip_16z091_01_top_cfg;        
       END FOR;                                                  
+       for srami: sram
+         use entity work.sram(internal);
+       end for;
     END FOR;
   END CONFIGURATION top_cfg; 
 
--- a/hdl/top/sram.vhd
+++ b/hdl/top/sram.vhd
@@ -259,7 +259,53 @@ sram_fsm : PROCESS (clk66, rst)
        END CASE;
     END IF;
  END PROCESS sram_fsm;
-  
+END sram_arch;

+architecture internal of sram is
+   signal rst_n : std_logic;
+   signal we, ack : std_logic;
+begin
+   --  External sram is not used
+   bwn <= '1';
+   bwan <= '1';
+   bwbn <= '1';
+   roen <= '1';
+   adscn <= '1';
+   rd_oe <= '0';

-END sram_arch;
+   rst_n <= not rst;
+   we <= cyc_i and stb_i and we_i;
+
+   inst_sram: entity work.generic_spram
+     generic map (
+       g_data_width => 32,
+       g_size => 1024,
+       g_with_byte_enable => True,
+       g_addr_conflict_resolution => "dont_care",
+       g_init_file => open,
+       g_implementation_hint => open
+     )
+     port map (
+       rst_n_i => rst_n,
+       clk_i => clk66,
+       bwe_i => sel_i,
+       we_i => we,
+       a_i => adr_i(11 downto 2),
+       d_i => dat_i,
+       q_o => dat_o
+     );
+
+  process (clk66) is
+  begin
+    if rising_edge(clk66) then
+      if rst_n = '0' then
+        ack <= '0';
+      else
+         --  One cycle ack.
+        ack <= cyc_i and stb_i and not ack;
+      end if;
+    end if;
+  end process;
+
+  ack_o <= ack;
+end internal;