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VME SBC A25 PCIe to VME bridge
Commit 7b3abf92 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '14-hdl-use-fifo-from-general-cores-part-2' into 'master' 

Resolve "HDL: use fifo from general-cores (part 2)"

Closes #14

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!10
parents 91bfd3f8 68069660
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general-cores @ 3c636a53
Subproject commit 225dd70e4cf4f93954414916f57ef1366e12e13b
Subproject commit 3c636a53f7c6605fbb8c66093a3dcb08132a572c
hdl/16z091-01_src/Source/generic_dcfifo_mixedw.vhd
View file @ 7b3abf92
......@@ -19,9 +19,6 @@
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity generic_dcfifo_mixedw is
generic (
g_device_family : string := "Cyclone IV GX";
......@@ -45,37 +42,28 @@ entity generic_dcfifo_mixedw is
end generic_dcfifo_mixedw;
architecture syn of generic_dcfifo_mixedw is
signal rst_n_a : std_logic;
begin
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map(
intended_device_family => g_device_family,
lpm_numwords => g_fifo_depth, -- value assigned must comply with this equation
-- 2^(LPM_WIDTHU -1) < LPM_NUMWORDS <= 2^(LPM_WIDTHU)
lpm_showahead => g_showahead, -- off: normal mode, on: show ahead mode
lpm_type => "dcfifo_mixed_widths", -- DON'T CHANGE / FIFO type
lpm_width => g_data_width, -- width for _data_ port
lpm_widthu => g_data_widthu, -- size of write usedw
lpm_width_r => g_q_width, -- width for _q_ port
lpm_widthu_r => g_q_widthu, -- size of read usedw
overflow_checking => "ON", -- DON'T CHANGE / protection circuit for overflow checking
rdsync_delaypipe => 4, -- nbr of read synchronization stages, internally reduced by 2 => 2 stages
read_aclr_synch => "OFF",
underflow_checking => "ON", -- DON'T CHANGE / protection circuit for underflow checking
use_eab => "ON", -- off: FIFO implemented in logic, on: FIFO implemented using RAM blocks
write_aclr_synch => "OFF",
wrsync_delaypipe => 4 -- nbr of write synchronization stages, internally reduced by 2 => 2 stages
)
port map (
aclr => aclr,
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => q,
rdempty => rdempty,
wrfull => wrfull,
wrusedw => wrusedw);
rst_n_a <= not aclr;
inst_fifo: entity work.generic_async_fifo_mixedw
generic map (
g_wr_width => g_data_width,
g_rd_width => g_q_width,
g_size => g_fifo_depth,
g_show_ahead => g_showahead = "ON",
g_memory_implementation_hint => open
)
port map (
rst_n_a_i => rst_n_a,
clk_wr_i => wrclk,
d_i => data,
we_i => wrreq,
wr_full_o => wrfull,
wr_count_o => wrusedw,
clk_rd_i => rdclk,
q_o => q,
rd_i => rdreq,
rd_empty_o => rdempty,
rd_count_o => open
);
end syn;
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @ 7b3abf92
......@@ -215,7 +215,7 @@ signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_w_data_full_int : std_logic;
signal tx_fifo_w_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(4 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(6 downto 0);
-- error:
signal ecrc_err_wb_int : std_logic;
......
hdl/16z091-01_src/Source/rx_module.vhd
View file @ 7b3abf92
......@@ -117,11 +117,11 @@ signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
......@@ -295,7 +295,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "ON")
......@@ -317,7 +317,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "OFF")
......
hdl/16z091-01_src/Source/tx_module.vhd
View file @ 7b3abf92
......@@ -99,7 +99,7 @@ entity tx_module is
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(4 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(6 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
......@@ -153,8 +153,8 @@ signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_empty_int : std_logic;
signal tx_fifo_w_data_out_int : std_logic_vector(63 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
begin
-- instanciate components -----------------------------------------------------
......@@ -285,7 +285,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -306,7 +306,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -328,7 +328,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -349,7 +349,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -365,7 +365,7 @@ begin
wrfull => tx_fifo_w_data_full,
wrusedw => tx_wrusedw_w);
-------------------------------------------------------------------------------
tx_fifo_c_data_usedw <= "000" & tx_wrusedw_c(6 downto 0);
tx_fifo_w_data_usedw <= "000" & tx_wrusedw_w(6 downto 0);
tx_fifo_c_data_usedw <= "0" & tx_wrusedw_c(8 downto 0);
tx_fifo_w_data_usedw <= "0" & tx_wrusedw_w(8 downto 0);
-------------------------------------------------------------------------------
end architecture tx_module_arch;
hdl/16z091-01_src/Source/z091_01_wb_slave.vhd
View file @ 7b3abf92
......@@ -87,7 +87,7 @@ entity z091_01_wb_slave is
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(4 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(6 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
......
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