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VME SBC A25 PCIe to VME bridge
Commit 9c977984 authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
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Remove unused pcie address decoder

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hdl/16z091-01_src/README.rst
View file @ 9c977984
......@@ -17,126 +17,6 @@ architecture of this IP core can be found in
Integration advice
------------------
Wishbone address decoder
~~~~~~~~~~~~~~~~~~~~~~~~
As you might need several PCIe instances the 16z091-01 IP core supports the
usage of configurations. This means that you can use one address decoding file,
z091_01_wb_adr_dec.vhd, which contains several architectures, one for each PCIe
instance. In your top-level file you generate a configuration statement that
combines the PCIe instances with the correct z091_01_wb_adr_dec.vhd
architecture.
Example:
--------
16z091-01 Wishbone address decoder (z091_01_wb_adr_dec.vhd):
entity z091_01_wb_adr_dec is
...
end entity z091_01_wb_adr_dec;
architecture xy of z091_01_wb_adr_dec is
<what ever>
end architecture xy;
Wishbone address decoder generated by chameleon table (wb_adr_dec.vhd):
Comment out the ENTITY of wb_adr_dec.vhd
--entity wb_adr_dec is
-- ...
--end entity wb_adr_dec;
Change the ENTITY Name in the ARCHITECTURE (from wb_adr_dec to z091_01_wb_adr_dec) and define your ARCHITECTURE name (for example: a21_arch)
architecture a21_arch of z091_01_wb_adr_dec is
<content generated from chameleon tool>
end architecture a21_arch;
A21 top file (a21_top.vhd):
entity a21_top is
...
end entity;
architecture a21_top_arch of a21_top is
<16z091-01 component declaration>
<other components, functions, signals etc.>
begin
...
pcie : ip_16z091_01_top
generic map(...)
port map(...);
<other component instantiations>
end architecture a21_top_arch;
CONFIGURATION:
NOTE: PCIe module hierarchy
-ip_16z091_01_top
-ip_16z091_01
-z091_01_wb_master
->(z091_01_wb_adr_dec is located in z091_01_wb_master) => therefore 4 CONFIGURATIONS are needed
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a21_arch); <-- choose the correct architecture for the address decoder here
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION a21_cfg OF A21_top IS
FOR A21_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg; <-- map the PCIe top-level instance to the correct address
END FOR; decoding configuration here
END FOR;
END CONFIGURATION a21_cfg;
NOTE that if you want to simulate this with ModelSim you need to specify the configuration instead of the entity for vsim:
vsim work.a21_cfg (can also be done by a CONFIGURATION in your test bench)
A21 test bench (tb_A21_top.vhd):
ENTITY tb_A21_top IS
END tb_A21_top;
ARCHITECTURE tb_A21_top_arch OF tb_A21_top IS
<A21_top component declaration>
<other components, functions, signals etc.>
BEGIN
...
dut: A21_top
generic map(...)
port map(...);
<other component instantiations>
END ARCHITECTURE tb_A21_top_arch;
CONFIGURATION:
CONFIGURATION tb_A21_top_conf of tb_A21_top IS
FOR tb_A21_top_arch
FOR dut : A21_top
USE CONFIGURATION work.a21_cfg;
END FOR;
END FOR;
END CONFIGURATION tb_A21_top_conf;
+------------------+
| Generic settings |
+------------------+
......
hdl/top/wb_adr_dec.vhd deleted 100644 → 0
View file @ b0a3ddc9
-- SPDX-FileCopyrightText: 2017, MEN Mikroelektronik Nuernberg GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
---------------------------------------------------------------
-- Title : Adress decoder for whisbone bus
-- Project : <A025-00>
---------------------------------------------------------------
-- File : wb_adr_dec.vhd
-- Author : Chameleon_V2.exe
-- Email : michael.ernst@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 2017/6/1 - 12:2:21
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description : Created with Chameleon_V2.exe
-- v1.18
-- 2016-06-14
--
--
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 10 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 200 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- | 16z002-01 VME CR/CSR | 9 | 0 | 1000000 | 4 |
-- +-------------------------------+-----+----------+----------+-----+
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
ENTITY wb_adr_dec IS
PORT (
pci_cyc_i : IN std_logic_vector(4 DOWNTO 0);
wbm_adr_o_q : IN std_logic_vector(31 DOWNTO 2);
wbm_cyc_o : OUT std_logic_vector(9 DOWNTO 0)
);
END wb_adr_dec;
ARCHITECTURE wb_adr_dec_arch OF wb_adr_dec IS
SIGNAL zero : std_logic_vector(4 DOWNTO 0);
BEGIN
zero <= (OTHERS => '0');
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(9 DOWNTO 0);
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 10 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 4) = "00000000100000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "010000000" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CR/CSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF pci_cyc_i /= zero AND wbm_cyc_o_int = "0000000000" THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
END wb_adr_dec_arch;
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