Skip to content

V
VME SBC A25 PCIe to VME bridge
Commit bcfeba9b authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
Browse files
Options

Adjust dcfifo widths

parent 27511fd2
Hide whitespace changes
Inline Side-by-side
Showing with 15 additions and 15 deletions
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @ bcfeba9b
......@@ -215,7 +215,7 @@ signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_in_int : std_logic_vector(31 downto 0);
signal tx_fifo_w_data_full_int : std_logic;
signal tx_fifo_w_data_usedw_int : std_logic_vector(9 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(4 downto 0);
signal tx_fifo_wr_head_usedw_int : std_logic_vector(6 downto 0);
-- error:
signal ecrc_err_wb_int : std_logic;
......
hdl/16z091-01_src/Source/rx_module.vhd
View file @ bcfeba9b
......@@ -117,11 +117,11 @@ signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
......@@ -295,7 +295,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "ON")
......@@ -317,7 +317,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_data_widthu => RX_LPM_WIDTHU+1,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "OFF")
......
hdl/16z091-01_src/Source/tx_module.vhd
View file @ bcfeba9b
......@@ -99,7 +99,7 @@ entity tx_module is
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(4 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(6 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
......@@ -153,8 +153,8 @@ signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_empty_int : std_logic;
signal tx_fifo_w_data_out_int : std_logic_vector(63 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU+1 downto 0);
begin
-- instanciate components -----------------------------------------------------
......@@ -285,7 +285,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -306,7 +306,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_data_widthu => TX_HEADER_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -328,7 +328,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -349,7 +349,7 @@ begin
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_data_widthu => TX_DATA_LPM_WIDTHU+2,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
......@@ -365,7 +365,7 @@ begin
wrfull => tx_fifo_w_data_full,
wrusedw => tx_wrusedw_w);
-------------------------------------------------------------------------------
tx_fifo_c_data_usedw <= "000" & tx_wrusedw_c(6 downto 0);
tx_fifo_w_data_usedw <= "000" & tx_wrusedw_w(6 downto 0);
tx_fifo_c_data_usedw <= "0" & tx_wrusedw_c(8 downto 0);
tx_fifo_w_data_usedw <= "0" & tx_wrusedw_w(8 downto 0);
-------------------------------------------------------------------------------
end architecture tx_module_arch;
hdl/16z091-01_src/Source/z091_01_wb_slave.vhd
View file @ bcfeba9b
......@@ -87,7 +87,7 @@ entity z091_01_wb_slave is
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(4 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(6 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment