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VME SBC A25 PCIe to VME bridge
Commit f96ca368 authored by Tristan Gingold's avatar Tristan Gingold
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ip_16z091: remove address decoding 

simply export selected BAR as cyc signals,
move address decoding in A25_top.vhd
parent 9b9a944e
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Showing with 22 additions and 84 deletions
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @ f96ca368
......@@ -49,7 +49,6 @@ use work.fpga_pkg_2.all;
entity ip_16z091_01 is
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
......@@ -120,15 +119,13 @@ entity ip_16z091_01 is
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_cyc_bar_o : out std_logic_vector(6 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
......@@ -286,7 +283,6 @@ begin
wb_master_comp : entity work.z091_01_wb_master
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
SUSPEND_FIFO_ACCESS => WBM_SUSPEND_FIFO_ACCESS,
RESUME_FIFO_ACCESS => WBM_RESUME_FIFO_ACCESS
)
......@@ -314,15 +310,13 @@ begin
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => wbm_cyc,
wbm_cyc_o => wbm_cyc_o,
wbm_cyc_bar_o => wbm_cyc_bar_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => wb_bar_dec,
-- error
ecrc_err_in => ecrc_err_wb_int,
......
hdl/16z091-01_src/Source/ip_16z091_01_top.vhd
View file @ f96ca368
......@@ -45,8 +45,6 @@ entity ip_16z091_01_top is
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
......@@ -79,7 +77,7 @@ entity ip_16z091_01_top is
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_cyc_bar_o : out std_logic_vector(6 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
......@@ -191,9 +189,6 @@ signal dlup_exit : std_logic;
signal rst_cwh : std_logic;
signal rst_cwh_cnt : std_logic_vector (1 downto 0);
--signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
--signal wbm_cyc_o_int_d : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0); --mwawrik: delayed cycle causes problems
signal test_in_int : std_logic_vector(39 downto 0);
signal pipe_mode_int : std_logic;
......@@ -457,18 +452,6 @@ COMPONENT Hard_IP_x4 is
);
end COMPONENT Hard_IP_x4;
--component z091_01_wb_adr_dec
-- generic(
-- NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
-- );
-- port (
-- pci_cyc_i : in std_logic_vector(6 downto 0);
-- wbm_adr_o_q : in std_logic_vector(31 downto 2);
--
-- wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
-- );
--end component;
component alt_reconf
port(
reconfig_clk : in std_logic;
......@@ -532,7 +515,6 @@ begin
ip_16z091_01_comp : entity work.ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
......@@ -602,15 +584,13 @@ begin
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => OPEN,
wbm_cyc_o => wbm_cyc_o,
wbm_cyc_bar_o => wbm_cyc_bar_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => int_bar_hit,
-- Wishbone slave
wbs_cyc => wbs_cyc,
......@@ -898,31 +878,6 @@ begin
tx_3 <= '1';
end generate gen_x1;
--z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
-- generic map(
-- NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
-- )
-- port map(
-- pci_cyc_i => int_bar_hit,
-- wbm_adr_o_q => wbm_adr_int(31 downto 2),
--
-- wbm_cyc_o => wbm_cyc_o_int
-- );
--mwawrik: this process is responsible for the problem, that the cycle is longer active than acknowledge
--cyc_o : process(wb_rst, wb_clk)
--begin
-- if wb_rst = '1' then
-- wbm_cyc_o_int_d <= (others => '0');
-- elsif wb_clk'event and wb_clk = '1' then
-- if wbm_ack = '1' then
-- wbm_cyc_o_int_d <= (others=>'0');
-- else
-- wbm_cyc_o_int_d <= wbm_cyc_o_int;
-- end if;
-- end if;
--end process cyc_o;
------------------------------------------------------------------------------
alt_reconf_comp : alt_reconf
port map(
reconfig_clk => clk_50,
......
hdl/16z091-01_src/Source/z091_01_wb_master.vhd
View file @ f96ca368
......@@ -53,7 +53,6 @@ use work.src_utils_pkg.all;
entity z091_01_wb_master is
generic(
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
......@@ -81,15 +80,13 @@ entity z091_01_wb_master is
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_cyc_bar_o : out std_logic_vector(6 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic; -- wbm_tga(0)=1 if ECRC error occured
--wb_bar_dec : out std_logic_vector(6 downto 0); -- decoded BAR for wb_adr_dec.vhd mwawrik: no longer necessary
-- error
ecrc_err_in : in std_logic; -- input from error module
......@@ -151,25 +148,10 @@ signal wb_bar_dec_int_d : std_logic_vector(6 downto 0);
signal ecrc_err_int : std_logic;
signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
-------------------------------------------------------------------------------
begin
z091_01_wb_adr_dec_comp : entity work.z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
port map(
pci_cyc_i => wb_bar_dec_int,
wbm_adr_o_q => addr_int(31 downto 2),
wbm_cyc_o => wbm_cyc_o_int
);
wb_bar_dec_int <= bar_dec_int when (state = START_TRANS) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B
and tx_fifo_c_data_full = '0' and goto_start = '0') else
......@@ -179,8 +161,6 @@ begin
else
wb_bar_dec_int_d;
--wb_bar_dec <= wb_bar_dec_int_d; --mwawrik: no longer necessary because out-pin wb_bar_dec removed
ecrc_err_int <= '0' when wb_rst = '1' else
'0' when state = TRANSMIT else
'1' when state /= TRANSMIT and ecrc_err_in = '1';
......@@ -309,7 +289,7 @@ begin
tx_fifo_c_data_clr <= '1';
tx_fifo_c_head_clr <= '1';
wbm_stb <= '0';
wbm_cyc_o <= (others => '0');
wbm_cyc_bar_o <= (others => '0');
wbm_we <= '0';
wbm_sel <= (others => '0');
wbm_adr <= (others => '0');
......@@ -438,17 +418,17 @@ begin
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb > ZERO_11B) ) then
wbm_cti <= "010";
wbm_cyc_o <= wbm_cyc_o_int;
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif((state = START_TRANS and suspend = '0' and length_int = ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ONE_11B or (tx_fifo_c_data_usedw = SUSPEND_FIFO_ACCESS and
wr_en_int = '0'))) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb <= ZERO_11B) ) then
wbm_cti <= "111";
wbm_cyc_o <= wbm_cyc_o_int;
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')) ) then
wbm_cti <= "000";
wbm_cyc_o <= (OTHERS=>'0');
wbm_cyc_bar_o <= (OTHERS=>'0');
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
......
hdl/top/A25_top.vhd
View file @ f96ca368
......@@ -123,8 +123,6 @@ END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT pll_pcie
PORT
(
......@@ -185,6 +183,7 @@ END COMPONENT;
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_bar : std_logic_vector(6 downto 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
......@@ -374,6 +373,17 @@ pll: pll_pcie
locked => pll_locked
);
z091_01_wb_adr_dec_comp : entity work.z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
port map(
pci_cyc_i => wbmo_0_cyc_bar,
wbm_adr_o_q => wbmo_0.adr(31 downto 2),
wbm_cyc_o => wbmo_0_cyc_int
);
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
......@@ -409,7 +419,6 @@ pcie: entity work.ip_16z091_01_top
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => f_sel_pcie_lanes(SIMULATION),
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
PCIE_REQUEST_LENGTH => "0001000000", -- 64DW = 256Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
......@@ -439,7 +448,7 @@ pcie: entity work.ip_16z091_01_top
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_o => wbmo_0_cyc_int,
wbm_cyc_bar_o => wbmo_0_cyc_bar,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
......
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