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VME64x core
Commit 0b5cb429 authored by Tom Levens's avatar Tom Levens
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Implement DFS and FAF in CR/CSR 

Implements DFS feature and FAF in CR/CSR. Note that the DFS is still
interpreted incorrectly by the function decoders.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent a293bef9
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Showing with 596 additions and 286 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 0b5cb429
......@@ -252,16 +252,34 @@ entity VME64xCore_Top is
STALL_i : in std_logic;
-- For the swapper
endian_i : in std_logic_vector(2 downto 0);
endian_i : in std_logic_vector(2 downto 0) := (others => '0');
-- User CR/CSR
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
-- IRQ Generator
irq_ack_o : out std_logic; -- when the IRQ controller acknowledges the
......@@ -273,8 +291,8 @@ entity VME64xCore_Top is
-- Controller which asserts one of the IRQ
-- lines.
irq_level_i : in std_logic_vector(7 downto 0);
irq_vector_i : in std_logic_vector(7 downto 0)
irq_level_i : in std_logic_vector(7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector(7 downto 0) := (others => '0')
);
end VME64xCore_Top;
......@@ -301,14 +319,14 @@ architecture RTL of VME64xCore_Top is
signal s_cr_csr_data_o : std_logic_vector( 7 downto 0);
signal s_cr_csr_data_i : std_logic_vector( 7 downto 0);
signal s_cr_csr_we : std_logic;
signal s_ader0 : std_logic_vector(31 downto 0);
signal s_ader1 : std_logic_vector(31 downto 0);
signal s_ader2 : std_logic_vector(31 downto 0);
signal s_ader3 : std_logic_vector(31 downto 0);
signal s_ader4 : std_logic_vector(31 downto 0);
signal s_ader5 : std_logic_vector(31 downto 0);
signal s_ader6 : std_logic_vector(31 downto 0);
signal s_ader7 : std_logic_vector(31 downto 0);
signal s_f0_ader : std_logic_vector(31 downto 0);
signal s_f1_ader : std_logic_vector(31 downto 0);
signal s_f2_ader : std_logic_vector(31 downto 0);
signal s_f3_ader : std_logic_vector(31 downto 0);
signal s_f4_ader : std_logic_vector(31 downto 0);
signal s_f5_ader : std_logic_vector(31 downto 0);
signal s_f6_ader : std_logic_vector(31 downto 0);
signal s_f7_ader : std_logic_vector(31 downto 0);
signal s_module_reset : std_logic;
signal s_module_enable : std_logic;
signal s_bar : std_logic_vector(4 downto 0);
......@@ -427,14 +445,14 @@ begin
cr_csr_data_i => s_cr_csr_data_o,
cr_csr_data_o => s_cr_csr_data_i,
cr_csr_we_o => s_cr_csr_we,
ader0_i => s_ader0,
ader1_i => s_ader1,
ader2_i => s_ader2,
ader3_i => s_ader3,
ader4_i => s_ader4,
ader5_i => s_ader5,
ader6_i => s_ader6,
ader7_i => s_ader7,
f0_ader_i => s_f0_ader,
f1_ader_i => s_f1_ader,
f2_ader_i => s_f2_ader,
f3_ader_i => s_f3_ader,
f4_ader_i => s_f4_ader,
f5_ader_i => s_f5_ader,
f6_ader_i => s_f6_ader,
f7_ader_i => s_f7_ader,
endian_i => endian_i,
module_enable_i => s_module_enable,
bar_i => s_bar
......@@ -501,28 +519,51 @@ begin
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_cr_space => f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
g_beg_cram, g_end_cram,
g_beg_user_csr, g_end_user_csr,
g_beg_sn, g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr
)
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f0_dawpr => g_f0_dawpr,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f1_dawpr => g_f1_dawpr,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
)
port map (
clk_i => clk_i,
......@@ -549,14 +590,32 @@ begin
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
ader0_o => s_ader0,
ader1_o => s_ader1,
ader2_o => s_ader2,
ader3_o => s_ader3,
ader4_o => s_ader4,
ader5_o => s_ader5,
ader6_o => s_ader6,
ader7_o => s_ader7
f0_ader_o => s_f0_ader,
f1_ader_o => s_f1_ader,
f2_ader_o => s_f2_ader,
f3_ader_o => s_f3_ader,
f4_ader_o => s_f4_ader,
f5_ader_o => s_f5_ader,
f6_ader_o => s_f6_ader,
f7_ader_o => s_f7_ader,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
);
end RTL;
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ 0b5cb429
......@@ -136,7 +136,7 @@ begin
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
else
......@@ -150,7 +150,7 @@ begin
end if;
end if;
else
if s_FUNC_ADER(i)(XAM_MODE) = '1' then
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 0b5cb429
......@@ -109,13 +109,51 @@ use work.vme64x_pack.all;
entity VME_CR_CSR_Space is
generic (
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_cr_space : t_cr_array
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -142,14 +180,32 @@ entity VME_CR_CSR_Space is
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader0_o : out std_logic_vector(31 downto 0);
ader1_o : out std_logic_vector(31 downto 0);
ader2_o : out std_logic_vector(31 downto 0);
ader3_o : out std_logic_vector(31 downto 0);
ader4_o : out std_logic_vector(31 downto 0);
ader5_o : out std_logic_vector(31 downto 0);
ader6_o : out std_logic_vector(31 downto 0);
ader7_o : out std_logic_vector(31 downto 0)
f0_ader_o : out std_logic_vector(31 downto 0);
f1_ader_o : out std_logic_vector(31 downto 0);
f2_ader_o : out std_logic_vector(31 downto 0);
f3_ader_o : out std_logic_vector(31 downto 0);
f4_ader_o : out std_logic_vector(31 downto 0);
f5_ader_o : out std_logic_vector(31 downto 0);
f6_ader_o : out std_logic_vector(31 downto 0);
f7_ader_o : out std_logic_vector(31 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0);
f1_faf_ader_i : in std_logic_vector(31 downto 0);
f2_faf_ader_i : in std_logic_vector(31 downto 0);
f3_faf_ader_i : in std_logic_vector(31 downto 0);
f4_faf_ader_i : in std_logic_vector(31 downto 0);
f5_faf_ader_i : in std_logic_vector(31 downto 0);
f6_faf_ader_i : in std_logic_vector(31 downto 0);
f7_faf_ader_i : in std_logic_vector(31 downto 0);
f0_dfs_adem_i : in std_logic_vector(31 downto 0);
f1_dfs_adem_i : in std_logic_vector(31 downto 0);
f2_dfs_adem_i : in std_logic_vector(31 downto 0);
f3_dfs_adem_i : in std_logic_vector(31 downto 0);
f4_dfs_adem_i : in std_logic_vector(31 downto 0);
f5_dfs_adem_i : in std_logic_vector(31 downto 0);
f6_dfs_adem_i : in std_logic_vector(31 downto 0);
f7_dfs_adem_i : in std_logic_vector(31 downto 0)
);
end VME_CR_CSR_Space;
......@@ -177,16 +233,34 @@ architecture rtl of VME_CR_CSR_Space is
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_ader0 : std_logic_vector(31 downto 0);
signal s_reg_ader1 : std_logic_vector(31 downto 0);
signal s_reg_ader2 : std_logic_vector(31 downto 0);
signal s_reg_ader3 : std_logic_vector(31 downto 0);
signal s_reg_ader4 : std_logic_vector(31 downto 0);
signal s_reg_ader5 : std_logic_vector(31 downto 0);
signal s_reg_ader6 : std_logic_vector(31 downto 0);
signal s_reg_ader7 : std_logic_vector(31 downto 0);
type t_reg_array is array (0 to 7) of std_logic_vector(31 downto 0);
signal s_cr_rom : t_cr_array(g_cr_space'range) := g_cr_space;
signal s_reg_ader : t_reg_array;
signal s_ader : t_reg_array;
signal s_faf_ader : t_reg_array;
signal s_dfs_adem : t_reg_array;
constant c_adem : t_reg_array := (
g_f0_adem, g_f1_adem, g_f2_adem, g_f3_adem,
g_f4_adem, g_f5_adem, g_f6_adem, g_f7_adem
);
signal s_cr_rom : t_cr_array(1023 downto 0) := f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
g_beg_cram, g_end_cram,
g_beg_user_csr, g_end_user_csr,
g_beg_sn, g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr
);
begin
......@@ -231,14 +305,7 @@ begin
s_reg_bit_reg <= x"00";
s_reg_cram_owner <= x"00";
s_reg_usr_bit_reg <= x"00";
s_reg_ader0 <= x"00000000";
s_reg_ader1 <= x"00000000";
s_reg_ader2 <= x"00000000";
s_reg_ader3 <= x"00000000";
s_reg_ader4 <= x"00000000";
s_reg_ader5 <= x"00000000";
s_reg_ader6 <= x"00000000";
s_reg_ader7 <= x"00000000";
s_reg_ader <= (others => x"00000000");
else
if we_i = '1' and s_csr_access = '1' then
case s_addr is
......@@ -274,38 +341,38 @@ begin
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) and (not data_i(i));
end loop;
when c_addr_func7_ader_0(18 downto 2) => s_reg_ader7( 7 downto 0) <= data_i;
when c_addr_func7_ader_1(18 downto 2) => s_reg_ader7(15 downto 8) <= data_i;
when c_addr_func7_ader_2(18 downto 2) => s_reg_ader7(23 downto 16) <= data_i;
when c_addr_func7_ader_3(18 downto 2) => s_reg_ader7(31 downto 24) <= data_i;
when c_addr_func6_ader_0(18 downto 2) => s_reg_ader6( 7 downto 0) <= data_i;
when c_addr_func6_ader_1(18 downto 2) => s_reg_ader6(15 downto 8) <= data_i;
when c_addr_func6_ader_2(18 downto 2) => s_reg_ader6(23 downto 16) <= data_i;
when c_addr_func6_ader_3(18 downto 2) => s_reg_ader6(31 downto 24) <= data_i;
when c_addr_func5_ader_0(18 downto 2) => s_reg_ader5( 7 downto 0) <= data_i;
when c_addr_func5_ader_1(18 downto 2) => s_reg_ader5(15 downto 8) <= data_i;
when c_addr_func5_ader_2(18 downto 2) => s_reg_ader5(23 downto 16) <= data_i;
when c_addr_func5_ader_3(18 downto 2) => s_reg_ader5(31 downto 24) <= data_i;
when c_addr_func4_ader_0(18 downto 2) => s_reg_ader4( 7 downto 0) <= data_i;
when c_addr_func4_ader_1(18 downto 2) => s_reg_ader4(15 downto 8) <= data_i;
when c_addr_func4_ader_2(18 downto 2) => s_reg_ader4(23 downto 16) <= data_i;
when c_addr_func4_ader_3(18 downto 2) => s_reg_ader4(31 downto 24) <= data_i;
when c_addr_func3_ader_0(18 downto 2) => s_reg_ader3( 7 downto 0) <= data_i;
when c_addr_func3_ader_1(18 downto 2) => s_reg_ader3(15 downto 8) <= data_i;
when c_addr_func3_ader_2(18 downto 2) => s_reg_ader3(23 downto 16) <= data_i;
when c_addr_func3_ader_3(18 downto 2) => s_reg_ader3(31 downto 24) <= data_i;
when c_addr_func2_ader_0(18 downto 2) => s_reg_ader2( 7 downto 0) <= data_i;
when c_addr_func2_ader_1(18 downto 2) => s_reg_ader2(15 downto 8) <= data_i;
when c_addr_func2_ader_2(18 downto 2) => s_reg_ader2(23 downto 16) <= data_i;
when c_addr_func2_ader_3(18 downto 2) => s_reg_ader2(31 downto 24) <= data_i;
when c_addr_func1_ader_0(18 downto 2) => s_reg_ader1( 7 downto 0) <= data_i;
when c_addr_func1_ader_1(18 downto 2) => s_reg_ader1(15 downto 8) <= data_i;
when c_addr_func1_ader_2(18 downto 2) => s_reg_ader1(23 downto 16) <= data_i;
when c_addr_func1_ader_3(18 downto 2) => s_reg_ader1(31 downto 24) <= data_i;
when c_addr_func0_ader_0(18 downto 2) => s_reg_ader0( 7 downto 0) <= data_i;
when c_addr_func0_ader_1(18 downto 2) => s_reg_ader0(15 downto 8) <= data_i;
when c_addr_func0_ader_2(18 downto 2) => s_reg_ader0(23 downto 16) <= data_i;
when c_addr_func0_ader_3(18 downto 2) => s_reg_ader0(31 downto 24) <= data_i;
when c_addr_f7_ader_0(18 downto 2) => s_reg_ader(7)( 7 downto 0) <= data_i;
when c_addr_f7_ader_1(18 downto 2) => s_reg_ader(7)(15 downto 8) <= data_i;
when c_addr_f7_ader_2(18 downto 2) => s_reg_ader(7)(23 downto 16) <= data_i;
when c_addr_f7_ader_3(18 downto 2) => s_reg_ader(7)(31 downto 24) <= data_i;
when c_addr_f6_ader_0(18 downto 2) => s_reg_ader(6)( 7 downto 0) <= data_i;
when c_addr_f6_ader_1(18 downto 2) => s_reg_ader(6)(15 downto 8) <= data_i;
when c_addr_f6_ader_2(18 downto 2) => s_reg_ader(6)(23 downto 16) <= data_i;
when c_addr_f6_ader_3(18 downto 2) => s_reg_ader(6)(31 downto 24) <= data_i;
when c_addr_f5_ader_0(18 downto 2) => s_reg_ader(5)( 7 downto 0) <= data_i;
when c_addr_f5_ader_1(18 downto 2) => s_reg_ader(5)(15 downto 8) <= data_i;
when c_addr_f5_ader_2(18 downto 2) => s_reg_ader(5)(23 downto 16) <= data_i;
when c_addr_f5_ader_3(18 downto 2) => s_reg_ader(5)(31 downto 24) <= data_i;
when c_addr_f4_ader_0(18 downto 2) => s_reg_ader(4)( 7 downto 0) <= data_i;
when c_addr_f4_ader_1(18 downto 2) => s_reg_ader(4)(15 downto 8) <= data_i;
when c_addr_f4_ader_2(18 downto 2) => s_reg_ader(4)(23 downto 16) <= data_i;
when c_addr_f4_ader_3(18 downto 2) => s_reg_ader(4)(31 downto 24) <= data_i;
when c_addr_f3_ader_0(18 downto 2) => s_reg_ader(3)( 7 downto 0) <= data_i;
when c_addr_f3_ader_1(18 downto 2) => s_reg_ader(3)(15 downto 8) <= data_i;
when c_addr_f3_ader_2(18 downto 2) => s_reg_ader(3)(23 downto 16) <= data_i;
when c_addr_f3_ader_3(18 downto 2) => s_reg_ader(3)(31 downto 24) <= data_i;
when c_addr_f2_ader_0(18 downto 2) => s_reg_ader(2)( 7 downto 0) <= data_i;
when c_addr_f2_ader_1(18 downto 2) => s_reg_ader(2)(15 downto 8) <= data_i;
when c_addr_f2_ader_2(18 downto 2) => s_reg_ader(2)(23 downto 16) <= data_i;
when c_addr_f2_ader_3(18 downto 2) => s_reg_ader(2)(31 downto 24) <= data_i;
when c_addr_f1_ader_0(18 downto 2) => s_reg_ader(1)( 7 downto 0) <= data_i;
when c_addr_f1_ader_1(18 downto 2) => s_reg_ader(1)(15 downto 8) <= data_i;
when c_addr_f1_ader_2(18 downto 2) => s_reg_ader(1)(23 downto 16) <= data_i;
when c_addr_f1_ader_3(18 downto 2) => s_reg_ader(1)(31 downto 24) <= data_i;
when c_addr_f0_ader_0(18 downto 2) => s_reg_ader(0)( 7 downto 0) <= data_i;
when c_addr_f0_ader_1(18 downto 2) => s_reg_ader(0)(15 downto 8) <= data_i;
when c_addr_f0_ader_2(18 downto 2) => s_reg_ader(0)(23 downto 16) <= data_i;
when c_addr_f0_ader_3(18 downto 2) => s_reg_ader(0)(31 downto 24) <= data_i;
when others => null;
end case;
......@@ -323,18 +390,52 @@ begin
end process;
bar_o <= s_reg_bar(7 downto 3);
ader0_o <= s_reg_ader0;
ader1_o <= s_reg_ader1;
ader2_o <= s_reg_ader2;
ader3_o <= s_reg_ader3;
ader4_o <= s_reg_ader4;
ader5_o <= s_reg_ader5;
ader6_o <= s_reg_ader6;
ader7_o <= s_reg_ader7;
f0_ader_o <= s_reg_ader(0);
f1_ader_o <= s_reg_ader(1);
f2_ader_o <= s_reg_ader(2);
f3_ader_o <= s_reg_ader(3);
f4_ader_o <= s_reg_ader(4);
f5_ader_o <= s_reg_ader(5);
f6_ader_o <= s_reg_ader(6);
f7_ader_o <= s_reg_ader(7);
module_enable_o <= s_reg_bit_reg(4);
vme_sysfail_ena_o <= s_reg_bit_reg(6);
module_reset_o <= s_reg_bit_reg(7);
-- Handle DFS and FAF
s_faf_ader <= (f0_faf_ader_i, f1_faf_ader_i, f2_faf_ader_i, f3_faf_ader_i,
f4_faf_ader_i, f5_faf_ader_i, f6_faf_ader_i, f7_faf_ader_i);
s_dfs_adem <= (f0_dfs_adem_i, f1_dfs_adem_i, f2_dfs_adem_i, f3_dfs_adem_i,
f4_dfs_adem_i, f5_dfs_adem_i, f6_dfs_adem_i, f7_dfs_adem_i);
process (s_reg_ader, s_faf_ader, s_dfs_adem)
begin
-- Function 0
if c_adem(0)(ADEM_FAF) = '1' then
s_ader(0) <= s_faf_ader(0);
elsif c_adem(0)(ADEM_DFS) = '1' and s_reg_ader(0)(ADER_DFSR) = '1' then
s_ader(0) <= s_dfs_adem(0)(31 downto 8) & s_reg_ader(0)(7 downto 0);
else
s_ader(0) <= s_reg_ader(0);
end if;
-- Function 1..7
for i in 1 to 7 loop
if (c_adem(i-1)(ADEM_EFM) = '1' and c_adem(i-1)(ADEM_FAF) = '1') or
(c_adem(i-1)(ADEM_EFM) = '0' and c_adem(i)(ADEM_FAF) = '1')
then
s_ader(i) <= s_faf_ader(i);
elsif (c_adem(i-1)(ADEM_EFM) = '1' and c_adem(i-1)(ADEM_DFS) = '1' and s_reg_ader(i-1)(ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i);
elsif (c_adem(i-1)(ADEM_EFM) = '0' and c_adem(i)(ADEM_DFS) = '1' and s_reg_ader(i)(ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i)(31 downto 8) & s_reg_ader(i)(7 downto 0);
else
s_ader(i) <= s_reg_ader(i);
end if;
end loop;
end process;
-- Read
process (clk_i)
begin
......@@ -343,45 +444,45 @@ begin
s_csr_data <= x"ff";
else
case s_addr is
when c_addr_bar(18 downto 2) => s_csr_data <= s_reg_bar;
when c_addr_bit_set_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_bit_clr_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_cram_owner(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_addr_usr_set_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_usr_clr_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_func7_ader_0(18 downto 2) => s_csr_data <= s_reg_ader7( 7 downto 0);
when c_addr_func7_ader_1(18 downto 2) => s_csr_data <= s_reg_ader7(15 downto 8);
when c_addr_func7_ader_2(18 downto 2) => s_csr_data <= s_reg_ader7(23 downto 16);
when c_addr_func7_ader_3(18 downto 2) => s_csr_data <= s_reg_ader7(31 downto 24);
when c_addr_func6_ader_0(18 downto 2) => s_csr_data <= s_reg_ader6( 7 downto 0);
when c_addr_func6_ader_1(18 downto 2) => s_csr_data <= s_reg_ader6(15 downto 8);
when c_addr_func6_ader_2(18 downto 2) => s_csr_data <= s_reg_ader6(23 downto 16);
when c_addr_func6_ader_3(18 downto 2) => s_csr_data <= s_reg_ader6(31 downto 24);
when c_addr_func5_ader_0(18 downto 2) => s_csr_data <= s_reg_ader5( 7 downto 0);
when c_addr_func5_ader_1(18 downto 2) => s_csr_data <= s_reg_ader5(15 downto 8);
when c_addr_func5_ader_2(18 downto 2) => s_csr_data <= s_reg_ader5(23 downto 16);
when c_addr_func5_ader_3(18 downto 2) => s_csr_data <= s_reg_ader5(31 downto 24);
when c_addr_func4_ader_0(18 downto 2) => s_csr_data <= s_reg_ader4( 7 downto 0);
when c_addr_func4_ader_1(18 downto 2) => s_csr_data <= s_reg_ader4(15 downto 8);
when c_addr_func4_ader_2(18 downto 2) => s_csr_data <= s_reg_ader4(23 downto 16);
when c_addr_func4_ader_3(18 downto 2) => s_csr_data <= s_reg_ader4(31 downto 24);
when c_addr_func3_ader_0(18 downto 2) => s_csr_data <= s_reg_ader3( 7 downto 0);
when c_addr_func3_ader_1(18 downto 2) => s_csr_data <= s_reg_ader3(15 downto 8);
when c_addr_func3_ader_2(18 downto 2) => s_csr_data <= s_reg_ader3(23 downto 16);
when c_addr_func3_ader_3(18 downto 2) => s_csr_data <= s_reg_ader3(31 downto 24);
when c_addr_func2_ader_0(18 downto 2) => s_csr_data <= s_reg_ader2( 7 downto 0);
when c_addr_func2_ader_1(18 downto 2) => s_csr_data <= s_reg_ader2(15 downto 8);
when c_addr_func2_ader_2(18 downto 2) => s_csr_data <= s_reg_ader2(23 downto 16);
when c_addr_func2_ader_3(18 downto 2) => s_csr_data <= s_reg_ader2(31 downto 24);
when c_addr_func1_ader_0(18 downto 2) => s_csr_data <= s_reg_ader1( 7 downto 0);
when c_addr_func1_ader_1(18 downto 2) => s_csr_data <= s_reg_ader1(15 downto 8);
when c_addr_func1_ader_2(18 downto 2) => s_csr_data <= s_reg_ader1(23 downto 16);
when c_addr_func1_ader_3(18 downto 2) => s_csr_data <= s_reg_ader1(31 downto 24);
when c_addr_func0_ader_0(18 downto 2) => s_csr_data <= s_reg_ader0( 7 downto 0);
when c_addr_func0_ader_1(18 downto 2) => s_csr_data <= s_reg_ader0(15 downto 8);
when c_addr_func0_ader_2(18 downto 2) => s_csr_data <= s_reg_ader0(23 downto 16);
when c_addr_func0_ader_3(18 downto 2) => s_csr_data <= s_reg_ader0(31 downto 24);
when others => s_csr_data <= x"ff";
when c_addr_bar(18 downto 2) => s_csr_data <= s_reg_bar;
when c_addr_bit_set_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_bit_clr_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_cram_owner(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_addr_usr_set_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_usr_clr_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_f7_ader_0(18 downto 2) => s_csr_data <= s_ader(7)( 7 downto 0);
when c_addr_f7_ader_1(18 downto 2) => s_csr_data <= s_ader(7)(15 downto 8);
when c_addr_f7_ader_2(18 downto 2) => s_csr_data <= s_ader(7)(23 downto 16);
when c_addr_f7_ader_3(18 downto 2) => s_csr_data <= s_ader(7)(31 downto 24);
when c_addr_f6_ader_0(18 downto 2) => s_csr_data <= s_ader(6)( 7 downto 0);
when c_addr_f6_ader_1(18 downto 2) => s_csr_data <= s_ader(6)(15 downto 8);
when c_addr_f6_ader_2(18 downto 2) => s_csr_data <= s_ader(6)(23 downto 16);
when c_addr_f6_ader_3(18 downto 2) => s_csr_data <= s_ader(6)(31 downto 24);
when c_addr_f5_ader_0(18 downto 2) => s_csr_data <= s_ader(5)( 7 downto 0);
when c_addr_f5_ader_1(18 downto 2) => s_csr_data <= s_ader(5)(15 downto 8);
when c_addr_f5_ader_2(18 downto 2) => s_csr_data <= s_ader(5)(23 downto 16);
when c_addr_f5_ader_3(18 downto 2) => s_csr_data <= s_ader(5)(31 downto 24);
when c_addr_f4_ader_0(18 downto 2) => s_csr_data <= s_ader(4)( 7 downto 0);
when c_addr_f4_ader_1(18 downto 2) => s_csr_data <= s_ader(4)(15 downto 8);
when c_addr_f4_ader_2(18 downto 2) => s_csr_data <= s_ader(4)(23 downto 16);
when c_addr_f4_ader_3(18 downto 2) => s_csr_data <= s_ader(4)(31 downto 24);
when c_addr_f3_ader_0(18 downto 2) => s_csr_data <= s_ader(3)( 7 downto 0);
when c_addr_f3_ader_1(18 downto 2) => s_csr_data <= s_ader(3)(15 downto 8);
when c_addr_f3_ader_2(18 downto 2) => s_csr_data <= s_ader(3)(23 downto 16);
when c_addr_f3_ader_3(18 downto 2) => s_csr_data <= s_ader(3)(31 downto 24);
when c_addr_f2_ader_0(18 downto 2) => s_csr_data <= s_ader(2)( 7 downto 0);
when c_addr_f2_ader_1(18 downto 2) => s_csr_data <= s_ader(2)(15 downto 8);
when c_addr_f2_ader_2(18 downto 2) => s_csr_data <= s_ader(2)(23 downto 16);
when c_addr_f2_ader_3(18 downto 2) => s_csr_data <= s_ader(2)(31 downto 24);
when c_addr_f1_ader_0(18 downto 2) => s_csr_data <= s_ader(1)( 7 downto 0);
when c_addr_f1_ader_1(18 downto 2) => s_csr_data <= s_ader(1)(15 downto 8);
when c_addr_f1_ader_2(18 downto 2) => s_csr_data <= s_ader(1)(23 downto 16);
when c_addr_f1_ader_3(18 downto 2) => s_csr_data <= s_ader(1)(31 downto 24);
when c_addr_f0_ader_0(18 downto 2) => s_csr_data <= s_ader(0)( 7 downto 0);
when c_addr_f0_ader_1(18 downto 2) => s_csr_data <= s_ader(0)(15 downto 8);
when c_addr_f0_ader_2(18 downto 2) => s_csr_data <= s_ader(0)(23 downto 16);
when c_addr_f0_ader_3(18 downto 2) => s_csr_data <= s_ader(0)(31 downto 24);
when others => s_csr_data <= x"ff";
end case;
end if;
end if;
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 0b5cb429
......@@ -318,7 +318,7 @@ begin
s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(DFS);
DFS_o(i) <= s_FUNC_ADEM(i)(ADEM_DFS);
end generate GDFS;
GADER_64 : for i in 0 to 6 generate
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 0b5cb429
......@@ -149,14 +149,14 @@ entity VME_bus is
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
ader0_i : in std_logic_vector(31 downto 0);
ader1_i : in std_logic_vector(31 downto 0);
ader2_i : in std_logic_vector(31 downto 0);
ader3_i : in std_logic_vector(31 downto 0);
ader4_i : in std_logic_vector(31 downto 0);
ader5_i : in std_logic_vector(31 downto 0);
ader6_i : in std_logic_vector(31 downto 0);
ader7_i : in std_logic_vector(31 downto 0);
f0_ader_i : in std_logic_vector(31 downto 0);
f1_ader_i : in std_logic_vector(31 downto 0);
f2_ader_i : in std_logic_vector(31 downto 0);
f3_ader_i : in std_logic_vector(31 downto 0);
f4_ader_i : in std_logic_vector(31 downto 0);
f5_ader_i : in std_logic_vector(31 downto 0);
f6_ader_i : in std_logic_vector(31 downto 0);
f7_ader_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
......@@ -1120,14 +1120,14 @@ begin
decode => s_decode,
ModuleEnable => module_enable_i,
Addr => std_logic_vector(s_locAddr),
Ader0 => ader0_i,
Ader1 => ader1_i,
Ader2 => ader2_i,
Ader3 => ader3_i,
Ader4 => ader4_i,
Ader5 => ader5_i,
Ader6 => ader6_i,
Ader7 => ader7_i,
Ader0 => f0_ader_i,
Ader1 => f1_ader_i,
Ader2 => f2_ader_i,
Ader3 => f3_ader_i,
Ader4 => f4_ader_i,
Ader5 => f5_ader_i,
Ader6 => f6_ader_i,
Ader7 => f7_ader_i,
Adem0 => g_f0_adem,
Adem1 => g_f1_adem,
Adem2 => g_f2_adem,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 0b5cb429
......@@ -56,8 +56,14 @@ package vme64x_pack is
constant c_revision_id : std_logic_vector(31 downto 0) := x"00000001";
constant c_program_id : std_logic_vector( 7 downto 0) := x"5a";
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
-- Bits in ADEM/ADER registers
constant ADEM_FAF : integer := 3;
constant ADEM_DFS : integer := 2;
constant ADEM_EFD : integer := 1;
constant ADEM_EFM : integer := 0;
constant ADER_DFSR : integer := 1;
constant ADER_XAM_MODE : integer := 0;
-- AM table.
-- References:
......@@ -112,38 +118,38 @@ package vme64x_pack is
constant c_addr_cram_owner : unsigned(19 downto 0) := x"7FFF3";
constant c_addr_usr_set_reg : unsigned(19 downto 0) := x"7FFEF";
constant c_addr_usr_clr_reg : unsigned(19 downto 0) := x"7FFEB";
constant c_addr_func7_ader_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_addr_func7_ader_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_addr_func7_ader_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_addr_func7_ader_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_addr_func6_ader_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_addr_func6_ader_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_addr_func6_ader_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_addr_func6_ader_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_addr_func5_ader_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_addr_func5_ader_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_addr_func5_ader_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_addr_func5_ader_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_addr_func4_ader_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_addr_func4_ader_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_addr_func4_ader_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_addr_func4_ader_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_addr_func3_ader_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_addr_func3_ader_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_addr_func3_ader_2 : unsigned(19 downto 0) := x"7FF97";
constant c_addr_func3_ader_3 : unsigned(19 downto 0) := x"7FF93";
constant c_addr_func2_ader_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_addr_func2_ader_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_addr_func2_ader_2 : unsigned(19 downto 0) := x"7FF87";
constant c_addr_func2_ader_3 : unsigned(19 downto 0) := x"7FF83";
constant c_addr_func1_ader_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_addr_func1_ader_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_addr_func1_ader_2 : unsigned(19 downto 0) := x"7FF77";
constant c_addr_func1_ader_3 : unsigned(19 downto 0) := x"7FF73";
constant c_addr_func0_ader_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_addr_func0_ader_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_addr_func0_ader_2 : unsigned(19 downto 0) := x"7FF67";
constant c_addr_func0_ader_3 : unsigned(19 downto 0) := x"7FF63";
constant c_addr_f7_ader_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_addr_f7_ader_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_addr_f7_ader_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_addr_f7_ader_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_addr_f6_ader_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_addr_f6_ader_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_addr_f6_ader_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_addr_f6_ader_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_addr_f5_ader_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_addr_f5_ader_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_addr_f5_ader_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_addr_f5_ader_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_addr_f4_ader_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_addr_f4_ader_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_addr_f4_ader_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_addr_f4_ader_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_addr_f3_ader_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_addr_f3_ader_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_addr_f3_ader_2 : unsigned(19 downto 0) := x"7FF97";
constant c_addr_f3_ader_3 : unsigned(19 downto 0) := x"7FF93";
constant c_addr_f2_ader_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_addr_f2_ader_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_addr_f2_ader_2 : unsigned(19 downto 0) := x"7FF87";
constant c_addr_f2_ader_3 : unsigned(19 downto 0) := x"7FF83";
constant c_addr_f1_ader_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_addr_f1_ader_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_addr_f1_ader_2 : unsigned(19 downto 0) := x"7FF77";
constant c_addr_f1_ader_3 : unsigned(19 downto 0) := x"7FF73";
constant c_addr_f0_ader_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_addr_f0_ader_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_addr_f0_ader_2 : unsigned(19 downto 0) := x"7FF67";
constant c_addr_f0_ader_3 : unsigned(19 downto 0) := x"7FF63";
-- User CSR addresses
constant c_addr_irq_vector : unsigned(19 downto 0) := x"0002F";
......@@ -423,17 +429,33 @@ package vme64x_pack is
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
endian_i : in std_logic_vector(2 downto 0);
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
irq_ack_o : out std_logic;
irq_i : in std_logic;
irq_level_i : in std_logic_vector(7 downto 0);
irq_vector_i : in std_logic_vector(7 downto 0)
irq_level_i : in std_logic_vector(7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector(7 downto 0) := (others => '0')
);
end component;
......@@ -512,14 +534,14 @@ package vme64x_pack is
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
ader0_i : in std_logic_vector(31 downto 0);
ader1_i : in std_logic_vector(31 downto 0);
ader2_i : in std_logic_vector(31 downto 0);
ader3_i : in std_logic_vector(31 downto 0);
ader4_i : in std_logic_vector(31 downto 0);
ader5_i : in std_logic_vector(31 downto 0);
ader6_i : in std_logic_vector(31 downto 0);
ader7_i : in std_logic_vector(31 downto 0);
f0_ader_i : in std_logic_vector(31 downto 0);
f1_ader_i : in std_logic_vector(31 downto 0);
f2_ader_i : in std_logic_vector(31 downto 0);
f3_ader_i : in std_logic_vector(31 downto 0);
f4_ader_i : in std_logic_vector(31 downto 0);
f5_ader_i : in std_logic_vector(31 downto 0);
f6_ader_i : in std_logic_vector(31 downto 0);
f7_ader_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
......@@ -609,13 +631,51 @@ package vme64x_pack is
component VME_CR_CSR_Space is
generic (
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_cr_space : t_cr_array
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -637,14 +697,30 @@ package vme64x_pack is
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader0_o : out std_logic_vector(31 downto 0);
ader1_o : out std_logic_vector(31 downto 0);
ader2_o : out std_logic_vector(31 downto 0);
ader3_o : out std_logic_vector(31 downto 0);
ader4_o : out std_logic_vector(31 downto 0);
ader5_o : out std_logic_vector(31 downto 0);
ader6_o : out std_logic_vector(31 downto 0);
ader7_o : out std_logic_vector(31 downto 0)
f0_ader_o : out std_logic_vector(31 downto 0);
f1_ader_o : out std_logic_vector(31 downto 0);
f2_ader_o : out std_logic_vector(31 downto 0);
f3_ader_o : out std_logic_vector(31 downto 0);
f4_ader_o : out std_logic_vector(31 downto 0);
f5_ader_o : out std_logic_vector(31 downto 0);
f6_ader_o : out std_logic_vector(31 downto 0);
f7_ader_o : out std_logic_vector(31 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0);
f1_faf_ader_i : in std_logic_vector(31 downto 0);
f2_faf_ader_i : in std_logic_vector(31 downto 0);
f3_faf_ader_i : in std_logic_vector(31 downto 0);
f4_faf_ader_i : in std_logic_vector(31 downto 0);
f5_faf_ader_i : in std_logic_vector(31 downto 0);
f6_faf_ader_i : in std_logic_vector(31 downto 0);
f7_faf_ader_i : in std_logic_vector(31 downto 0);
f0_dfs_adem_i : in std_logic_vector(31 downto 0);
f1_dfs_adem_i : in std_logic_vector(31 downto 0);
f2_dfs_adem_i : in std_logic_vector(31 downto 0);
f3_dfs_adem_i : in std_logic_vector(31 downto 0);
f4_dfs_adem_i : in std_logic_vector(31 downto 0);
f5_dfs_adem_i : in std_logic_vector(31 downto 0);
f6_dfs_adem_i : in std_logic_vector(31 downto 0);
f7_dfs_adem_i : in std_logic_vector(31 downto 0)
);
end component VME_CR_CSR_Space;
......
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 0b5cb429
......@@ -40,6 +40,7 @@ entity xvme64x_core is
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false;
-- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
......@@ -136,7 +137,33 @@ entity xvme64x_core is
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
irq_ack_o : out std_logic;
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0')
);
end xvme64x_core;
......@@ -144,15 +171,15 @@ end xvme64x_core;
architecture wrapper of xvme64x_core is
signal dat_out,
dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(31 downto 0);
dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(31 downto 0);
signal irq_vector,
irq_level : std_logic_vector( 7 downto 0);
signal endian : std_logic_vector( 2 downto 0);
signal user_csr_addr : std_logic_vector(18 downto 2);
signal user_csr_data_i,
user_csr_data_o : std_logic_vector( 7 downto 0);
signal user_csr_we : std_logic;
irq_level : std_logic_vector( 7 downto 0);
signal endian : std_logic_vector( 2 downto 0);
signal user_csr_addr : std_logic_vector(18 downto 2);
signal user_csr_data_in,
user_csr_data_out : std_logic_vector( 7 downto 0);
signal user_csr_we : std_logic;
begin -- wrapper
......@@ -253,16 +280,34 @@ begin -- wrapper
endian_i => endian,
user_csr_addr_o => user_csr_addr,
user_csr_data_i => user_csr_data_o,
user_csr_data_o => user_csr_data_i,
user_csr_data_i => user_csr_data_in,
user_csr_data_o => user_csr_data_out,
user_csr_we_o => user_csr_we,
user_cr_addr_o => open,
user_cr_data_i => x"00",
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
irq_i => irq_i,
irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector,
irq_level_i => irq_level
irq_level_i => irq_level,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
);
master_o.dat <= dat_out(31 downto 0);
......@@ -270,22 +315,31 @@ begin -- wrapper
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
U_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
addr_i => user_csr_addr,
data_i => user_csr_data_i,
data_o => user_csr_data_o,
we_i => user_csr_we,
irq_vector_o => irq_vector,
irq_level_o => irq_level,
endian_o => endian,
time_i => x"0000000000",
bytes_i => x"0000"
);
gen_user_cr_csr: if g_user_csr_ext = false generate
U_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
addr_i => user_csr_addr,
data_i => user_csr_data_out,
data_o => user_csr_data_in,
we_i => user_csr_we,
irq_vector_o => irq_vector,
irq_level_o => irq_level,
endian_o => endian,
time_i => x"0000000000",
bytes_i => x"0000"
);
end generate;
gen_no_user_cr_csr: if g_user_csr_ext = true generate
user_csr_data_in <= user_csr_data_i;
end generate;
user_csr_addr_o <= user_csr_addr;
user_csr_data_o <= user_csr_data_out;
user_csr_we_o <= user_csr_we;
end wrapper;
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ 0b5cb429
......@@ -81,6 +81,7 @@ package xvme64x_core_pkg is
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_user_csr_ext : boolean;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
......@@ -131,7 +132,6 @@ package xvme64x_core_pkg is
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
......@@ -157,12 +157,32 @@ package xvme64x_core_pkg is
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic;
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0')
);
end component xvme64x_core;
......
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