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VME64x core
Commit 199c8e94 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/boards/svec/testbench: fixed compile errors with new VME64x core interface

parent b2fc3ce7
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Showing with 452 additions and 468 deletions
hdl/boards/svec/rtl/Manifest.py 0 → 100644
View file @ 199c8e94
files=["IRQ_Generator_Top.vhd",
"IRQ_generator.vhd",
"ram_8bits.vhd",
"spram.vhd",
"TOP_LEVEL.vhd",
"WB_Bridge.vhd",
"xwb_ram.vhd",
"wishbone_pkg.vhd",
"genram_pkg.vhd"];
\ No newline at end of file
hdl/boards/svec/rtl/TOP_LEVEL.vhd
View file @ 199c8e94
......@@ -77,10 +77,10 @@
---------------------------------------------------------------------------------------
-- uncomment to use the PLL
Library UNISIM;
library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
......@@ -90,51 +90,51 @@ use work.VME_CR_pack.all;
-- Entity declaration
--===========================================================================
entity TOP_LEVEL is
generic(
g_clock : integer := 10;
--WB data width:
g_wb_data_width : integer := 64; --c_width;
-- WB addr width:
g_wb_addr_width : integer := 11; --c_addr_width;
--CRAM size in the CR/CSR space (bytes):
g_cram_size : integer := 1024; --c_CRAM_SIZE;
--My WB slave memory:
g_WB_memory_size : integer := 1024; -- c_SIZE
g_BoardID : integer := 408; -- 0x00000198
g_ManufacturerID : integer := 524336; -- 0x080030
g_RevisionID : integer := 1; -- 0x00000001
g_ProgramID : integer := 90 -- 0x0000005a
);
port(
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic;
generic(
g_clock : integer := 10;
--WB data width:
g_wb_data_width : integer := 64; --c_width;
-- WB addr width:
g_wb_addr_width : integer := 11; --c_addr_width;
--CRAM size in the CR/CSR space (bytes):
g_cram_size : integer := 1024; --c_CRAM_SIZE;
--My WB slave memory:
g_WB_memory_size : integer := 1024; -- c_SIZE
g_BoardID : integer := 408; -- 0x00000198
g_ManufacturerID : integer := 524336; -- 0x080030
g_RevisionID : integer := 1; -- 0x00000001
g_ProgramID : integer := 90 -- 0x0000005a
);
port(
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic;
-- VME buffers
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
end TOP_LEVEL;
--===========================================================================
......@@ -142,311 +142,305 @@ end TOP_LEVEL;
--===========================================================================
architecture Behavioral of TOP_LEVEL is
component VME64xCore_Top is
generic(
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
port(
-- VME signals:
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
-- IRQ Generator
IRQ_i : in std_logic;
INT_ack_o : out std_logic;
reset_o : out std_logic;
-- for debug:
debug : out std_logic_vector(7 downto 0)
);
end component VME64xCore_Top;
component xwb_ram is
generic(
g_size : integer := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end component xwb_ram;
component VME64xCore_Top is
generic(
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
component WB_Bridge is
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic
);
end component WB_Bridge;
signal WbDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal WbMemDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbMemCyc_i : std_logic;
signal WbMemErr_o : std_logic;
signal WbMemRty_o : std_logic;
signal WbMemSel_i : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbMemStb_i : std_logic;
signal WbMemAck_o : std_logic;
signal WbMemWe_i : std_logic;
signal WbMemStall_o : std_logic;
signal Rst : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst : std_logic;
component xwb_ram is
generic(
g_size : integer := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end component xwb_ram;
component WB_Bridge is
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic
);
end component WB_Bridge;
signal WbDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal WbMemDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbMemCyc_i : std_logic;
signal WbMemErr_o : std_logic;
signal WbMemRty_o : std_logic;
signal WbMemSel_i : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbMemStb_i : std_logic;
signal WbMemAck_o : std_logic;
signal WbMemWe_i : std_logic;
signal WbMemStall_o : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst_n: std_logic;
--mux
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_VME_DATA_DIR : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_VME_ADDR_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_VME_DATA_DIR : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_VME_ADDR_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
Inst_VME64xCore_Top: VME64xCore_Top
generic map(
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size,
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
)
port map(
s_rst_n <= not reset;
Inst_VME64xCore_Top : VME64xCore_Top
generic map(
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size,
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
)
port map(
-- VME
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_i => VME_LWORD_n_b,
VME_LWORD_n_o => s_VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b,
VME_ADDR_o => s_VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b,
VME_DATA_o => s_VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-- buffer
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
--WB
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
CYC_o => WbCyc_o,
ERR_i => WbErr_i,
RTY_i => WbRty_i,
SEL_o => WbSel_o,
STB_o => WbStb_o,
ACK_i => WbAck_i,
WE_o => WbWe_o,
STALL_i => WbStall_i,
--IRQ Generator
IRQ_i => WbIrq_i,
INT_ack_o => s_INT_ack,
reset_o => s_rst,
-- Add by Davide for debug:
debug => leds
);
clk_i => clk_in,
rst_n_i => s_rst_n,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_i => VME_LWORD_n_b,
VME_LWORD_n_o => s_VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b,
VME_ADDR_o => s_VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b,
VME_DATA_o => s_VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-- buffer
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
--WB
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
CYC_o => WbCyc_o,
ERR_i => WbErr_i,
RTY_i => WbRty_i,
SEL_o => WbSel_o,
STB_o => WbStb_o,
ACK_i => WbAck_i,
WE_o => WbWe_o,
STALL_i => WbStall_i,
--IRQ Generator
IRQ_i => WbIrq_i,
INT_ack_o => s_INT_ack,
-- Add by Davide for debug:
debug => leds
);
Inst_xwb_ram : xwb_ram
generic map(g_size => g_WB_memory_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
)
port map(
clk_sys_i => clk_in,
slave1_i.cyc => WbMemCyc_i,
slave1_i.stb => WbMemStb_i,
slave1_i.adr => WbMemAdr_i,
slave1_i.sel => WbMemSel_i,
slave1_i.we => WbMemWe_i,
slave1_i.dat => WbMemDat_i,
slave1_o.ack => WbMemAck_o,
slave1_o.err => WbMemErr_o,
slave1_o.rty => WbMemRty_o,
slave1_o.stall => WbMemStall_o,
slave1_o.dat => WbMemDat_o
);
Inst_WB_Bridge : WB_Bridge
generic map(
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_in,
rst_i => reset,
Int_Ack_i => s_INT_ack,
Int_Req_o => WbIrq_i,
cyc_i => WbCyc_o,
stb_i => WbStb_o,
adr_i => WbAdr_o,
dat_i => WbDat_o,
sel_i => WbSel_o,
we_i => WbWe_o,
ack_o => WbAck_i,
err_o => WbErr_i,
rty_o => WbRty_i,
stall_o => WbStall_i,
dat_o => WbDat_i,
m_cyc_o => WbMemCyc_i,
m_stb_o => WbMemStb_i,
m_adr_o => WbMemAdr_i,
m_dat_o => WbMemDat_i,
m_sel_o => WbMemSel_i,
m_we_o => WbMemWe_i,
m_ack_i => WbMemAck_o,
m_err_i => WbMemErr_o,
m_stall_i => WbMemStall_o,
m_rty_i => WbMemRty_o,
m_dat_i => WbMemDat_o
);
Inst_xwb_ram: xwb_ram
generic map(g_size => g_WB_memory_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
)
port map(
clk_sys_i => clk_in,
slave1_i.cyc => WbMemCyc_i,
slave1_i.stb => WbMemStb_i,
slave1_i.adr => WbMemAdr_i,
slave1_i.sel => WbMemSel_i,
slave1_i.we => WbMemWe_i,
slave1_i.dat => WbMemDat_i,
slave1_o.ack => WbMemAck_o,
slave1_o.err => WbMemErr_o,
slave1_o.rty => WbMemRty_o,
slave1_o.stall => WbMemStall_o,
slave1_o.dat => WbMemDat_o
);
Inst_WB_Bridge: WB_Bridge
generic map(
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_in,
rst_i => s_rst,
Int_Ack_i => s_INT_ack,
Int_Req_o => WbIrq_i,
cyc_i => WbCyc_o,
stb_i => WbStb_o,
adr_i => WbAdr_o,
dat_i => WbDat_o,
sel_i => WbSel_o,
we_i => WbWe_o,
ack_o => WbAck_i,
err_o => WbErr_i,
rty_o => WbRty_i,
stall_o => WbStall_i,
dat_o => WbDat_i,
m_cyc_o => WbMemCyc_i,
m_stb_o => WbMemStb_i,
m_adr_o => WbMemAdr_i,
m_dat_o => WbMemDat_i,
m_sel_o => WbMemSel_i,
m_we_o => WbMemWe_i,
m_ack_i => WbMemAck_o,
m_err_i => WbMemErr_o,
m_stall_i => WbMemStall_o,
m_rty_i => WbMemRty_o,
m_dat_i => WbMemDat_o
);
Rst <= VME_RST_n_i and Reset;
---------------------------------------------------------------------------------
-- buffers
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
---------------------------------------------------------------------------------
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
-- buffers
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
---------------------------------------------------------------------------------
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
......@@ -455,32 +449,32 @@ port map(
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016,-- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016, -- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => false -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
CLKOUT0 => clk_in_buf, --clk 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_in,
I => clk_in_buf);
-- comment the next line if the PLL is used:
-- clk_in <= clk_i;
-- clk_in <= clk_i;
end Behavioral;
--===========================================================================
-- Architecture end
......
hdl/boards/svec/sim/testbench/Manifest.py 0 → 100644
View file @ 199c8e94
files =["VME64x_Package.vhd",
"VME64x_SIM_Package.vhd",
"VME64x_TB.vhd",
"../../../../vme64x-core/rtl/VME64xCore_Top.vhd",
"../../../../vme64x-core/rtl/vme64x_pack.vhd",
"../../../../vme64x-core/rtl/VME_Access_Decode.vhd",
"../../../../vme64x-core/rtl/VME_Am_Match.vhd",
"../../../../vme64x-core/rtl/VME_bus.vhd",
"../../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd",
"../../../../vme64x-core/rtl/VME_CR_pack.vhd",
"../../../../vme64x-core/rtl/VME_CSR_pack.vhd",
"../../../../vme64x-core/rtl/VME_CRAM.vhd",
"../../../../vme64x-core/rtl/VME_Funct_Match.vhd",
"../../../../vme64x-core/rtl/VME_Init.vhd",
"../../../../vme64x-core/rtl/VME_IRQ_Controller.vhd",
"../../../../vme64x-core/rtl/VME_SharedComps.vhd",
"../../../../vme64x-core/rtl/VME_swapper.vhd",
"../../../../vme64x-core/rtl/VME_Wb_master.vhd"];
modules = {"local":[ "../../rtl"]};
hdl/boards/svec/sim/testbench/VME64x_TB.vhd
View file @ 199c8e94
......@@ -13,7 +13,7 @@ use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
use work.VME64xSim.all;
use work.VME64x.all;
use work.wishbone_pkg.all;
--use work.wishbone_pkg.all;
use std.textio.all;
use work.vme64x_pack.all;
......@@ -173,7 +173,9 @@ BEGIN
test_VME64x : process
begin
wait for 100ns;
Reset <= '0';
wait for 8800 ns; -- wait until the initialization finish (wait more than 8705 ns)
-- Write in CSR:
VME64xBus_Out.Vme64xIACK <= '1';
......
hdl/boards/svec/sim/testbench/run.do 0 → 100644
View file @ 199c8e94
vlib work
make
vsim -t 1ps -L unisim -c work.vme64x_tb
do wave1.do
run 100us
\ No newline at end of file
hdl/boards/svec/sim/testbench/wave1.do
View file @ 199c8e94
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/clk_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/s_mainFSMstate
add wave -noupdate -expand -group VME_TOP /vme64x_tb/s_dataTransferType
add wave -noupdate -expand -group VME_TOP /vme64x_tb/s_AddressingType
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/Reset
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_AS_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_RST_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_WRITE_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_AM_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DS_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_GA_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_BERR_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DTACK_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_RETRY_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_LWORD_n_b
add wave -noupdate -expand -group VME_TOP -radix hexadecimal /vme64x_tb/uut/VME_ADDR_b
add wave -noupdate -expand -group VME_TOP -radix hexadecimal /vme64x_tb/uut/VME_DATA_b
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IRQ_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IACKIN_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IACKOUT_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IACK_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_RETRY_OE_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DTACK_OE_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DATA_DIR_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DATA_OE_N_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_ADDR_DIR_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_ADDR_OE_N_o
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/clk_i
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/ModuleEnable
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/InitInProgress
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Addr
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader0
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader1
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader2
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader3
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader4
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader5
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader6
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Ader7
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem0
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem1
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem2
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem3
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem4
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem5
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem6
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Adem7
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap0
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap1
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap2
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap3
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap4
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap5
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap6
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AmCap7
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap0
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap1
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap2
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap3
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap4
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap5
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap6
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAmCap7
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Am
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/XAm
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/AddrWidth
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Funct_Sel
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Base_Addr
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Confaccess
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/CardSel
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/clk_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/stall_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/rty_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/err_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/cyc_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/memReq_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/WBdata_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/wbData_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/locAddr_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/memAckWB_i
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/WbSel_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/RW_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/clk_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_IACKIN_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_AS_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DS_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_LWORD_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_ADDR_123
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/INT_Level
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/INT_Vector
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/INT_Req
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_IRQ_n_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_IACKOUT_n_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DTACK_n_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DATA_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_cyc_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_stb_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_adr_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_dat_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_sel_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_we_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_ack_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_err_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_stall_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_rty_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_dat_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/s_VMEaddrInput
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/Reset
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_AS_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RST_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_WRITE_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_AM_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DS_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_GA_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_BERR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DTACK_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RETRY_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_LWORD_n_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IRQ_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACKIN_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACKOUT_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACK_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RETRY_OE_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DTACK_OE_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_DIR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_OE_N_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_DIR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_OE_N_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/leds
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbDat_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbDat_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbAdr_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbCyc_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbErr_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbRty_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbSel_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbStb_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbAck_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbWe_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbStall_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbIrq_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemDat_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemDat_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemAdr_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemCyc_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemErr_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemRty_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemSel_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemStb_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemAck_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemWe_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemStall_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_in_buf
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_in
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_locked
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_fb
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_INT_ack
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_rst_n
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_DATA_b_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_DATA_DIR
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_ADDR_DIR
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_ADDR_b_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_LWORD_n_b_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8963596 ps} 0}
WaveRestoreCursors {{Cursor 1} {8963000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -123,4 +75,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {7948848 ps} {10676982 ps}
WaveRestoreZoom {97409 ns} {100137 ns}
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