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VME64x core
Commit 2cdedc10 authored by Tristan Gingold's avatar Tristan Gingold
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vme_bus: renaming.

parent b5476928
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hdl/rtl/vme_bus.vhd
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......@@ -132,21 +132,21 @@ architecture rtl of vme_bus is
signal s_locDataIn : std_logic_vector(63 downto 0);
signal s_locDataOut : std_logic_vector(63 downto 0);
-- VME latched signals
-- VME latched signals - corresponds to the input dff in the pad.
-- latched at the rising edge of /AS:
signal s_ADDRlatched : std_logic_vector(31 downto 1);
signal s_LWORDlatched_n : std_logic;
signal s_AMlatched : std_logic_vector(5 downto 0);
signal vme_idff_addr : std_logic_vector(31 downto 1);
signal vme_idff_lword_n : std_logic;
signal vme_idff_am : std_logic_vector(5 downto 0);
signal s_DSlatched_n : std_logic_vector(1 downto 0);
signal s_WRITElatched_n : std_logic;
signal vme_idff_ds_n : std_logic_vector(1 downto 0);
signal vme_idff_write_n : std_logic;
-- Address and data from the VME bus. There are two registers so that the
-- first one can be placed in the IOBs.
signal s_vme_addr_reg : std_logic_vector(31 downto 1);
signal s_vme_data_reg : std_logic_vector(31 downto 0);
signal s_vme_lword_n_reg : std_logic;
signal s_vme_addr_dir : std_logic;
signal vme_odff_addr : std_logic_vector(31 downto 1);
signal vme_odff_data : std_logic_vector(31 downto 0);
signal vme_odff_lword_n : std_logic;
signal vme_odff_addr_dir : std_logic;
type t_addressingType is (
A24,
......@@ -308,7 +308,7 @@ begin
-- Address modifier decoder
-- Both the supervisor and the user access modes are supported
with s_AMlatched select s_addressingType <=
with vme_idff_am select s_addressingType <=
A24 when c_AM_A24_SUP | c_AM_A24,
A24_BLT when c_AM_A24_BLT | c_AM_A24_BLT_SUP,
A24_MBLT when c_AM_A24_MBLT | c_AM_A24_MBLT_SUP,
......@@ -361,11 +361,11 @@ begin
s_wb_first_pf <= '1';
s_wb_prefetch <= '0';
s_ADDRlatched <= (others => '0');
s_AMlatched <= (others => '0');
vme_idff_addr <= (others => '0');
vme_idff_am <= (others => '0');
s_vme_addr_reg <= (others => '0');
s_vme_addr_dir <= '0';
vme_odff_addr <= (others => '0');
vme_odff_addr_dir <= '0';
s_card_sel <= '0';
s_conf_sel <= '0';
......@@ -390,9 +390,9 @@ begin
assert vme_as_n_i = '0';
-- Store ADDR, AM and LWORD
s_ADDRlatched <= vme_addr_i;
s_LWORDlatched_n <= vme_lword_n_i;
s_AMlatched <= vme_am_i;
vme_idff_addr <= vme_addr_i;
vme_idff_lword_n <= vme_lword_n_i;
vme_idff_am <= vme_am_i;
if vme_iack_n_i = '1' then
-- ANSI/VITA 1-1994 Rule 2.11
......@@ -407,17 +407,17 @@ begin
-- Reformat address according to the mode (A16, A24, A32)
-- FIXME: not needed if ADEM are correctly reduced to not compare
-- MSBs of A16 or A24 addresses.
s_vme_addr_reg <= s_ADDRlatched;
vme_odff_addr <= vme_idff_addr;
case s_addressingType is
when A16 =>
s_vme_addr_reg (31 downto 16) <= (others => '0'); -- A16
vme_odff_addr (31 downto 16) <= (others => '0'); -- A16
when A24 | A24_BLT | A24_MBLT =>
s_vme_addr_reg (31 downto 24) <= (others => '0'); -- A24
vme_odff_addr (31 downto 24) <= (others => '0'); -- A24
when others =>
null; -- A32
end case;
s_vme_lword_n_reg <= s_LWORDlatched_n;
vme_odff_lword_n <= vme_idff_lword_n;
-- Address is not yet decoded.
s_card_sel <= '0';
......@@ -431,15 +431,15 @@ begin
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
-- capability.
if s_LWORDlatched_n = '0' and s_ADDRlatched(1) = '1' then
if vme_idff_lword_n = '0' and vme_idff_addr(1) = '1' then
-- unaligned.
s_mainFSMstate <= WAIT_END;
elsif g_VME32 = False and s_LWORDlatched_n = '0' then
elsif g_VME32 = False and vme_idff_lword_n = '0' then
-- No 32bit access on VME16.
s_mainFSMstate <= WAIT_END;
else
if s_ADDRlatched(23 downto 19) = bar_i
and s_AMlatched = c_AM_CR_CSR
if vme_idff_addr(23 downto 19) = bar_i
and vme_idff_am = c_AM_CR_CSR
then
-- conf_sel = '1' it means CR/CSR space addressed
s_conf_sel <= '1';
......@@ -455,7 +455,7 @@ begin
-- Wait for DS in parallel.
if vme_ds_n_i /= "11" then
s_WRITElatched_n <= vme_write_n_i;
vme_idff_write_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
......@@ -466,7 +466,7 @@ begin
-- card_sel = '1' it means WB application addressed
s_card_sel <= '1';
-- Keep only the local part of the address.
s_vme_addr_reg <= addr_decoder_i;
vme_odff_addr <= addr_decoder_i;
if vme_ds_n_i = "11" then
s_mainFSMstate <= WAIT_FOR_DS;
......@@ -490,7 +490,7 @@ begin
-- if vme_ds_n_i /= "11" then
-- -- ANSI/VITA 1-1994 Table 4-1
-- -- For interrupts ack, the handler MUST NOT drive WRITE* low
-- s_WRITElatched_n <= vme_write_n_i;
-- vme_idff_write_n <= vme_write_n_i;
-- if s_DS_latch_count /= 0 then
-- s_DS_latch_count <= s_DS_latch_count - 1;
-- end if;
......@@ -499,7 +499,6 @@ begin
-- s_mainFSMstate <= WAIT_FOR_DS;
-- end if;
if s_wb_prefetch = '1'
and s_transferType = MBLT
and s_WBFSMstate = IDLE
......@@ -529,7 +528,7 @@ begin
then
-- ANSI/VITA 1-1994 Table 4-1
-- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= vme_write_n_i;
vme_idff_write_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
......@@ -554,12 +553,10 @@ begin
vme_dtack_oe_o <= '1';
s_data_on_bus <= '0';
end if;
elsif vme_ds_n_i /= "11" and s_wb_prefetch /= '1' then
-- ANSI/VITA 1-1994 Table 4-1
-- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= vme_write_n_i;
vme_idff_write_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
......@@ -575,14 +572,14 @@ begin
-- ANSI/VITA 1-1994 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT
-- drive the D[] lines until DSA* goes low.
vme_data_dir_o <= s_WRITElatched_n;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= '0';
if g_VME32 and s_transferType = MBLT then
s_dataPhase <= '1';
-- Start with D[31..0] when writing, but D[63..32] when reading.
s_vme_addr_reg(2) <= not s_WRITElatched_n;
vme_odff_addr(2) <= not vme_idff_write_n;
else
s_dataPhase <= '0';
end if;
......@@ -603,52 +600,52 @@ begin
end if;
-- Read DS (which is delayed to avoid metastability).
s_DSlatched_n <= vme_ds_n_i;
vme_idff_ds_n <= vme_ds_n_i;
-- Read DATA (which are stable)
s_locDataIn(63 downto 33) <= vme_addr_i;
s_LWORDlatched_n <= vme_lword_n_i;
s_vme_data_reg <= vme_data_i;
vme_idff_lword_n <= vme_lword_n_i;
vme_odff_data <= vme_data_i;
else
s_mainFSMstate <= LATCH_DS;
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
when CHECK_TRANSFER_TYPE =>
vme_data_dir_o <= s_WRITElatched_n;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= '0';
s_dataPhase <= s_dataPhase;
-- vme_addr is an output during MBLT *read* data transfer.
if s_transferType = MBLT and s_WRITElatched_n = '1' and g_VME32 then
s_vme_addr_dir <= '1';
if s_transferType = MBLT and vme_idff_write_n = '1' and g_VME32 then
vme_odff_addr_dir <= '1';
else
s_vme_addr_dir <= '0';
vme_odff_addr_dir <= '0';
end if;
s_locDataIn(32) <= s_LWORDlatched_n;
s_locDataIn(31 downto 0) <= s_vme_data_reg;
if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' and g_VME32 then
s_locDataIn(32) <= vme_idff_lword_n;
s_locDataIn(31 downto 0) <= vme_odff_data;
if vme_odff_lword_n = '1' and vme_odff_addr(1) = '0' and g_VME32 then
-- Word/byte access with A1=0
s_locDataIn(31 downto 16) <= s_vme_data_reg(15 downto 0);
s_locDataIn(31 downto 16) <= vme_odff_data(15 downto 0);
end if;
-- Translate DS+LWORD+ADDR to WB byte selects
if not g_VME32 then
-- 16bit access on a 16bit bus.
wb_sel_o (3 downto 2) <= "00";
wb_sel_o (1 downto 0) <= not s_DSlatched_n;
elsif s_vme_lword_n_reg = '0' then
wb_sel_o (1 downto 0) <= not vme_idff_ds_n;
elsif vme_odff_lword_n = '0' then
-- 32bit access
wb_sel_o <= "1111";
else
-- 16bit access on a 32bit bus.
wb_sel_o <= "0000";
case s_vme_addr_reg(1) is
case vme_odff_addr(1) is
when '0' =>
wb_sel_o (3 downto 2) <= not s_DSlatched_n;
wb_sel_o (3 downto 2) <= not vme_idff_ds_n;
when '1' =>
wb_sel_o (1 downto 0) <= not s_DSlatched_n;
wb_sel_o (1 downto 0) <= not vme_idff_ds_n;
when others =>
null;
end case;
......@@ -658,7 +655,7 @@ begin
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
-- capability.
if s_vme_lword_n_reg = '0' and s_DSlatched_n /= "00" then
if vme_odff_lword_n = '0' and vme_idff_ds_n /= "00" then
-- unaligned.
s_mainFSMstate <= WAIT_END;
elsif s_WBFSMstate = IDLE and s_wb_prefetch = '1' then
......@@ -673,9 +670,9 @@ begin
s_conf_req <= s_conf_sel;
end if;
-- Needed to add this here because it must be availible sooner
-- Needed to add this here because it must be available sooner
-- for prefetch. May be reduntant at CTT
if g_VME32 and s_vme_lword_n_reg = '0' and s_WRITElatched_n = '1' then
if g_VME32 and vme_odff_lword_n = '0' and vme_idff_write_n = '1' then
if s_transferType = MBLT then
-- 64 bit
addr_word_incr := 4;
......@@ -689,8 +686,8 @@ begin
when DATA_TO_BUS =>
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= vme_odff_addr_dir;
if g_VME32 then
-- only for MBLT
......@@ -704,7 +701,7 @@ begin
-- DTACK* low before it drives D[].
s_mainFSMstate <= DTACK_LOW;
if s_WRITElatched_n = '1' then
if vme_idff_write_n = '1' then
-- if it is a read, but not MBLT or 1st MBLT data
vme_dtack_n_o <= '0';
end if;
......@@ -716,8 +713,8 @@ begin
when DTACK_LOW =>
-- Think this block can execute when moving from WAIT_WB_FSM to DTACK_LOW
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= vme_odff_addr_dir;
-- Set DTACK (or retry or berr)
if s_card_sel = '1' and s_err = '1' then
......@@ -783,9 +780,9 @@ begin
when INCREMENT_ADDR =>
vme_dtack_oe_o <= '1';
vme_addr_dir_o <= s_vme_addr_dir;
vme_addr_dir_o <= vme_odff_addr_dir;
if g_VME32 and s_vme_lword_n_reg = '0' then
if g_VME32 and vme_odff_lword_n = '0' then
if s_transferType = MBLT then
-- 64 bit
addr_word_incr := 4;
......@@ -794,7 +791,7 @@ begin
addr_word_incr := 2;
end if;
else
if s_DSlatched_n (0) = '0' then
if vme_idff_ds_n (0) = '0' then
-- Next word for D16 or D08(O)
addr_word_incr := 1;
else
......@@ -804,8 +801,8 @@ begin
-- Only increment within the window, don't check the limit.
-- BLT --> limit = 256 bytes (rule 2.12a ANSI/VITA 1-1994)
-- MBLT --> limit = 2048 bytes (rule 2.78 ANSI/VITA 1-1994)
s_vme_addr_reg (11 downto 1) <= std_logic_vector
(unsigned(s_vme_addr_reg (11 downto 1)) + addr_word_incr);
vme_odff_addr (11 downto 1) <= std_logic_vector
(unsigned(vme_odff_addr (11 downto 1)) + addr_word_incr);
s_mainFSMstate <= WAIT_FOR_DS;
if s_wb_prefetch = '1' then
......@@ -834,7 +831,7 @@ begin
when IRQ_CHECK =>
if vme_iackin_n_i = '0' then
if s_ADDRlatched(3 downto 1) = int_level_i
if vme_idff_addr(3 downto 1) = int_level_i
and irq_pending_i = '1'
then
-- That's for us
......@@ -866,14 +863,14 @@ begin
-- Update what WB FSM prepared
s_dataPhase <= s_wb_dataPhase;
if s_wb_done = '1' then -- Solving the unalligned data during write
if s_wb_done = '1' then -- Solving the unaligned data during write
s_locDataIn <= s_wb_locDataIn;
elsif s_WBFSMstate = MEMORY_PAUSE then
s_locDataIn <= s_wb_locDataIn;
end if;
s_locDataOut <= s_wb_locDataOut;
s_vme_addr_reg <= s_wb_vme_addr_reg; --may be possible only 1 bit
vme_odff_addr <= s_wb_vme_addr_reg; --may be possible only 1 bit
s_wb_start <= '0';
......@@ -881,7 +878,7 @@ begin
s_mainFSMstate <= DATA_TO_BUS;
if (s_transferType = MBLT) and (s_WRITElatched_n = '1') then
if (s_transferType = MBLT) and (vme_idff_write_n = '1') then
-- MBLT read (Might want to specify exactly the one MBLT of
-- interest)
s_wb_prefetch <= '1'; -- needs to be reset somewhere
......@@ -891,20 +888,20 @@ begin
-- Only increment within the window, don't check the limit.
-- MBLT --> limit = 2048 bytes (rule 2.78 ANSI/VITA 1-1994)
if s_wb_first_pf = '1' then
s_vme_addr_reg (11 downto 1) <= std_logic_vector
(unsigned(s_vme_addr_reg (11 downto 1)) + addr_word_incr/2 ); -- Only for first prefetch, @ A32 MBLT 64
vme_odff_addr (11 downto 1) <= std_logic_vector
(unsigned(vme_odff_addr (11 downto 1)) + addr_word_incr/2 ); -- Only for first prefetch, @ A32 MBLT 64
s_wb_first_pf <= '0';
else
null; -- the other MAIN FSM states will prepare the adress in case of not first prefetch
end if;
end if;
if s_WRITElatched_n = '1' and s_wb_prefetch = '0' then
if vme_idff_write_n = '1' and s_wb_prefetch = '0' then
-- if it is a read, but not MBLT or 1st MBLT data
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= vme_odff_addr_dir;
if g_VME32 then
-- only for MBLT
......@@ -917,7 +914,7 @@ begin
elsif ((s_wb_DTACK_LOW = '1')
or ((s_WBFSMstate = MEMORY_REQ) and (s_DataPhase = '0')
and (s_WRITElatched_n = '0') and (wb_ack_i = '1')))
and (vme_idff_write_n = '0') and (wb_ack_i = '1')))
then
-- added or to not loose a cycle for acknowledging.
-- Solving for write only 1st.
......@@ -984,8 +981,8 @@ begin
if s_WBFSMstate = MEMORY_REQ then
-- We want this state machine to drive them, but under the same condition
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= vme_odff_addr_dir;
end if;
end if;
end if;
......@@ -1024,32 +1021,29 @@ begin
-- Latching some important signals from the main FSM
s_wb_dataPhase <= s_dataPhase;
s_wb_vme_addr_reg <= s_vme_addr_reg;
s_wb_vme_addr_reg <= vme_odff_addr;
s_wb_locDataIn <= s_locDataIn;
if s_wb_start /= '1' then
if vme_ds_n_i /= "11" and s_wb_prefetch = '1' and s_pom = '1' then
-- Start WB cycle.
wb_cyc_o <= s_card_sel;
wb_stb_o <= s_card_sel;
s_stall <= '1'; -- Can stall
s_err <= '0';
s_WBFSMstate <= MEMORY_REQ;
s_wb_dataPhase <= '1';
else
-- Wait in IDLE until s_wb_start = '1'
s_WBFSMstate <= IDLE;
end if;
else
if s_wb_start = '1' then
-- Start WB cycle.
wb_cyc_o <= s_card_sel;
wb_stb_o <= s_card_sel;
s_stall <= '1'; -- Can stall
s_err <= '0';
s_WBFSMstate <= MEMORY_REQ;
elsif vme_ds_n_i /= "11" and s_wb_prefetch = '1' and s_pom = '1'
then
-- Start WB cycle.
wb_cyc_o <= s_card_sel;
wb_stb_o <= s_card_sel;
s_stall <= '1'; -- Can stall
s_err <= '0';
s_WBFSMstate <= MEMORY_REQ;
s_wb_dataPhase <= '1';
else
-- Wait in IDLE until s_wb_start = '1'
s_WBFSMstate <= IDLE;
end if;
when MEMORY_REQ =>
......@@ -1083,7 +1077,7 @@ begin
s_wb_DTACK_LOW <= '1';
s_WBFSMstate <= IDLE;
elsif s_WRITElatched_n = '0' then
elsif vme_idff_write_n = '0' then
-- Write cycle.
if s_wb_dataPhase = '1' then
-- MBLT
......@@ -1107,7 +1101,7 @@ begin
s_wb_locDataOut(63 downto 32) <= s_wb_locDataOut(31 downto 0);
s_wb_locDataOut(31 downto 0) <= (others => '0');
if s_card_sel = '1' then
if g_VME32 and s_vme_lword_n_reg = '1' and s_wb_vme_addr_reg(1) = '0' then
if g_VME32 and vme_odff_lword_n = '1' and s_wb_vme_addr_reg(1) = '0' then
-- Word/byte access with A1 = 0 on a 32bit bus.
s_wb_locDataOut(15 downto 0) <= wb_dat_i(31 downto 16);
else
......@@ -1146,11 +1140,6 @@ begin
else
s_WBFSMstate <= MEMORY_PAUSE;
end if;
when others =>
-- No-op, wait until AS is released.
null;
end case;
end if;
end if;
......@@ -1164,13 +1153,13 @@ begin
-- g_wb_addr32: if g_VME32 generate
-- with g_WB_GRANULARITY select
-- wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
-- s_vme_addr_reg(31 downto 2) & "00" when BYTE;
-- wb_adr_o <= "00" & vme_odff_addr(31 downto 2) when WORD,
-- vme_odff_addr(31 downto 2) & "00" when BYTE;
-- end generate;
-- g_wb_addr16: if not g_VME32 generate
-- with g_WB_GRANULARITY select
-- wb_adr_o <= "0" & s_vme_addr_reg(31 downto 1) when WORD,
-- s_vme_addr_reg(31 downto 1) & "0" when BYTE;
-- wb_adr_o <= "0" & vme_odff_addr(31 downto 1) when WORD,
-- vme_odff_addr(31 downto 1) & "0" when BYTE;
-- end generate;
......@@ -1185,20 +1174,20 @@ begin
-- -- wb_adr_o <= "0" & s_wb_vme_addr_reg(31 downto 1) when WORD,
-- -- s_wb_vme_addr_reg(31 downto 1) & "0" when BYTE;
-- -- end generate;
process (s_vme_addr_reg, s_wb_vme_addr_reg)
process (vme_odff_addr, s_wb_vme_addr_reg)
begin
if (s_wb_prefetch = '0') then
if g_VME32 then
if g_WB_GRANULARITY = WORD then
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2);
wb_adr_o <= "00" & vme_odff_addr(31 downto 2);
elsif g_WB_GRANULARITY = BYTE then
wb_adr_o <= s_vme_addr_reg(31 downto 2) & "00";
wb_adr_o <= vme_odff_addr(31 downto 2) & "00";
end if;
elsif(not g_VME32) then
if g_WB_GRANULARITY = WORD then
wb_adr_o <= "0" & s_vme_addr_reg(31 downto 1);
wb_adr_o <= "0" & vme_odff_addr(31 downto 1);
elsif g_WB_GRANULARITY = BYTE then
wb_adr_o <= s_vme_addr_reg(31 downto 1) & "0";
wb_adr_o <= vme_odff_addr(31 downto 1) & "0";
end if;
end if;
elsif (s_wb_prefetch = '1') then
......@@ -1218,18 +1207,18 @@ begin
end if;
end process;
wb_we_o <= not s_WRITElatched_n;
wb_we_o <= not vme_idff_write_n;
wb_dat_o <= s_locDataIn(31 downto 0);
-- Function Decoder
addr_decoder_o <= s_vme_addr_reg;
am_o <= s_AMlatched;
addr_decoder_o <= vme_odff_addr;
am_o <= vme_idff_am;
-- CR/CSR In/Out
cr_csr_data_o <= s_locDataIn(7 downto 0);
cr_csr_addr_o <= s_vme_addr_reg(18 downto 2);
cr_csr_addr_o <= vme_odff_addr(18 downto 2);
cr_csr_we_o <= '1' when s_conf_req = '1' and
s_WRITElatched_n = '0'
vme_idff_write_n = '0'
else '0';
end rtl;
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