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VME64x core
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VME64x core
Commits
2f426d19
Commit
2f426d19
authored
Nov 30, 2017
by
Tristan Gingold
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Width of irq_level_i is 3.
parent
b98546ca
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5 changed files
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8 additions
and
16 deletions
+8
-16
vme64x_core.vhd
hdl/rtl/vme64x_core.vhd
+1
-1
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+1
-1
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+3
-3
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+2
-10
top_tb.vhd
hdl/testbench/simple_tb/top_tb.vhd
+1
-1
No files found.
hdl/rtl/vme64x_core.vhd
View file @
2f426d19
...
@@ -93,7 +93,7 @@ entity vme64x_core is
...
@@ -93,7 +93,7 @@ entity vme64x_core is
wb_we_o
:
out
std_logic
;
wb_we_o
:
out
std_logic
;
wb_dat_o
:
out
t_wishbone_data
;
wb_dat_o
:
out
t_wishbone_data
;
irq_ack_o
:
out
std_logic
;
irq_ack_o
:
out
std_logic
;
irq_level_i
:
std_logic_vector
(
7
downto
0
);
irq_level_i
:
std_logic_vector
(
2
downto
0
);
irq_vector_i
:
std_logic_vector
(
7
downto
0
);
irq_vector_i
:
std_logic_vector
(
7
downto
0
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
std_logic_vector
(
7
downto
0
);
user_csr_data_i
:
std_logic_vector
(
7
downto
0
);
...
...
hdl/rtl/vme64x_pkg.vhd
View file @
2f426d19
...
@@ -222,7 +222,7 @@ package vme64x_pkg is
...
@@ -222,7 +222,7 @@ package vme64x_pkg is
irq_ack_o
:
out
std_logic
;
irq_ack_o
:
out
std_logic
;
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_level_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
...
...
hdl/rtl/vme_bus.vhd
View file @
2f426d19
hdl/rtl/xvme64x_core.vhd
View file @
2f426d19
...
@@ -34,14 +34,6 @@
...
@@ -34,14 +34,6 @@
-- | |________________| |________| |___________________| |
-- | |________________| |________| |___________________| |
-- |_________________________________________________________|
-- |_________________________________________________________|
--
--
-- This core complies with the VME64x specifications and allows "plug and
-- play" configuration of VME crates.
-- The base address is setted by the Geographical lines.
-- The base address can't be setted by hand with the switches on the board.
-- If the core is used in an old VME system without GA lines, the core should
-- be provided with a logic that detects if GA = "11111" and if it is the base
-- address of the module, this logic should derive the GA from the switches on
-- the board.
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- metastability problem.
-- metastability problem.
-- All the output signals on the WB bus are registered.
-- All the output signals on the WB bus are registered.
...
@@ -181,7 +173,7 @@ entity xvme64x_core is
...
@@ -181,7 +173,7 @@ entity xvme64x_core is
-- User CSR
-- User CSR
-- The following signals are used when g_USER_CSR_EXT = true
-- The following signals are used when g_USER_CSR_EXT = true
-- otherwise they are connected to the internal user CSR.
-- otherwise they are connected to the internal user CSR.
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_level_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
...
@@ -446,7 +438,7 @@ begin
...
@@ -446,7 +438,7 @@ begin
)
)
port
map
(
port
map
(
clk_i
=>
clk_i
,
clk_i
=>
clk_i
,
rst_n_i
=>
s_reset_n
,
-- asserted when low
rst_n_i
=>
s_reset_n
,
INT_Level_i
=>
s_irq_level
,
INT_Level_i
=>
s_irq_level
,
INT_Req_i
=>
wb_i
.
int
,
INT_Req_i
=>
wb_i
.
int
,
irq_pending_o
=>
s_irq_pending
,
irq_pending_o
=>
s_irq_pending
,
...
...
hdl/testbench/simple_tb/top_tb.vhd
View file @
2f426d19
...
@@ -237,7 +237,7 @@ architecture behaviour of top_tb is
...
@@ -237,7 +237,7 @@ architecture behaviour of top_tb is
signal
WE_o
:
std_logic
;
signal
WE_o
:
std_logic
;
signal
STALL_i
:
std_logic
;
signal
STALL_i
:
std_logic
;
signal
rty_i
:
std_logic
:
=
'0'
;
signal
rty_i
:
std_logic
:
=
'0'
;
signal
irq_level_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
irq_level_i
:
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
signal
irq_vector_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
irq_vector_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
user_csr_addr_o
:
std_logic_vector
(
18
downto
2
);
signal
user_csr_addr_o
:
std_logic_vector
(
18
downto
2
);
signal
user_csr_data_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
user_csr_data_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
...
...
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