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VME64x core
Commits
56ee00ac
Commit
56ee00ac
authored
Sep 21, 2017
by
Tristan Gingold
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Adjust AMCAP bits (remove unsupported modes).
parent
7e121be4
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4 changed files
with
28 additions
and
28 deletions
+28
-28
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+24
-2
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+0
-22
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+2
-2
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+2
-2
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
56ee00ac
...
...
@@ -154,12 +154,12 @@ entity VME64xCore_Top is
-- Function 0
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
bb
00"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
ee
00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 1
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
bb
000000_00000000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
ee
000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
-- Function 2
...
...
@@ -340,7 +340,29 @@ architecture RTL of VME64xCore_Top is
g_F0_DAWPR
,
g_F1_DAWPR
,
g_F2_DAWPR
,
g_F3_DAWPR
,
g_F4_DAWPR
,
g_F5_DAWPR
,
g_F6_DAWPR
,
g_F7_DAWPR
);
-- List of supported AM.
constant
c_AMCAP_ALLOWED
:
std_logic_vector
(
63
downto
0
)
:
=
(
16
#
3
d
#
to
16
#
3
f
#
=>
'1'
,
-- A24
16
#
39
#
to
16
#
3
b
#
=>
'1'
,
16
#
2
d
#
|
16
#
29
#
=>
'1'
,
-- A16
16
#
0
d
#
to
16
#
0
f
#
=>
'1'
,
-- A32
16
#
09
#
to
16
#
0
b
#
=>
'1'
,
others
=>
'0'
);
begin
-- Check for invalid bits in ADEM/AMCAP
gen_gchecks
:
for
i
in
7
downto
0
generate
assert
c_ADEM
(
i
)(
c_ADEM_FAF
)
=
'0'
report
"FAF bit set in ADEM"
severity
failure
;
assert
c_ADEM
(
i
)(
c_ADEM_DFS
)
=
'0'
report
"DFS bit set in ADEM"
severity
failure
;
assert
c_ADEM
(
i
)(
c_ADEM_EFM
)
=
'0'
report
"EFM bit set in ADEM"
severity
failure
;
assert
(
c_AMCAP
(
i
)
and
c_AMCAP_ALLOWED
)
=
c_AMCAP
(
i
)
report
"bit set in AMCAP for not supported AM"
severity
failure
;
end
generate
;
------------------------------------------------------------------------------
-- Metastability
------------------------------------------------------------------------------
...
...
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
56ee00ac
...
...
@@ -73,15 +73,6 @@ architecture rtl of VME_Funct_Match is
signal
s_function
:
std_logic_vector
(
7
downto
0
);
signal
s_ader_am_valid
:
std_logic_vector
(
7
downto
0
);
-- List of supported AM.
constant
c_AMCAP_ALLOWED
:
std_logic_vector
(
63
downto
0
)
:
=
(
16
#
3
d
#
to
16
#
3
f
#
=>
'1'
,
-- A24
16
#
39
#
to
16
#
3
b
#
=>
'1'
,
16
#
2
d
#
|
16
#
29
#
=>
'1'
,
-- A16
16
#
0
d
#
to
16
#
0
f
#
=>
'1'
,
-- A32
16
#
09
#
to
16
#
0
b
#
=>
'1'
,
others
=>
'0'
);
------------------------------------------------------------------------------
-- Generate EFD lookup table
------------------------------------------------------------------------------
...
...
@@ -106,19 +97,6 @@ architecture rtl of VME_Funct_Match is
constant
c_EFD_LUT
:
t_efd_lut
:
=
f_gen_efd_lut
;
begin
-- Check for invalid bits in ADEM/AMCAP
gen_gchecks
:
for
i
in
7
downto
0
generate
assert
g_ADEM
(
i
)(
c_ADEM_FAF
)
=
'0'
report
"FAF bit set in ADEM"
severity
error
;
assert
g_ADEM
(
i
)(
c_ADEM_DFS
)
=
'0'
report
"DFS bit set in ADEM"
severity
error
;
assert
g_ADEM
(
i
)(
c_ADEM_EFM
)
=
'0'
report
"EFM bit set in ADEM"
severity
error
;
assert
(
g_AMCAP
(
i
)
and
c_AMCAP_ALLOWED
)
=
g_AMCAP
(
i
)
report
"bit set in AMCAP for not supported AM"
severity
error
;
end
generate
;
------------------------------------------------------------------------------
-- Address and AM comparators
------------------------------------------------------------------------------
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
56ee00ac
...
...
@@ -136,10 +136,10 @@ package vme64x_pack is
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
bb
00"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
ee
00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
bb
000000_00000000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
ee
000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
...
...
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
56ee00ac
...
...
@@ -63,11 +63,11 @@ entity xvme64x_core is
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
bb
00"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000
ee
00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
bb
000000_00000000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"
ee
000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
...
...
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