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VME64x core
Commits
88d3fe21
Commit
88d3fe21
authored
Oct 02, 2017
by
Tristan Gingold
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Remove function_o
parent
26d4d453
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7 changed files
with
4 additions
and
48 deletions
+4
-48
VME64x_v2_specs.txt
documentation/specifications/VME64x_v2_specs.txt
+0
-1
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+1
-9
VME_Funct_Match.vhd
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+2
-30
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+0
-1
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+0
-3
xvme64x_core_pkg.vhd
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+0
-1
top_tb.vhd
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
+1
-3
No files found.
documentation/specifications/VME64x_v2_specs.txt
View file @
88d3fe21
...
...
@@ -28,7 +28,6 @@ Changes
* WB data bus is 32 bit
* Internal component declarations removed.
* Number of sync registers (for async inputs) is configurable. Default is 2.
* Port function_o to be removed.
VME interface
-------------
...
...
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
88d3fe21
...
...
@@ -256,9 +256,6 @@ entity VME64xCore_Top is
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
-- Functions
function_o
:
out
std_logic_vector
(
3
downto
0
);
-- IRQ Generator
irq_ack_o
:
out
std_logic
;
-- when the IRQ controller acknowledges the
-- Interrupt cycle it sends a pulse to the
...
...
@@ -305,7 +302,6 @@ architecture RTL of VME64xCore_Top is
signal
s_decode_start
:
std_logic
;
signal
s_decode_done
:
std_logic
;
signal
s_decode_sel
:
std_logic
;
signal
s_function
:
std_logic_vector
(
2
downto
0
);
signal
s_am
:
std_logic_vector
(
5
downto
0
);
-- Oversampled input signals
...
...
@@ -473,13 +469,9 @@ begin
am_i
=>
s_am
,
ader_i
=>
s_ader
,
decode_sel_o
=>
s_decode_sel
,
decode_done_o
=>
s_decode_done
,
function_o
=>
s_function
decode_done_o
=>
s_decode_done
);
function_o
(
2
downto
0
)
<=
s_function
;
function_o
(
3
)
<=
'0'
;
-- FIXME: purpose of that bit ?
------------------------------------------------------------------------------
-- Output
------------------------------------------------------------------------------
...
...
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @
88d3fe21
...
...
@@ -54,12 +54,10 @@ entity VME_Funct_Match is
ader_i
:
in
t_ader_array
(
0
to
7
);
-- Set when a function is selected
(ie function_o is valid)
.
-- Set when a function is selected.
decode_sel_o
:
out
std_logic
;
-- Set when sel_o is valid (decoding is done).
decode_done_o
:
out
std_logic
;
-- Selected function.
function_o
:
out
std_logic_vector
(
2
downto
0
)
decode_done_o
:
out
std_logic
);
end
VME_Funct_Match
;
...
...
@@ -72,30 +70,6 @@ architecture rtl of VME_Funct_Match is
-- Selected function
signal
s_function
:
std_logic_vector
(
7
downto
0
);
signal
s_ader_am_valid
:
std_logic_vector
(
7
downto
0
);
------------------------------------------------------------------------------
-- Generate EFD lookup table
------------------------------------------------------------------------------
type
t_efd_lut
is
array
(
0
to
7
)
of
std_logic_vector
(
2
downto
0
);
function
f_gen_efd_lut
return
t_efd_lut
is
variable
lut
:
t_efd_lut
;
begin
lut
(
0
)
:
=
"000"
;
for
i
in
1
to
7
loop
if
g_ADEM
(
i
-1
)(
c_ADEM_EFD
)
=
'1'
then
lut
(
i
)
:
=
lut
(
i
-
1
);
else
lut
(
i
)
:
=
std_logic_vector
(
to_unsigned
(
i
,
3
));
end
if
;
end
loop
;
return
lut
;
end
function
;
-- Map from function defined by address to real function. Handle extra
-- decoders.
constant
c_EFD_LUT
:
t_efd_lut
:
=
f_gen_efd_lut
;
begin
------------------------------------------------------------------------------
-- Address and AM comparators
...
...
@@ -145,7 +119,6 @@ begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
or
s_decode_start_1
=
'0'
then
addr_o
<=
(
others
=>
'0'
);
function_o
<=
(
others
=>
'0'
);
decode_done_o
<=
'0'
;
decode_sel_o
<=
'0'
;
else
...
...
@@ -153,7 +126,6 @@ begin
decode_done_o
<=
'1'
;
if
s_function_sel_valid
=
'1'
then
function_o
<=
c_EFD_LUT
(
s_function_sel
);
mask
:
=
(
others
=>
'0'
);
mask
(
c_ADEM_M
)
:
=
g_adem
(
s_function_sel
)(
c_ADEM_M
);
addr_o
<=
addr_i
and
not
mask
;
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
88d3fe21
...
...
@@ -207,7 +207,6 @@ package vme64x_pack is
user_csr_we_o
:
out
std_logic
;
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
irq_ack_o
:
out
std_logic
;
irq_i
:
in
std_logic
);
...
...
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
88d3fe21
...
...
@@ -134,7 +134,6 @@ entity xvme64x_core is
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -240,8 +239,6 @@ begin -- wrapper
WE_o
=>
master_o
.
we
,
STALL_i
=>
master_i
.
stall
,
function_o
=>
function_o
,
user_csr_addr_o
=>
user_csr_addr_o
,
user_csr_data_i
=>
user_csr_data_i
,
user_csr_data_o
=>
user_csr_data_o
,
...
...
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @
88d3fe21
...
...
@@ -156,7 +156,6 @@ package xvme64x_core_pkg is
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
...
...
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @
88d3fe21
entity
top_tb
is
generic
(
scenario
:
natural
range
0
to
7
:
=
7
);
generic
(
scenario
:
natural
range
0
to
7
:
=
6
);
end
;
library
ieee
;
...
...
@@ -218,7 +218,6 @@ architecture behaviour of top_tb is
signal
user_csr_we_o
:
std_logic
;
signal
user_cr_addr_o
:
std_logic_vector
(
18
downto
2
);
signal
user_cr_data_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
function_o
:
std_logic_vector
(
3
downto
0
);
signal
irq_ack_o
:
std_logic
;
signal
irq_i
:
std_logic
;
...
...
@@ -285,7 +284,6 @@ begin
user_csr_we_o
=>
user_csr_we_o
,
user_cr_addr_o
=>
user_cr_addr_o
,
user_cr_data_i
=>
user_cr_data_i
,
function_o
=>
function_o
,
irq_ack_o
=>
irq_ack_o
,
irq_i
=>
irq_i
);
...
...
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