Compact Universal Timing Endpoint Based on WR
The Cute-WR project aims to build a self-contained White Rabbit Node implementation on a FMC(FPGA Mezzanine Card) form factor. The idea is to have a compact, low-cost and full functional WR node, it can be plugged to any carrier board with FMC connectors and brings the WR synchronization performance to the carrier board. The Cute-WR series has been used in timing distribution, synchronous DAQ frontends and other applications!
After ten years development, several generations of Cute-WR cards have been built. A short introduction about the Cute-WR series and their application has been given on the 13th WR workshop.
Type | Description | Status |
---|---|---|
Cute-WR | the first generation with Spartan6 FPGA, it proves the feasibility of the idea. | obsolete |
Cute-WR-DP | Dual port version of Cute-WR with Spartan6 FPGA that can support different operation modes | obsolete |
Cute-WR-A7 | The successor of the CUTE-WR-DP with Xilinx Artix7 FPGA. It inherits similar interfaces from Cute-WR-DP: two SFP ports, two SMA/LEMO connectors, FMC form factor with LPC connector, etc. The timing of signals from SMA can be further tuned with a fine delay chip. Due to the limited panel space, the USB-console can only be provided on carrier board. | Active |
Cute-WR-A7-Lite | lite version of Cute-WR-A7 to replace one SFP with USB-serial console that makes it more complete. The fine delay chip is removed to reduce cost. | Active |