cgen_vhdl: fixed f_x_to_zero(std_logic_vector) for Mentor Precision

ed4e1500 · Grzegorz Daniluk · ff1f5a98 · ed4e1500 · ed4e1500
Commit ed4e1500 authored Aug 06, 2015 by Grzegorz Daniluk
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Showing with 6 additions and 6 deletions

cgen_vhdl.lua cgen_vhdl.lua +3 -3

wbgen2 wbgen2 +3 -3

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--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -114,10 +114,10 @@ function cgen_vhdl_package()
 	 emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
   emit("begin");
   emit("for i in 0 to x'length-1 loop");
-   emit("if(x(i) = 'X' or x(i) = 'U') then");
-   emit("tmp(i):= '0';");
+   emit("if x(i) = '1' then");
+   emit("tmp(i):= '1';");
   emit("else");
-   emit("tmp(i):=x(i);");
+   emit("tmp(i):= '0';");
   emit("end if; ");
   emit("end loop; ");
   emit("return tmp;");

--- a/wbgen2
+++ b/wbgen2
@@ -899,10 +899,10 @@ emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
 emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
 emit("begin");
 emit("for i in 0 to x'length-1 loop");
-emit("if(x(i) = 'X' or x(i) = 'U') then");
-emit("tmp(i):= '0';");
+emit("if x(i) = '1' then");
+emit("tmp(i):= '1';");
 emit("else");
-emit("tmp(i):=x(i);");
+emit("tmp(i):= '0';");
 emit("end if; ");
 emit("end loop; ");
 emit("return tmp;");