Peripheral block
Peripheral* block contains a single Wishbone peripheral. It's the
main (top-level) block in each WB file. Peripheral block may contain any
number
of registers, FIFO registers, RAMs and up to 32 interrupt request lines.
Block-specific attributes*
| * Attribute *| Status| * Description *|
|hdl_entity
|mandatory|Name of the VHDL entity or Verilog module of the
slave core to be generated.|