1. RAM memory block
RAM block describes a dual-port RAM memory block with one port hooked to Wishbone bus, and the other port available for user application. Currently wbgen2 can produce:
- RAM blocks of power-of-2 sizes,
- variable data bus width (1 to 32/64 bits),
- configurable byte select lines.
RAMs are implemented using FPGA embedded memory blocks (BRAM in Xilinx, DCRAM in Altera).
1.1. Block-specific attributes
Attribute | Status | Description |
width = bits |
mandatory | Width of RAM data bus in bits. Valid values are from 1 to 32 (64). |
size = words |
mandatory | Number of words of length width in the RAM array. Must be a power of 2. |
byte_select = true/false |
optional | When set to true , RAM will be byte-addressable using byte select lines (wb_sel_i from the WB bus and ram_bwsel_i from the peripheral). Default value is false (no byte addressing) |
wrap_bits = num |
optional | Number of extra bits allocated from the address bus. Used for mirroring the memory block multiple times (if wrap_bits > 0, the memory will be mirrored 2^wrap_bits times in the Wishbone address space. Useful for implementing circular buffers. |
clock = clock signal |
optional | Clock for the peripheral port of memory block. If it isn't specified, wbgen2 will assume the peripheral-side port works in WB bus clock domain) |
access_bus , access_dev
|
mandatory | Specify how the memory block can be accessed from the bus and the peripheral. All combinations of READ_ONLY , READ_WRITE and WRITE_ONLY are supported (except for the nonsense ones: RO/RO or WO/WO). |