1. Register block
Register block describes a single memory-mapped register. wbgen2 supports variety of MMIO registers:
- SLV, SIGNED, UNSIGNED and BIT standard registers
- Bus-synchronous (operating with the same clock as the Wishbone bus) or asynchronous (using externally supplied clock). wbgen2 automatically provides all necessary synchronisation logic.
- MONOSTABLE registers which generate positive pulse upon write of
1
. - PASS_THROUGH registers
- Different access configurations
- Single register can contain fields of different types, clocks and access.
1.1. Block-specific attributes
Attribute | Status | Description |
align = num |
optional | Specifies the alignment of the register's address. When given, wbgen2 will align the hardware address (as seen on wb_addr_i bus) of this register to the nearest multiple of num . Default value of align is 1 - this means that the register is placed right after the previously defined register. See figure 1 for explanation. |
Note:* C/HDL prefixes of each register must be unique in the entire peripheral.
Figure 1.* Register address alignment:
2. Registers and fields
As we mentioned before, each register can contain multiple fields - an example is shown on figure 2. The number and size of fields is limited - total size of all fields in a single register (including alignment) must not exceed the data bus width. Each field can have a different #type and #access flags.
Figure 2.* Sample field layout in a register - 3 bit fields, one
8-bit unsigned
field and one 16-bit std_logic_vector
field.
2.1. Field types available for registers
Table 1.* Supported field types:
Type | Description |
BIT |
VHDL single bit of type std_logic
|
SLV |
VHDL field of type std_logic_vector
|
SIGNED |
VHDL field of type signed
|
UNSIGNED |
VHDL field of type unsigned
|
MONOSTABLE |
VHDL field of type std_logic , which generates a single clock cycle-long positive pulse when 1 is written to it. |
PASS_THROUGH |
special field, for which wbgen2 will generate only the address decoding logic, providing "wr" signal asserted high for a single bus clock cycle upon each write to the register. The written value will be fed to the corresponding SLV output directly from the Wishbone bus (just wires, no registers in between). |
Note:* for Verilog HDL output, there is no difference between
UNSIGNED
, SIGNED
and SLV
types, as Verilog doesn't differentiate
data types.
2.2. Field attributes
Table 2 shows all possible field attributes. Some of them may apply only to certain field types.
Table 2.* Field block attributes
Attribute | Status | Description |
type = BIT , SLV , SIGNED , UNSIGNED , MONOSTALBLE , PASS_THROUGH
|
mandatory | Type of the field. See table 1 for detailed description of all field types |
size = num |
mandatory for: SLV , PASS_THROUGH optional for: SIGNED , UNSIGNED
|
Size of the field in bits. For SIGNED and UNSIGNED types it's interchangeable with range attribute |
range = {min,max} |
optional for: SIGNED , UNSIGNED
|
Minimal and maximal possible field value. When provided, wbgen2 will automatically allocate the necessary number of bits. |
access_bus access_dev
|
optional | Field access flags. access_bus defines how the field can be accessed from the Wishbone bus, access_dev defines how the field can be accessed by the HDL entity connected to the slave core. Access flags can have one of these values: READ_ONLY , WRITE_ONLY , READ_WRITE . For the possible access combinations, see table 3. The default value is READ_WRITE (from the bus) and READ_ONLY (from the device). |
align = num |
optional | Alignment value for the field bit offset. When given, wbgen2 will align the offset of this field to the nearest multiple of num , in the same way it aligns register addresses. For example, the field COUNTER on figure 2 is 8-aligned. |
clock = clock input |
optional | Can be used to provide a clock port name if the field needs to operate in clock domain other than Wishbone bus clock. wbgen2 will automatically provide the necessary synchronisation logic. Clock names are automatically appended to slave core entity port list. Identical names are recognised as same clocks. If no clock attribute is provided, wbgen2 will generate field synchronous to Wishbone bus clock . |
load |
mandatory for RW/RW fields | Attribute is applicable only to RW/RW-accessed fields (e.g. the fields which are writable both from the bus and the device). It tells where the register will be physically placed. Currently there is only one possibility: LOAD_EXT , where the register is be placed outside the slave core and wired to reg_i , reg_o and reg_wr_o ports of the slave core. |
Note 1:* Due to limitations in the current version of wbgen2, asynchronous clock must always be faster than Wishbone clock for proper operation of synchronisation logic.
2.3. Field types cheatsheet.
Figures 2 & 3* show all possible combinations of field types, access flags & clocking options. Their make a quick cheatsheet for
Figure 2.* Supported BIT/SLV/SIGNED/UNSIGNED field attribute combinations.
Figure 3.* Supported MONOSTABLE/PASS_THROUGH field attribute combinations.
2.4. Register access latency.
Fields of different access modes and/or clocks have different read/write latencies which are shown on figures 2 & 3 (Cycle length). Be careful when putting fields with different cycle lengths in the same register - wbgen2 register R/W latency is always equal to the latency of the slowest field in the register. in order to minimize the latency, allocate asynchronous or RW/RW fields in separate registers.