wr_endpoint: fixed The Heisenbug(TM) in the TX PCS.

Explanation: - the busy flag is asserted whenever the TX state machine is not idle (e.g not in TX_IDLE or TX_COMMA state) or if the TX FIFO is not empty - since the TX FSM works in different clock domain than the system clock, where the busy flag is outputted, there is a synchronizer - The Heisenbug appeared in designs where TX clock is phase locked to the system clock (e.g. SPEC/SVEC). It was caused by a cross-clock domain setup time violation between the output of the LUT generating the tx_busy signal and the first flip flop of the synchronizer, which under certain conditions could permanently sample incorrect output of the LUT, resulting with the pcs_busy_o signal being stuck at 1 forever. - registering the TX clock domain busy signal removes glitches and fixes the problem.

wr_endpoint: fixed The Heisenbug(TM) in the TX PCS.
Explanation: - the busy flag is asserted whenever the TX state machine is not idle (e.g not in TX_IDLE or TX_COMMA state) or if the TX FIFO is not empty - since the TX FSM works in different clock domain than the system clock, where the busy flag is outputted, there is a synchronizer - The Heisenbug appeared in designs where TX clock is phase locked to the system clock (e.g. SPEC/SVEC). It was caused by a cross-clock domain setup time violation between the output of the LUT generating the tx_busy signal and the first flip flop of the synchronizer, which under certain conditions could permanently sample incorrect output of the LUT, resulting with the pcs_busy_o signal being stuck at 1 forever. - registering the TX clock domain busy signal removes glitches and fixes the problem.
01b463bf · Tomasz Wlostowski · Grzegorz Daniluk · 0f84242f · 01b463bf
Commit 01b463bf authored Dec 01, 2014 by Tomasz Wlostowski Committed by Grzegorz Daniluk Dec 09, 2014
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ep_tx_pcs_8bit.vhd modules/wr_endpoint/ep_tx_pcs_8bit.vhd +11 -3

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--- a/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT section
 -- Created    : 2009-06-16
-- Last update: 2012-03-21
+-- Last update: 2014-11-28
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -490,11 +490,19 @@ begin
    end if;
  end process;

-  tx_busy <= '1' when (fifo_empty = '0') or (tx_state /= TX_IDLE and tx_state /= TX_COMMA) else '0';
+  process(phy_tx_clk_i)
+  begin
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_IDLE and tx_state /= TX_COMMA) then
+        tx_busy <= '1';
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
+  end process;

  pcs_dreq_o <= not fifo_almost_full;

-
 end behavioral;