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White Rabbit core collection
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04583a97
Commit
04583a97
authored
Jul 14, 2015
by
Grzegorz Daniluk
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modules/wr_softpll_ng: for ext channel, use locked signal to notify lm32 if 10mhz in is there
parent
477ea639
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7 changed files
with
27 additions
and
7 deletions
+27
-7
wr_softpll_ng.vhd
modules/wr_softpll_ng/wr_softpll_ng.vhd
+2
-1
xwr_softpll_ng.vhd
modules/wr_softpll_ng/xwr_softpll_ng.vhd
+3
-0
wr_core.vhd
modules/wrc_core/wr_core.vhd
+2
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+4
-1
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+2
-0
ext_pll_10_to_125m.vhd
platform/xilinx/ext_pll_10_to_125m.vhd
+8
-3
spec_top.vhd
top/spec_1_1/wr_core_demo/spec_top.vhd
+6
-2
No files found.
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @
04583a97
...
...
@@ -111,6 +111,7 @@ entity wr_softpll_ng is
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
...
...
@@ -524,7 +525,7 @@ begin -- rtl
);
regs_out
.
eccr_ext_supported_i
<=
'1'
;
regs_out
.
eccr_ext_ref_present_i
<=
'1'
;
regs_out
.
eccr_ext_ref_present_i
<=
clk_ext_mul_locked_i
;
end
generate
gen_with_ext_clock_input
;
aligner_sample_valid
(
g_num_outputs
-1
downto
0
)
<=
(
others
=>
'0'
);
...
...
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @
04583a97
...
...
@@ -100,6 +100,7 @@ entity xwr_softpll_ng is
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
...
...
@@ -152,6 +153,7 @@ architecture wrapper of xwr_softpll_ng is
clk_dmtd_i
:
in
std_logic
;
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
;
pps_ext_a_i
:
in
std_logic
;
dac_dmtd_data_o
:
out
std_logic_vector
(
15
downto
0
);
...
...
@@ -201,6 +203,7 @@ begin -- behavioral
clk_dmtd_i
=>
clk_dmtd_i
,
clk_ext_i
=>
clk_ext_i
,
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
pps_csync_p1_i
=>
pps_csync_p1_i
,
pps_ext_a_i
=>
pps_ext_a_i
,
dac_dmtd_data_o
=>
dac_dmtd_data_o
,
...
...
modules/wrc_core/wr_core.vhd
View file @
04583a97
...
...
@@ -116,6 +116,7 @@ entity wr_core is
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -549,6 +550,7 @@ begin
clk_ext_i
=>
clk_ext_i
,
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
pps_csync_p1_i
=>
s_pps_csync
,
pps_ext_a_i
=>
pps_ext_i
,
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
04583a97
...
...
@@ -271,6 +271,7 @@ package wrcore_pkg is
clk_dmtd_i
:
in
std_logic
;
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
;
pps_ext_a_i
:
in
std_logic
;
dac_dmtd_data_o
:
out
std_logic_vector
(
15
downto
0
);
...
...
@@ -317,6 +318,7 @@ package wrcore_pkg is
clk_ref_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
...
...
@@ -439,7 +441,8 @@ package wrcore_pkg is
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i
:
in
std_logic
:
=
'0'
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
04583a97
...
...
@@ -103,6 +103,7 @@ entity xwr_core is
clk_ext_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_i
:
in
std_logic
:
=
'0'
;
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -249,6 +250,7 @@ begin
clk_aux_i
=>
clk_aux_i
,
clk_ext_i
=>
clk_ext_i
,
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
pps_ext_i
=>
pps_ext_i
,
rst_n_i
=>
rst_n_i
,
...
...
platform/xilinx/ext_pll_10_to_125m.vhd
View file @
04583a97
...
...
@@ -78,13 +78,14 @@ port
-- Clock out ports
clk_ext_mul_o
:
out
std_logic
;
-- Status and control signals
rst_a_i
:
in
std_logic
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
ext_pll_10_to_125m
;
architecture
xilinx
of
ext_pll_10_to_125m
is
attribute
CORE_GENERATION_INFO
:
string
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=
fals
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"
;
attribute
CORE_GENERATION_INFO
of
xilinx
:
architecture
is
"ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=
tru
e,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"
;
-- Input clock buffering / unused connectors
signal
clkin1
:
std_logic
;
-- Output clock buffering
...
...
@@ -97,6 +98,9 @@ architecture xilinx of ext_pll_10_to_125m is
begin
-- Input buffering
--------------------------------------
clkin1
<=
clk_ext_i
;
-- Clocking primitive
...
...
@@ -119,7 +123,7 @@ begin
STARTUP_WAIT
=>
FALSE
)
port
map
-- Input clock
(
CLKIN
=>
clk
_ext_i
,
(
CLKIN
=>
clk
in1
,
CLKFB
=>
clkfb
,
-- Output clocks
CLK0
=>
clk0
,
...
...
@@ -143,6 +147,7 @@ begin
-- Unused pin, tie low
DSSEN
=>
'0'
);
locked_o
<=
locked_internal
;
...
...
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @
04583a97
...
...
@@ -249,7 +249,8 @@ architecture rtl of spec_top is
port
(
clk_ext_i
:
in
std_logic
;
clk_ext_mul_o
:
out
std_logic
;
rst_a_i
:
in
std_logic
);
rst_a_i
:
in
std_logic
;
locked_o
:
out
std_logic
);
end
component
;
--component chipscope_ila
...
...
@@ -392,6 +393,7 @@ architecture rtl of spec_top is
signal
local_reset
,
ext_pll_reset
:
std_logic
;
signal
clk_ext
,
clk_ext_mul
:
std_logic
;
signal
clk_ext_mul_locked
:
std_logic
;
signal
clk_ref_div2
:
std_logic
;
begin
...
...
@@ -402,7 +404,8 @@ begin
port
map
(
clk_ext_i
=>
clk_ext
,
clk_ext_mul_o
=>
clk_ext_mul
,
rst_a_i
=>
ext_pll_reset
);
rst_a_i
=>
ext_pll_reset
,
locked_o
=>
clk_ext_mul_locked
);
U_Extend_EXT_Reset
:
gc_extend_pulse
generic
map
(
...
...
@@ -673,6 +676,7 @@ begin
clk_aux_i
=>
(
others
=>
'0'
),
clk_ext_i
=>
clk_ext
,
clk_ext_mul_i
=>
clk_ext_mul
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked
,
pps_ext_i
=>
dio_in
(
3
),
rst_n_i
=>
local_reset_n
,
...
...
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