Skip to content

W
White Rabbit core collection
Commit 04fd6b13 authored by Peter Jansweijer's avatar Peter Jansweijer
Browse files
Options

Avoid naming AD9516 and moulded PLL interface such that it also suits an LTC6950 

Adding pll_wr_mode[1:0] for SPEC7 V2
parent f5f7f210
Hide whitespace changes
Inline Side-by-side
Showing with 190 additions and 47 deletions
board/common/wr_board_pkg.vhd
View file @ 04fd6b13
......@@ -149,8 +149,8 @@ package wr_board_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_wr_mode_o : out std_logic_vector(1 downto 0);
pll_clk_sel_o : out std_logic;
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
......
board/common/xwrc_board_common.vhd
View file @ 04fd6b13
......@@ -117,7 +117,7 @@ entity xwrc_board_common is
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-----------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
......@@ -126,10 +126,10 @@ entity xwrc_board_common is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
-- 125 MHz from PLL after PLL initialisation.)
pll_clk_sel_o : out std_logic;
---------------------------------------------------------------------------
......@@ -432,8 +432,8 @@ begin -- architecture struct
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
pll_clk_sel_o => pll_clk_sel_o,
phy_ref_clk_i => '0',
phy_tx_data_o => open,
......
board/spec7/wr_spec7_pkg.vhd
View file @ 04fd6b13
......@@ -87,8 +87,8 @@ package wr_spec7_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_wr_mode_o : out std_logic_vector(1 downto 0);
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
......
board/spec7/xwrc_board_spec7.vhd
View file @ 04fd6b13
......@@ -120,7 +120,7 @@ entity xwrc_board_spec7 is
dac_dmtd_din_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic := '0';
......@@ -130,8 +130,8 @@ entity xwrc_board_spec7 is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_wr_mode_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
......@@ -355,7 +355,7 @@ begin -- architecture struct
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
-- The AD9516 on the SPEC7 needs to be initialized before it outputs
-- The PLL on the SPEC7 needs to be initialized before it outputs
-- clk_125m_gtx_p/n_i (which is
cmp_bufgmux: BUFGMUX
......@@ -388,7 +388,7 @@ begin -- architecture struct
-- logic AND of all async reset sources (active low)
-- Note: pll_locked = pll_dmtd_locked and pll_sys_locked. SPEC7 uses
-- direct_dmtd thus pll_dmtd_locked is always '1'. SPEC7 initial clk_sys_62m5
-- is clk_dmtd (selected by BUFGMUX) and clk_pll_62m5 is not yet driven by AD9516
-- is clk_dmtd (selected by BUFGMUX) and clk_pll_62m5 is not yet driven by the PLL
-- so pll_sys_locked = '0' and can't be used for synchronous reset generation.
--rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
rstlogic_arst_n <= areset_n_i and (not areset_edge_ppulse);
......@@ -506,8 +506,8 @@ begin -- architecture struct
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
pll_clk_sel_o => pll_clk_sel,
phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc,
......
modules/wrc_core/wr_core.vhd
View file @ 04fd6b13
......@@ -139,7 +139,7 @@ entity wr_core is
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-- AD9516 signals
-- PLL signals
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -147,10 +147,10 @@ entity wr_core is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
-- 125 MHz from PLL after PLL initialisation.)
pll_clk_sel_o : out std_logic;
-- PHY I/f
......@@ -947,7 +947,7 @@ begin
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
-- AD9516 signals
-- PLL signals
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......@@ -955,8 +955,8 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
pll_clk_sel_o => pll_clk_sel_o,
slave_i => periph_slave_i,
......
modules/wrc_core/wrc_periph.vhd
View file @ 04fd6b13
......@@ -86,7 +86,7 @@ entity wrc_periph is
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- AD9516 signals
-- PLL signals
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -94,10 +94,10 @@ entity wrc_periph is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
-- 125 MHz from PLL after PLL initialisation.)
pll_clk_sel_o : out std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 4);
......@@ -531,7 +531,7 @@ begin
wrpc_diag_regs_in.wdiag_temp_i <= sysc_regs_o.wdiag_temp_o;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-------------------------------------------------------------------------------
U_SPI_Master : xwb_spi
......@@ -568,12 +568,22 @@ begin
pll_clk_sel_o <= '1';
end if;
if(sysc_regs_o.gpsr_pll_wr_mode0_o = '1') then
pll_wr_mode_o(0) <= '1';
elsif(sysc_regs_o.gpcr_pll_wr_mode0_o = '1') then
pll_wr_mode_o(0) <= '0';
end if;
if(sysc_regs_o.gpsr_pll_wr_mode1_o = '1') then
pll_wr_mode_o(1) <= '1';
elsif(sysc_regs_o.gpcr_pll_wr_mode1_o = '1') then
pll_wr_mode_o(1) <= '0';
end if;
sysc_regs_i.gpsr_pll_lock_i <= pll_lock_i;
sysc_regs_i.gpsr_pll_status_i <= pll_status_i;
end if;
end process;
pll_sync_n_o <= '1'; -- Not Used by AD9516, default drive '1'
pll_refsel_o <= '0'; -- Not Used by AD9516, default drive '0'
pll_sync_n_o <= '1'; -- Not Used by PLL, default drive '1'
end struct;
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 04fd6b13
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : 11/22/19 16:40:26
-- Created : 01/20/20 09:14:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -104,6 +104,8 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_load_o : std_logic;
gpsr_pll_reset_o : std_logic;
gpsr_pll_clk_sel_o : std_logic;
gpsr_pll_wr_mode0_o : std_logic;
gpsr_pll_wr_mode1_o : std_logic;
gpcr_led_stat_o : std_logic;
gpcr_led_link_o : std_logic;
gpcr_fmc_scl_o : std_logic;
......@@ -115,6 +117,8 @@ package sysc_wbgen2_pkg is
gpcr_spi_mosi_o : std_logic;
gpcr_pll_reset_o : std_logic;
gpcr_pll_clk_sel_o : std_logic;
gpcr_pll_wr_mode0_o : std_logic;
gpcr_pll_wr_mode1_o : std_logic;
tcr_enable_o : std_logic;
diag_cr_adr_o : std_logic_vector(15 downto 0);
diag_cr_adr_load_o : std_logic;
......@@ -167,6 +171,8 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_load_o => '0',
gpsr_pll_reset_o => '0',
gpsr_pll_clk_sel_o => '0',
gpsr_pll_wr_mode0_o => '0',
gpsr_pll_wr_mode1_o => '0',
gpcr_led_stat_o => '0',
gpcr_led_link_o => '0',
gpcr_fmc_scl_o => '0',
......@@ -178,6 +184,8 @@ package sysc_wbgen2_pkg is
gpcr_spi_mosi_o => '0',
gpcr_pll_reset_o => '0',
gpcr_pll_clk_sel_o => '0',
gpcr_pll_wr_mode0_o => '0',
gpcr_pll_wr_mode1_o => '0',
tcr_enable_o => '0',
diag_cr_adr_o => (others => '0'),
diag_cr_adr_load_o => '0',
......
modules/wrc_core/wrc_syscon_regs.h
View file @ 04fd6b13
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : 11/22/19 16:40:26
* Created : 01/20/20 09:14:48
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -98,6 +98,12 @@
/* definitions for field: PLL_CLK_SEL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_PLL_CLK_SEL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: PLL_WR_MODE0 in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_PLL_WR_MODE0 WBGEN2_GEN_MASK(18, 1)
/* definitions for field: PLL_WR_MODE1 in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_PLL_WR_MODE1 WBGEN2_GEN_MASK(19, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -133,6 +139,12 @@
/* definitions for field: PLL_CLK_SEL in reg: GPIO Clear Register */
#define SYSC_GPCR_PLL_CLK_SEL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: PLL_WR_MODE0 in reg: GPIO Clear Register */
#define SYSC_GPCR_PLL_WR_MODE0 WBGEN2_GEN_MASK(18, 1)
/* definitions for field: PLL_WR_MODE1 in reg: GPIO Clear Register */
#define SYSC_GPCR_PLL_WR_MODE1 WBGEN2_GEN_MASK(19, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 04fd6b13
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : 11/22/19 16:40:26
-- Created : 01/20/20 09:14:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -48,6 +48,10 @@ signal sysc_gpsr_pll_reset_dly0 : std_logic ;
signal sysc_gpsr_pll_reset_int : std_logic ;
signal sysc_gpsr_pll_clk_sel_dly0 : std_logic ;
signal sysc_gpsr_pll_clk_sel_int : std_logic ;
signal sysc_gpsr_pll_wr_mode0_dly0 : std_logic ;
signal sysc_gpsr_pll_wr_mode0_int : std_logic ;
signal sysc_gpsr_pll_wr_mode1_dly0 : std_logic ;
signal sysc_gpsr_pll_wr_mode1_int : std_logic ;
signal sysc_gpcr_led_stat_dly0 : std_logic ;
signal sysc_gpcr_led_stat_int : std_logic ;
signal sysc_gpcr_led_link_dly0 : std_logic ;
......@@ -70,6 +74,10 @@ signal sysc_gpcr_pll_reset_dly0 : std_logic ;
signal sysc_gpcr_pll_reset_int : std_logic ;
signal sysc_gpcr_pll_clk_sel_dly0 : std_logic ;
signal sysc_gpcr_pll_clk_sel_int : std_logic ;
signal sysc_gpcr_pll_wr_mode0_dly0 : std_logic ;
signal sysc_gpcr_pll_wr_mode0_int : std_logic ;
signal sysc_gpcr_pll_wr_mode1_dly0 : std_logic ;
signal sysc_gpcr_pll_wr_mode1_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
signal sysc_diag_cr_rw_int : std_logic ;
signal sysc_wdiag_ctrl_data_valid_int : std_logic ;
......@@ -134,6 +142,8 @@ begin
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpsr_pll_reset_int <= '0';
sysc_gpsr_pll_clk_sel_int <= '0';
sysc_gpsr_pll_wr_mode0_int <= '0';
sysc_gpsr_pll_wr_mode1_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
......@@ -145,6 +155,8 @@ begin
sysc_gpcr_spi_mosi_int <= '0';
sysc_gpcr_pll_reset_int <= '0';
sysc_gpcr_pll_clk_sel_int <= '0';
sysc_gpcr_pll_wr_mode0_int <= '0';
sysc_gpcr_pll_wr_mode1_int <= '0';
sysc_tcr_enable_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
sysc_diag_cr_rw_int <= '0';
......@@ -189,6 +201,8 @@ begin
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpsr_pll_reset_int <= '0';
sysc_gpsr_pll_clk_sel_int <= '0';
sysc_gpsr_pll_wr_mode0_int <= '0';
sysc_gpsr_pll_wr_mode1_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
......@@ -200,6 +214,8 @@ begin
sysc_gpcr_spi_mosi_int <= '0';
sysc_gpcr_pll_reset_int <= '0';
sysc_gpcr_pll_clk_sel_int <= '0';
sysc_gpcr_pll_wr_mode0_int <= '0';
sysc_gpcr_pll_wr_mode1_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
regs_o.diag_dat_load_o <= '0';
ack_in_progress <= '0';
......@@ -271,6 +287,8 @@ begin
regs_o.gpsr_spi_mosi_load_o <= '1';
sysc_gpsr_pll_reset_int <= wrdata_reg(14);
sysc_gpsr_pll_clk_sel_int <= wrdata_reg(17);
sysc_gpsr_pll_wr_mode0_int <= wrdata_reg(18);
sysc_gpsr_pll_wr_mode1_int <= wrdata_reg(19);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -290,8 +308,8 @@ begin
rddata_reg(15) <= regs_i.gpsr_pll_lock_i;
rddata_reg(16) <= regs_i.gpsr_pll_status_i;
rddata_reg(17) <= '0';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(18) <= '0';
rddata_reg(19) <= '0';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
......@@ -319,6 +337,8 @@ begin
sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
sysc_gpcr_pll_reset_int <= wrdata_reg(14);
sysc_gpcr_pll_clk_sel_int <= wrdata_reg(17);
sysc_gpcr_pll_wr_mode0_int <= wrdata_reg(18);
sysc_gpcr_pll_wr_mode1_int <= wrdata_reg(19);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -331,6 +351,8 @@ begin
rddata_reg(12) <= '0';
rddata_reg(14) <= '0';
rddata_reg(17) <= '0';
rddata_reg(18) <= '0';
rddata_reg(19) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -849,6 +871,32 @@ begin
end process;
-- PLL_WR_MODE0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_pll_wr_mode0_dly0 <= '0';
regs_o.gpsr_pll_wr_mode0_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_pll_wr_mode0_dly0 <= sysc_gpsr_pll_wr_mode0_int;
regs_o.gpsr_pll_wr_mode0_o <= sysc_gpsr_pll_wr_mode0_int and (not sysc_gpsr_pll_wr_mode0_dly0);
end if;
end process;
-- PLL_WR_MODE1
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_pll_wr_mode1_dly0 <= '0';
regs_o.gpsr_pll_wr_mode1_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_pll_wr_mode1_dly0 <= sysc_gpsr_pll_wr_mode1_int;
regs_o.gpsr_pll_wr_mode1_o <= sysc_gpsr_pll_wr_mode1_int and (not sysc_gpsr_pll_wr_mode1_dly0);
end if;
end process;
-- Status LED
process (clk_sys_i, rst_n_i)
begin
......@@ -992,6 +1040,32 @@ begin
end process;
-- PLL_WR_MODE0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_pll_wr_mode0_dly0 <= '0';
regs_o.gpcr_pll_wr_mode0_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_pll_wr_mode0_dly0 <= sysc_gpcr_pll_wr_mode0_int;
regs_o.gpcr_pll_wr_mode0_o <= sysc_gpcr_pll_wr_mode0_int and (not sysc_gpcr_pll_wr_mode0_dly0);
end if;
end process;
-- PLL_WR_MODE1
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_pll_wr_mode1_dly0 <= '0';
regs_o.gpcr_pll_wr_mode1_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_pll_wr_mode1_dly0 <= sysc_gpcr_pll_wr_mode1_int;
regs_o.gpcr_pll_wr_mode1_o <= sysc_gpcr_pll_wr_mode1_int and (not sysc_gpcr_pll_wr_mode1_dly0);
end if;
end process;
-- Memory size
-- Storage type
-- Storage sector size
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 04fd6b13
......@@ -208,10 +208,26 @@ peripheral {
field {
name = "PLL_CLK_SEL";
prefix = "pll_clk_sel";
description = "write 1: SPEC7, Select clk_sys source from AD9516";
description = "write 1: Select clk_sys source from external PLL";
type = MONOSTABLE;
align = 17;
};
field {
name = "PLL_WR_MODE0";
prefix = "pll_wr_mode0";
description = "write 1: Set WR_Mode bit 0";
type = MONOSTABLE;
align = 18;
};
field {
name = "PLL_WR_MODE1";
prefix = "pll_wr_mode1";
description = "write 1: Set WR_Mode bit 1";
type = MONOSTABLE;
align = 19;
};
};
reg {
......@@ -299,10 +315,26 @@ peripheral {
field {
name = "PLL_CLK_SEL";
prefix = "pll_clk_sel";
description = "write 1: SPEC7, Select clk_sys source from free running clk_dmtd";
description = "write 1: Select clk_sys source from free running clk_dmtd";
type = MONOSTABLE;
align = 17;
};
field {
name = "PLL_WR_MODE0";
prefix = "pll_wr_mode0";
description = "write 1: Clear WR_Mode bit 0";
type = MONOSTABLE;
align = 18;
};
field {
name = "PLL_WR_MODE1";
prefix = "pll_wr_mode1";
description = "write 1: Clear WR_Mode bit 1";
type = MONOSTABLE;
align = 19;
};
};
reg {
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 04fd6b13
......@@ -285,8 +285,8 @@ package wrcore_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
pll_clk_sel_o : out std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 4);
slave_o : out t_wishbone_slave_out_array(0 to 4);
......@@ -419,8 +419,8 @@ package wrcore_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_wr_mode_o : out std_logic_vector(1 downto 0);
pll_clk_sel_o : out std_logic;
-----------------------------------------
......@@ -649,9 +649,9 @@ package wrcore_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic := '0';
pll_clk_sel_o : out std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
pll_clk_sel_o : out std_logic;
-----------------------------------------
--UART
......
modules/wrc_core/xwr_core.vhd
View file @ 04fd6b13
......@@ -138,7 +138,7 @@ entity xwr_core is
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-----------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
......@@ -147,10 +147,10 @@ entity xwr_core is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
-- SPEC7 Select clk_sys source (either always running clk_dmtd or
-- 125 MHz from AD9516 after PLL initialisation.)
-- 125 MHz from PLL after PLL initialisation.)
pll_clk_sel_o : out std_logic;
-----------------------------------------
......@@ -342,8 +342,8 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
pll_clk_sel_o => pll_clk_sel_o,
phy_ref_clk_i => phy_ref_clk_i,
......
sim/wrc_syscon_regs.vh
View file @ 04fd6b13
......@@ -40,6 +40,10 @@
`define SYSC_GPSR_PLL_STATUS 32'h00010000
`define SYSC_GPSR_PLL_CLK_SEL_OFFSET 17
`define SYSC_GPSR_PLL_CLK_SEL 32'h00020000
`define SYSC_GPSR_PLL_WR_MODE0_OFFSET 18
`define SYSC_GPSR_PLL_WR_MODE0 32'h00040000
`define SYSC_GPSR_PLL_WR_MODE1_OFFSET 19
`define SYSC_GPSR_PLL_WR_MODE1 32'h00080000
`define ADDR_SYSC_GPCR 7'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
......@@ -63,6 +67,10 @@
`define SYSC_GPCR_PLL_RESET 32'h00004000
`define SYSC_GPCR_PLL_CLK_SEL_OFFSET 17
`define SYSC_GPCR_PLL_CLK_SEL 32'h00020000
`define SYSC_GPCR_PLL_WR_MODE0_OFFSET 18
`define SYSC_GPCR_PLL_WR_MODE0 32'h00040000
`define SYSC_GPCR_PLL_WR_MODE1_OFFSET 19
`define SYSC_GPCR_PLL_WR_MODE1 32'h00080000
`define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
......
top/spec7_write_design/spec7_write_top.vhd
View file @ 04fd6b13
......@@ -97,7 +97,7 @@ entity spec7_write_top is
dac_dmtd_din_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
......@@ -106,9 +106,8 @@ entity spec7_write_top is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- SFP I/O for transceiver
......@@ -317,9 +316,9 @@ begin -- architecture top
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_reset_n_o => open,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
......
top/spec7_write_design/spec7_write_top.xdc
View file @ 04fd6b13
......@@ -77,7 +77,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B11 [get_ports pll_status_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_status_i]
set_property PACKAGE_PIN B12 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C14 [get_ports pll_mosi_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C11 [get_ports pll_miso_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_miso_i]
......@@ -87,12 +87,12 @@ set_property PACKAGE_PIN A14 [get_ports pll_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_cs_n_o]
set_property PACKAGE_PIN B14 [get_ports pll_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sync_n_o]
set_property PACKAGE_PIN C12 [get_ports pll_reset_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_reset_n_o]
set_property PACKAGE_PIN C14 [get_ports pll_refsel_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_refsel_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
set_property PACKAGE_PIN B12 [get_ports pll_wr_mode_o_0]]
set_property IOSTANDARD LVCMOS18 [get_ports pll_wr_mode_o_0]
set_property PACKAGE_PIN C12 [get_ports pll_wr_mode_o_1]
set_property IOSTANDARD LVCMOS18 [get_ports pll_wr_mode_o_1]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment