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White Rabbit core collection
Commit 05fc2bee authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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minic: updating simulation and testbench for fifos

parent b670fedb
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Showing with 148 additions and 170 deletions
sim/drivers/simdrv_minic.svh
View file @ 05fc2bee
......@@ -14,14 +14,19 @@ class CSimDrv_Minic;
`define RX_DESC_ERROR(d) ((d) & (1<<30) ? 1 : 0)
`define RX_DESC_HAS_OOB(d) ((d) & (1<<29) ? 1 : 0)
`define RX_DESC_SIZE(d) (((d) & (1<<0) ? -1 : 0) + (d & 'hffe))
`define c_WRF_DATA 0
`define c_WRF_OOB 1
`define c_WRF_STATUS 2
`define c_WRF_BYTESEL 3
protected CBusAccessor acc_regs, acc_pmem;
protected uint32_t base_regs, base_pmem;
protected int pmem_size;
protected bit little_endian;
protected uint32_t tx_head, tx_base, tx_avail, tx_size, tx_count, tx_oob_val;
protected uint32_t rx_head, rx_base, rx_avail, rx_size, rx_count;
protected uint32_t tx_head, tx_base, tx_avail, tx_size, tx_oob_val;
protected uint32_t rx_head, rx_base, rx_avail, rx_size;
protected EthPacket rx_queue[$];
......@@ -29,44 +34,44 @@ class CSimDrv_Minic;
const int MINIC_MTU = 1536;
function new(int pmem_size_, CBusAccessor regs_, uint32_t base_regs_, CBusAccessor pmem_, uint32_t base_pmem_);
base_pmem = base_pmem_;
function new(CBusAccessor regs_, uint32_t base_regs_);
base_regs = base_regs_;
acc_regs = regs_;
acc_pmem = pmem_;
pmem_size = pmem_size_;
little_endian = 1;
endfunction // new
endfunction
task minic_writel(uint32_t addr, uint32_t val);
acc_regs.write(base_regs + addr, val, 4);
endtask // minic_writel
endtask
task minic_readl(uint32_t addr, output uint32_t val);
uint64_t tmp;
acc_regs.read(base_regs + addr, tmp, 4);
val = tmp;
endtask // minic_writel
endtask
task minic_write_txword(uint32_t word_type, uint32_t word);
uint32_t val;
val = word_type << `MINIC_TX_FIFO_TYPE_OFFSET;
val = val | (word & `MINIC_TX_FIFO_DAT);
minic_writel(`ADDR_MINIC_TX_FIFO, val);
endtask
task new_tx_buffer();
tx_head = tx_base;
tx_avail = (tx_size - MINIC_MTU) >> 2;
minic_writel(`ADDR_MINIC_TX_ADDR, tx_base);
endtask // new_tx_buffers
task new_rx_buffer();
rx_head = rx_base;
minic_writel(`ADDR_MINIC_MCR, 0);
minic_writel(`ADDR_MINIC_RX_ADDR, rx_base);
minic_writel(`ADDR_MINIC_RX_SIZE, rx_size >> 2);
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
minic_writel(`ADDR_MINIC_MCR, `MINIC_MCR_RX_EN);
endtask // new_rx_buffer
//task new_tx_buffer();
// tx_head = tx_base;
// tx_avail = (tx_size - MINIC_MTU) >> 2;
// minic_writel(`ADDR_MINIC_TX_ADDR, tx_base);
//endtask // new_tx_buffers
//task new_rx_buffer();
// rx_head = rx_base;
// minic_writel(`ADDR_MINIC_MCR, 0);
// minic_writel(`ADDR_MINIC_RX_ADDR, rx_base);
// minic_writel(`ADDR_MINIC_RX_SIZE, rx_size >> 2);
// minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
// minic_writel(`ADDR_MINIC_MCR, `MINIC_MCR_RX_EN);
//endtask // new_rx_buffer
task init();
......@@ -75,47 +80,65 @@ class CSimDrv_Minic;
minic_writel(`ADDR_MINIC_EIC_IDR, `MINIC_EIC_IDR_RX);
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
tx_base = base_pmem;
tx_size = pmem_size / 2;
rx_base = base_pmem + pmem_size / 2;
rx_size = pmem_size / 2;
//tx_base = base_pmem;
//tx_size = pmem_size / 2;
//rx_base = base_pmem + pmem_size / 2;
//rx_size = pmem_size / 2;
tx_oob_val = 12345;
lo = rx_base >> 2;
hi = (rx_base >> 2) + (rx_size >> 2) - 1;
//lo = rx_base >> 2;
//hi = (rx_base >> 2) + (rx_size >> 2) - 1;
minic_writel(`ADDR_MINIC_MPROT, (lo << `MINIC_MPROT_LO_OFFSET) | (hi << `MINIC_MPROT_HI_OFFSET));
tx_count = 0;
rx_count = 0;
//minic_writel(`ADDR_MINIC_MPROT, (lo << `MINIC_MPROT_LO_OFFSET) | (hi << `MINIC_MPROT_HI_OFFSET));
new_rx_buffer();
//new_rx_buffer();
minic_writel(`ADDR_MINIC_EIC_IER, `MINIC_EIC_IER_RX);
endtask // init
task tx_frame(byte payload[], uint32_t size, bit with_oob, int ts_id, output uint32_t ts, output int port_id);
task tx_frame(byte frame[], uint32_t size, bit with_oob, int frame_id, output uint32_t ts, output int port_id);
int i;
uint32_t d_hdr, mcr, nwords;
uint32_t size_words;
uint16_t word;
u64_array_t buff;
int bytesel = 0;
byte tmp[];
byte oob[2];
new_tx_buffer();
//new_tx_buffer();
if(size < 60) size = 60;
if(size & 1) size = size + 1;
if(size & 1) begin
size = size + 1;
bytesel = 1;
end
tmp = new[size](payload);
//tmp = new[size](payload);
buff = SimUtils.pack({0,0,0,0, tmp, 0,0,0,0}, 4, 1);
size = size / 2;
for(i=0;i<buff.size(); i++)
acc_pmem.write(tx_head + i*4, buff[i], 4);
//buff = SimUtils.pack({0,0,0,0, tmp, 0,0,0,0}, 4, 1);
size_words = size / 2;
//first we write status word (empty status)
minic_write_txword(`c_WRF_STATUS, 0);
acc_pmem.write(tx_head, TX_DESC_HAS_OWN_MAC | TX_DESC_VALID | (with_oob ? TX_DESC_WITH_OOB :0 )| size | (ts_id << 12), 4);
//then we write the actual frame
for(i=0;i<size_words-1; i++) begin
word = (frame[2*i+1] << 8) | frame[2*i];
minic_write_txword(`c_WRF_DATA, word);
end
//write the last word with bytesel or normal
if(bytesel == 1)
minic_write_txword(`c_WRF_BYTESEL, frame[2*size_words]);
else begin
word = (frame[2*size_words+1] << 8) | frame[2*size_words];
minic_write_txword(`c_WRF_DATA, word);
end
if (with_oob) begin
minic_write_txword(`c_WRF_OOB, frame_id);
end
minic_readl(`ADDR_MINIC_MCR, mcr);
minic_writel(`ADDR_MINIC_MCR, mcr | `MINIC_MCR_TX_START);
......@@ -133,59 +156,59 @@ class CSimDrv_Minic;
int n_recvd;
uint32_t isr;
minic_readl(`ADDR_MINIC_EIC_ISR, isr);
if(! (isr & `MINIC_EIC_ISR_RX))
return;
acc_pmem.read(rx_head, desc_hdr);
if(!`RX_DESC_VALID(desc_hdr))
begin
$error("SimDRV_Minic::rx_frame: weird, invalid RX desc header");
$stop;
end
payload_size = `RX_DESC_SIZE(desc_hdr);
num_words = (payload_size + 3) >> 2;
pbuff = new [num_words];
// $display("NWords %d hdr %x", num_words, desc_hdr);
if(`RX_DESC_HAS_OOB(desc_hdr))
payload_size = payload_size - 6;
if(!`RX_DESC_ERROR(desc_hdr))
begin
for(i=0; i<num_words;i++)
acc_pmem.read((rx_head + 4 + i * 4) % rx_size, pbuff[i]);
payload = SimUtils.unpack(pbuff, 4, payload_size);
end
size = payload_size;
rx_head = (rx_head + 4 + num_words * 4 - rx_base) % rx_size + rx_base;
minic_writel(`ADDR_MINIC_RX_AVAIL, (num_words + 1));
minic_readl(`ADDR_MINIC_RX_AVAIL, cur_avail);
acc_pmem.read(rx_head, desc_hdr);
if( cur_avail == (rx_size>>2) || !(`RX_DESC_VALID(desc_hdr)))
begin
minic_readl(`ADDR_MINIC_MCR, mcr);
if(mcr & `MINIC_MCR_RX_FULL)
new_rx_buffer();
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
end
//minic_readl(`ADDR_MINIC_EIC_ISR, isr);
//
//if(! (isr & `MINIC_EIC_ISR_RX))
// return;
//acc_pmem.read(rx_head, desc_hdr);
//
//if(!`RX_DESC_VALID(desc_hdr))
// begin
// $error("SimDRV_Minic::rx_frame: weird, invalid RX desc header");
// $stop;
// end
//payload_size = `RX_DESC_SIZE(desc_hdr);
//num_words = (payload_size + 3) >> 2;
//pbuff = new [num_words];
//// $display("NWords %d hdr %x", num_words, desc_hdr);
//
//
//if(`RX_DESC_HAS_OOB(desc_hdr))
// payload_size = payload_size - 6;
//
//
//if(!`RX_DESC_ERROR(desc_hdr))
// begin
// for(i=0; i<num_words;i++)
// acc_pmem.read((rx_head + 4 + i * 4) % rx_size, pbuff[i]);
// payload = SimUtils.unpack(pbuff, 4, payload_size);
// end
//size = payload_size;
//
//rx_head = (rx_head + 4 + num_words * 4 - rx_base) % rx_size + rx_base;
//minic_writel(`ADDR_MINIC_RX_AVAIL, (num_words + 1));
//minic_readl(`ADDR_MINIC_RX_AVAIL, cur_avail);
//acc_pmem.read(rx_head, desc_hdr);
//if( cur_avail == (rx_size>>2) || !(`RX_DESC_VALID(desc_hdr)))
// begin
// minic_readl(`ADDR_MINIC_MCR, mcr);
//
// if(mcr & `MINIC_MCR_RX_FULL)
// new_rx_buffer();
// minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
// end
//
endtask // rx_frame
task do_rx();
......
testbench/wr_minic/Manifest.py
View file @ 05fc2bee
action = "simulation"
files = "main.sv"
#fetchto = "../../ip_cores"
target = "xilinx"
#syn_device = "xc6slx45t"
#syn_grade = "-3"
#syn_package = "fgg484"
#sim_tool = "modelsim"
#top_module = "main"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim"
vlog_opt="+incdir+../../sim"
files = [ "main.sv" ]
modules ={"local" : ["../../ip_cores/general-cores",
"../../modules/wr_endpoint",
"../../modules/wr_mini_nic" ] };
modules = { "local" : [ "../../",
"../../ip_cores/general-cores"
]};
testbench/wr_minic/main.sv
View file @ 05fc2bee
......@@ -3,8 +3,8 @@
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "simdrv_minic.svh"
`include "ep2ep_wrapper.svh"
`include "drivers/simdrv_minic.svh"
//`include "ep2ep_wrapper.svh"
module main;
......@@ -49,18 +49,6 @@ module main;
);
IWishboneMaster
#(
.g_data_width(32),
.g_addr_width(16))
U_pmem_bus_master
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
wire minic_irq;
wire [31:0] pmem_wr_data, pmem_rd_data;
wire [13:0] pmem_addr;
......@@ -71,10 +59,10 @@ module main;
.clk_sys_i (clk_sys),
.rst_n_i (rst_n),
.mem_data_o (pmem_wr_data),
.mem_addr_o (pmem_addr),
.mem_data_i (pmem_rd_data),
.mem_wr_o (pmem_wr),
.mem_data_o (),
.mem_addr_o (),
.mem_data_i (32'h0),
.mem_wr_o (p),
.src_dat_o (U_wrf_sink.dat_i),
.src_adr_o (U_wrf_sink.adr),
......@@ -115,30 +103,9 @@ module main;
.wb_irq_o (minic_irq)
);
minic_packet_buffer PBUF
(
.clk_sys_i (clk_sys),
.rst_n_i (rst_n),
.minic_addr_i (pmem_addr),
.minic_data_i (pmem_wr_data),
.minic_wr_i (pmem_wr),
.minic_data_o (pmem_rd_data),
.wb_cyc_i (U_pmem_bus_master.cyc),
.wb_stb_i (U_pmem_bus_master.stb),
.wb_we_i (U_pmem_bus_master.we),
.wb_addr_i (U_pmem_bus_master.adr[13:0]),
.wb_data_i (U_pmem_bus_master.dat_o),
.wb_data_o (U_pmem_bus_master.dat_i),
.wb_ack_o (U_pmem_bus_master.ack)
);
CSimDrv_Minic minic;
task test_tx_path(int n_packets, CSimDrv_Minic minic, WBPacketSink sink);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl;
......@@ -192,7 +159,7 @@ module main;
initial begin
CWishboneAccessor sys_bus, pmem_bus;
CWishboneAccessor sys_bus;
WBPacketSource src = new(U_wrf_source.get_accessor());
WBPacketSink sink = new(U_wrf_sink.get_accessor());
EthPacketGenerator gen = new;
......@@ -200,26 +167,17 @@ module main;
EthPacket txed[$];
int i;
@(posedge rst_n);
@(posedge clk_sys);
sys_bus = U_sys_bus_master.get_accessor();
sys_bus = U_sys_bus_master.get_accessor();
sys_bus.set_mode(CLASSIC);
pmem_bus = U_pmem_bus_master.get_accessor();
pmem_bus.set_mode(CLASSIC);
minic = new('h10000, sys_bus, 0, pmem_bus, 0);
minic = new(sys_bus, 0);
minic.init();
tmpl = new;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{10,11,12,13,14,15};
tmpl.has_smac = 1;
......@@ -270,15 +228,6 @@ module main;
end
// #1;
// end // forever begin
join
......
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