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White Rabbit core collection
Commit 0f54b1da authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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greg-testing: minic rx circular buffer

parent 00675d68
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Showing with 144 additions and 48 deletions
modules/wr_mini_nic/mini_nic.wb
View file @ 0f54b1da
......@@ -113,7 +113,25 @@ peripheral {
reg {
name = "RX buffer size register";
description = "Number of available 32-bit words in the RX buffer";
description = "Size of RX buffer in 32-bit words";
prefix = "RX_SIZE";
field {
name = "RX available words";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "RX buffer available words register";
description = "Number of available 32-bit words in the RX buffer\
read: available words in RX buffer\
write: increment available words in RX buffer";
prefix = "RX_AVAIL";
field {
......@@ -244,4 +262,4 @@ peripheral {
trigger = LEVEL_1;
prefix = "TXTS";
};
};
\ No newline at end of file
};
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 0f54b1da
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Sun Nov 6 00:30:17 2011
-- Created : Tue May 29 15:57:15 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -22,7 +22,7 @@ entity minic_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -65,7 +65,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -95,6 +95,7 @@ begin
minic_mcr_rx_class_int <= "00000000";
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
tx_ts_read_ack_o <= '0';
minic_mprot_lo_int <= "0000000000000000";
......@@ -111,6 +112,7 @@ begin
minic_mcr_tx_start_int <= '0';
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
tx_ts_read_ack_o <= '0';
eic_idr_write_int <= '0';
......@@ -120,12 +122,13 @@ begin
else
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
minic_mcr_tx_start_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
......@@ -165,7 +168,7 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00001" =>
if (wb_we_i = '1') then
regs_o.tx_addr_load_o <= '1';
else
......@@ -181,7 +184,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00010" =>
if (wb_we_i = '1') then
regs_o.rx_addr_load_o <= '1';
else
......@@ -197,7 +200,23 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00011" =>
if (wb_we_i = '1') then
regs_o.rx_size_load_o <= '1';
else
rddata_reg(23 downto 0) <= regs_i.rx_size_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
regs_o.rx_avail_load_o <= '1';
else
......@@ -213,7 +232,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00101" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
else
......@@ -233,7 +252,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= regs_i.tsr1_tsval_i;
......@@ -241,7 +260,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "00111" =>
if (wb_we_i = '1') then
rddata_reg(24) <= 'X';
else
......@@ -257,7 +276,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "01000" =>
if (wb_we_i = '1') then
minic_mprot_lo_int <= wrdata_reg(15 downto 0);
minic_mprot_hi_int <= wrdata_reg(31 downto 16);
......@@ -267,7 +286,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "10000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
......@@ -306,7 +325,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "10001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
......@@ -345,7 +364,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "10010" =>
if (wb_we_i = '1') then
else
rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
......@@ -381,7 +400,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "10011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
......@@ -456,6 +475,8 @@ begin
regs_o.tx_addr_o <= wrdata_reg(23 downto 0);
-- RX DMA buffer address
regs_o.rx_addr_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_size_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_avail_o <= wrdata_reg(23 downto 0);
-- Timestamp valid
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 0f54b1da
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Sun Nov 6 00:30:17 2011
-- Created : Tue May 29 15:57:15 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -27,6 +27,7 @@ package minic_wbgen2_pkg is
mcr_rx_full_i : std_logic;
tx_addr_i : std_logic_vector(23 downto 0);
rx_addr_i : std_logic_vector(23 downto 0);
rx_size_i : std_logic_vector(23 downto 0);
rx_avail_i : std_logic_vector(23 downto 0);
tsr0_valid_i : std_logic;
tsr0_pid_i : std_logic_vector(4 downto 0);
......@@ -43,6 +44,7 @@ package minic_wbgen2_pkg is
mcr_rx_full_i => '0',
tx_addr_i => (others => '0'),
rx_addr_i => (others => '0'),
rx_size_i => (others => '0'),
rx_avail_i => (others => '0'),
tsr0_valid_i => '0',
tsr0_pid_i => (others => '0'),
......@@ -62,6 +64,8 @@ package minic_wbgen2_pkg is
tx_addr_load_o : std_logic;
rx_addr_o : std_logic_vector(23 downto 0);
rx_addr_load_o : std_logic;
rx_size_o : std_logic_vector(23 downto 0);
rx_size_load_o : std_logic;
rx_avail_o : std_logic_vector(23 downto 0);
rx_avail_load_o : std_logic;
mprot_lo_o : std_logic_vector(15 downto 0);
......@@ -76,6 +80,8 @@ package minic_wbgen2_pkg is
tx_addr_load_o => '0',
rx_addr_o => (others => '0'),
rx_addr_load_o => '0',
rx_size_o => (others => '0'),
rx_size_load_o => '0',
rx_avail_o => (others => '0'),
rx_avail_load_o => '0',
mprot_lo_o => (others => '0'),
......@@ -103,6 +109,7 @@ tmp.mcr_rx_ready_i := left.mcr_rx_ready_i or right.mcr_rx_ready_i;
tmp.mcr_rx_full_i := left.mcr_rx_full_i or right.mcr_rx_full_i;
tmp.tx_addr_i := left.tx_addr_i or right.tx_addr_i;
tmp.rx_addr_i := left.rx_addr_i or right.rx_addr_i;
tmp.rx_size_i := left.rx_size_i or right.rx_size_i;
tmp.rx_avail_i := left.rx_avail_i or right.rx_avail_i;
tmp.tsr0_valid_i := left.tsr0_valid_i or right.tsr0_valid_i;
tmp.tsr0_pid_i := left.tsr0_pid_i or right.tsr0_pid_i;
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 0f54b1da
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2012-04-24
-- Last update: 2012-05-31
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -117,7 +117,7 @@ architecture behavioral of wr_mini_nic is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -224,10 +224,12 @@ architecture behavioral of wr_mini_nic is
type t_rx_fsm_state is (RX_WAIT_SOF, RX_MEM_RESYNC, RX_MEM_FLUSH, RX_ALLOCATE_DESCRIPTOR, RX_DATA, RX_UPDATE_DESC);
signal nrx_state : t_rx_fsm_state;
signal nrx_avail : unsigned(g_memsize_log2-1 downto 0);
signal nrx_toggle : std_logic;
signal nrx_oob_reg : std_logic_vector(15 downto 0);
signal nrx_state : t_rx_fsm_state;
signal nrx_avail : unsigned(g_memsize_log2-1 downto 0);
signal nrx_bufstart : unsigned(g_memsize_log2-1 downto 0);
signal nrx_bufsize : unsigned(g_memsize_log2-1 downto 0);
signal nrx_toggle : std_logic;
signal nrx_oob_reg : std_logic_vector(15 downto 0);
--STATUS Reg for RX path
signal nrx_status_reg : t_wrf_status_reg;
......@@ -297,6 +299,7 @@ architecture behavioral of wr_mini_nic is
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal s_nrx_state : std_logic_vector(2 downto 0);
begin -- behavioral
......@@ -312,6 +315,18 @@ begin -- behavioral
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--
-- TRIG0(0) <= snk_cyc_i;
-- TRIG0(1) <= snk_stb_i;
-- TRIG0(2) <= snk_stall_int;
-- TRIG0(4 downto 3) <= snk_adr_i;
-- TRIG0(7 downto 5) <= s_nrx_state;
-- TRIG0(8) <= nrx_error;
-- TRIG0(23 downto 9) <= std_logic_vector(nrx_avail);
-- TRIG1 <= nrx_mem_d;
-- TRIG2(14 downto 0) <= std_logic_vector(nrx_mem_a);
-- TRIG2(29 downto 15) <= std_logic_vector(nrx_bufstart);
-- TRIG3(14 downto 0) <= std_logic_vector(nrx_bufsize);
-------------------------------------------------------------------------------
......@@ -689,9 +704,12 @@ begin -- behavioral
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
nrx_state <= RX_WAIT_SOF;
s_nrx_state <= "000";
nrx_mem_a <= (others => '0');
nrx_mem_wr <= '0';
nrx_avail <= (others => '0');
nrx_bufstart <= (others => '0');
nrx_bufsize <= (others => '0');
nrx_rdreg <= (others => '0');
nrx_toggle <= '0';
nrx_stall_mask <= '0';
......@@ -729,16 +747,23 @@ begin -- behavioral
-- handle writes to RX_ADDR and RX_AVAIL
if(regs_out.rx_addr_load_o = '1') then
nrx_mem_a_saved <= unsigned(regs_out.rx_addr_o(g_memsize_log2+1 downto 2));
nrx_bufstart <= unsigned(regs_out.rx_addr_o(g_memsize_log2+1 downto 2));
regs_in.rx_addr_i <= (others => '0');
-- nrx_mem_a <= unsigned(minic_rx_addr_new(g_memsize_log2+1 downto 2));
end if;
if(regs_out.rx_avail_load_o = '1') then
if(regs_out.rx_size_load_o = '1') then
nrx_buf_full <= '0';
regs_in.mcr_rx_full_i <= '0';
nrx_avail <= unsigned(regs_out.rx_avail_o(nrx_avail'high downto 0));
nrx_avail <= unsigned(regs_out.rx_size_o(nrx_avail'high downto 0));
nrx_bufsize <= unsigned(regs_out.rx_size_o(nrx_bufsize'high downto 0));
end if;
else
if(regs_out.rx_avail_load_o = '1') then
nrx_buf_full <= '0';
regs_in.mcr_rx_full_i <= '0';
nrx_avail <= nrx_avail + unsigned(regs_out.rx_avail_o(nrx_avail'high downto 0));
end if;
-- main RX FSM
case nrx_state is
......@@ -749,6 +774,7 @@ begin -- behavioral
-------------------------------------------------------------------------------
when RX_WAIT_SOF =>
-- TRIG0(2 downto 0) <= "000";
s_nrx_state <= "000";
nrx_newpacket <= '0';
nrx_done <= '0';
......@@ -776,6 +802,7 @@ begin -- behavioral
when RX_ALLOCATE_DESCRIPTOR =>
-- TRIG0(2 downto 0) <= "001";
s_nrx_state <= "001";
-- wait until we have memory access
if(mem_arb_rx = '0') then
......@@ -801,6 +828,7 @@ begin -- behavioral
when RX_DATA =>
-- TRIG0(2 downto 0) <= "010";
s_nrx_state <= "010";
nrx_mem_wr <= '0';
......@@ -836,7 +864,11 @@ begin -- behavioral
nrx_state <= RX_MEM_FLUSH;
if(nrx_valid = '1' or nrx_toggle = '1') then
nrx_mem_a <= nrx_mem_a + 1;
if nrx_mem_a + 1 >= nrx_bufstart + nrx_bufsize then
nrx_mem_a <= nrx_bufstart;
else
nrx_mem_a <= nrx_mem_a + 1;
end if;
end if;
-- disable the RX fabric reception, so we won't get another
......@@ -882,7 +914,11 @@ begin -- behavioral
-- we've got the second valid word of the payload, write it to the
-- memory
if(nrx_toggle = '1' and nrx_valid = '1' and snk_cyc_i = '1' and nrx_stat_error = '0') then
nrx_mem_a <= nrx_mem_a + 1;
if nrx_mem_a + 1 >= nrx_bufstart + nrx_bufsize then
nrx_mem_a <= nrx_bufstart;
else
nrx_mem_a <= nrx_mem_a + 1;
end if;
nrx_mem_wr <= '1';
nrx_avail <= nrx_avail - 1;
......@@ -902,14 +938,19 @@ begin -- behavioral
when RX_MEM_RESYNC =>
-- TRIG0(2 downto 0) <= "011";
s_nrx_state <= "011";
-- check for error/abort conditions, they may appear even when
-- the fabric is not accepting the data (tx_dreq_o = 0)
if(nrx_stat_error = '1') then
nrx_error <= '1';
nrx_done <= '1';
nrx_state <= RX_MEM_FLUSH;
nrx_mem_a <= nrx_mem_a + 1;
nrx_error <= '1';
nrx_done <= '1';
nrx_state <= RX_MEM_FLUSH;
if nrx_mem_a + 1 >= nrx_bufstart + nrx_bufsize then
nrx_mem_a <= nrx_bufstart;
else
nrx_mem_a <= nrx_mem_a + 1;
end if;
nrx_stall_mask <= '1';
nrx_size <= nrx_size + 2;
else
......@@ -923,6 +964,7 @@ begin -- behavioral
when RX_MEM_FLUSH =>
-- TRIG0(2 downto 0) <= "100";
s_nrx_state <= "100";
nrx_stall_mask <= '1';
if(nrx_buf_full = '0') then
......@@ -946,6 +988,7 @@ begin -- behavioral
when RX_UPDATE_DESC =>
-- TRIG0(2 downto 0) <= "101";
s_nrx_state <= "101";
nrx_stall_mask <= '1';
if(mem_arb_rx = '0') then
......@@ -956,8 +999,12 @@ begin -- behavioral
regs_in.rx_addr_i(g_memsize_log2+1 downto 0) <= std_logic_vector(nrx_mem_a_saved) & "00";
regs_in.rx_addr_i(regs_in.rx_addr_i'high downto g_memsize_log2+2) <= (others => '0');
nrx_mem_a <= nrx_mem_a_saved;
nrx_mem_a_saved <= nrx_mem_a + 1;
nrx_mem_a <= nrx_mem_a_saved;
if nrx_mem_a + 1 >= nrx_bufstart + nrx_bufsize then
nrx_mem_a_saved <= nrx_bufstart;
else
nrx_mem_a_saved <= nrx_mem_a + 1;
end if;
-- compose the RX descriptor
nrx_mem_d(31) <= '1';
......@@ -1095,7 +1142,7 @@ begin -- behavioral
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_out.adr(3 downto 0),
wb_addr_i => wb_out.adr(4 downto 0),
wb_data_i => wb_out.dat,
wb_data_o => wb_in.dat,
wb_cyc_i => wb_out.cyc,
......@@ -1117,5 +1164,7 @@ begin -- behavioral
regs_in.rx_avail_i(nrx_avail'high downto 0) <= std_logic_vector(nrx_avail);
regs_in.rx_avail_i(regs_in.rx_avail_i'high downto nrx_avail'high+1) <= (others => '0');
regs_in.rx_size_i(nrx_size'high downto 0) <= std_logic_vector(nrx_bufsize);
regs_in.rx_size_i(regs_in.rx_size_i'high downto nrx_size'high+1) <= (others => '0');
end behavioral;
sim/minic_regs.vh
View file @ 0f54b1da
`define ADDR_MINIC_MCR 6'h0
`define ADDR_MINIC_MCR 7'h0
`define MINIC_MCR_TX_START_OFFSET 0
`define MINIC_MCR_TX_START 32'h00000001
`define MINIC_MCR_TX_IDLE_OFFSET 1
......@@ -13,51 +13,52 @@
`define MINIC_MCR_RX_EN 32'h00000400
`define MINIC_MCR_RX_CLASS_OFFSET 16
`define MINIC_MCR_RX_CLASS 32'h00ff0000
`define ADDR_MINIC_TX_ADDR 6'h4
`define ADDR_MINIC_RX_ADDR 6'h8
`define ADDR_MINIC_RX_AVAIL 6'hc
`define ADDR_MINIC_TSR0 6'h10
`define ADDR_MINIC_TX_ADDR 7'h4
`define ADDR_MINIC_RX_ADDR 7'h8
`define ADDR_MINIC_RX_SIZE 7'hc
`define ADDR_MINIC_RX_AVAIL 7'h10
`define ADDR_MINIC_TSR0 7'h14
`define MINIC_TSR0_VALID_OFFSET 0
`define MINIC_TSR0_VALID 32'h00000001
`define MINIC_TSR0_PID_OFFSET 1
`define MINIC_TSR0_PID 32'h0000003e
`define MINIC_TSR0_FID_OFFSET 6
`define MINIC_TSR0_FID 32'h003fffc0
`define ADDR_MINIC_TSR1 6'h14
`define ADDR_MINIC_TSR1 7'h18
`define MINIC_TSR1_TSVAL_OFFSET 0
`define MINIC_TSR1_TSVAL 32'hffffffff
`define ADDR_MINIC_DBGR 6'h18
`define ADDR_MINIC_DBGR 7'h1c
`define MINIC_DBGR_IRQ_CNT_OFFSET 0
`define MINIC_DBGR_IRQ_CNT 32'h00ffffff
`define MINIC_DBGR_WB_IRQ_VAL_OFFSET 24
`define MINIC_DBGR_WB_IRQ_VAL 32'h01000000
`define ADDR_MINIC_MPROT 6'h1c
`define ADDR_MINIC_MPROT 7'h20
`define MINIC_MPROT_LO_OFFSET 0
`define MINIC_MPROT_LO 32'h0000ffff
`define MINIC_MPROT_HI_OFFSET 16
`define MINIC_MPROT_HI 32'hffff0000
`define ADDR_MINIC_EIC_IDR 6'h20
`define ADDR_MINIC_EIC_IDR 7'h40
`define MINIC_EIC_IDR_TX_OFFSET 0
`define MINIC_EIC_IDR_TX 32'h00000001
`define MINIC_EIC_IDR_RX_OFFSET 1
`define MINIC_EIC_IDR_RX 32'h00000002
`define MINIC_EIC_IDR_TXTS_OFFSET 2
`define MINIC_EIC_IDR_TXTS 32'h00000004
`define ADDR_MINIC_EIC_IER 6'h24
`define ADDR_MINIC_EIC_IER 7'h44
`define MINIC_EIC_IER_TX_OFFSET 0
`define MINIC_EIC_IER_TX 32'h00000001
`define MINIC_EIC_IER_RX_OFFSET 1
`define MINIC_EIC_IER_RX 32'h00000002
`define MINIC_EIC_IER_TXTS_OFFSET 2
`define MINIC_EIC_IER_TXTS 32'h00000004
`define ADDR_MINIC_EIC_IMR 6'h28
`define ADDR_MINIC_EIC_IMR 7'h48
`define MINIC_EIC_IMR_TX_OFFSET 0
`define MINIC_EIC_IMR_TX 32'h00000001
`define MINIC_EIC_IMR_RX_OFFSET 1
`define MINIC_EIC_IMR_RX 32'h00000002
`define MINIC_EIC_IMR_TXTS_OFFSET 2
`define MINIC_EIC_IMR_TXTS 32'h00000004
`define ADDR_MINIC_EIC_ISR 6'h2c
`define ADDR_MINIC_EIC_ISR 7'h4c
`define MINIC_EIC_ISR_TX_OFFSET 0
`define MINIC_EIC_ISR_TX 32'h00000001
`define MINIC_EIC_ISR_RX_OFFSET 1
......
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