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White Rabbit core collection
Commit 0f920d9e authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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exploder: enforce clock crossing analysis and build firmware into image

parent 881d7258
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Showing with 120 additions and 115 deletions
syn/gsi_exploder/wr_core_demo/Makefile
View file @ 0f920d9e
......@@ -3,7 +3,7 @@ TARGET = exploder_top
QUARTUS ?= /opt/quartus
QUARTUS_BIN = $(QUARTUS)/bin
all: $(TARGET).jam
all: $(TARGET).jic $(TARGET).jam
clean:
rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt
......@@ -11,7 +11,6 @@ clean:
rm -f $(TARGET).jam $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep
%.sof: %.qsf
hdlmake
$(QUARTUS_BIN)/quartus_map $*
$(QUARTUS_BIN)/quartus_fit $*
$(QUARTUS_BIN)/quartus_asm $*
......
top/gsi_exploder/wr_core_demo/exploder_top.vhd
View file @ 0f920d9e
......@@ -346,7 +346,7 @@ architecture rtl of exploder_top is
signal rstn_ref : std_logic;
-- DMTD PLL from clk_20m_vcxo_i
signal dmtd_locked : std_logic;
--signal dmtd_locked : std_logic;
signal clk_dmtd : std_logic;
signal dac_hpll_load_p1 : std_logic;
......@@ -435,7 +435,7 @@ begin
dmtd_inst : dmtd_pll port map(
inclk0 => clk_20m_vcxo_i, -- 20 Mhz
c0 => clk_dmtd, -- 62.5MHz
locked => dmtd_locked);
locked => open); -- dmtd_locked);
ref_inst : ref_pll port map(
inclk0 => clk_125m_pllref_i, -- 125 MHz
......@@ -477,7 +477,7 @@ begin
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "",
g_dpram_initf => "../../../ip_cores/wrpc-sw/wrc.mif",
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
......
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