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White Rabbit core collection
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White Rabbit core collection
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1254a4f7
Commit
1254a4f7
authored
Oct 04, 2018
by
Tomasz Wlostowski
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wr_endpoint: removed unused signals/declarations in ep_rx_path
parent
0fb97d73
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-29
ep_rx_path.vhd
modules/wr_endpoint/ep_rx_path.vhd
+1
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modules/wr_endpoint/ep_rx_path.vhd
View file @
1254a4f7
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Created : 2009-06-22
-- Last update: 201
7-02-02
-- Last update: 201
8-10-03
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -115,34 +115,6 @@ end ep_rx_path;
...
@@ -115,34 +115,6 @@ end ep_rx_path;
architecture
behavioral
of
ep_rx_path
is
architecture
behavioral
of
ep_rx_path
is
type
t_rx_deframer_state
is
(
RXF_IDLE
,
RXF_DATA
,
RXF_FLUSH_STALL
,
RXF_FINISH_CYCLE
,
RXF_THROW_ERROR
);
signal
state
:
t_rx_deframer_state
;
signal
gap_cntr
:
unsigned
(
3
downto
0
);
-- new sigs
signal
counter
:
unsigned
(
7
downto
0
);
signal
rxdata_saved
:
std_logic_vector
(
15
downto
0
);
signal
next_hdr
:
std_logic
;
signal
is_pause
:
std_logic
;
signal
data_firstword
:
std_logic
;
signal
flush_stall
:
std_logic
;
signal
stb_int
:
std_logic
;
signal
fab_int
:
t_ep_internal_fabric
;
signal
dreq_int
:
std_logic
;
signal
ack_count
:
unsigned
(
7
downto
0
);
signal
src_out_int
:
t_wrf_source_out
;
signal
tmp_sel
:
std_logic
;
signal
tmp_dat
:
std_logic_vector
(
15
downto
0
);
signal
fab_pipe
:
t_fab_pipe
(
0
to
9
);
signal
fab_pipe
:
t_fab_pipe
(
0
to
9
);
signal
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
signal
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
...
...
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