added module containing all the platform-dependent stuff needed for WRPC

- this new module contains the PLLs, buffers, PHY and DAC arbiter that would be usually copied in the top_level of each design - it was created to make integration of WRPC in user's design easier and cleaner - it is expected to be extended with more families in which case, only the PHY is expected to change - similar module will be created for Altera

added module containing all the platform-dependent stuff needed for WRPC
- this new module contains the PLLs, buffers, PHY and DAC arbiter that would be usually copied in the top_level of each design - it was created to make integration of WRPC in user's design easier and cleaner - it is expected to be extended with more families in which case, only the PHY is expected to change - similar module will be created for Altera
12df4287 · Maciej Lipinski · ef95a3eb · 12df4287 · 12df4287 · 12df4287
Commit 12df4287 authored Oct 27, 2016 by Maciej Lipinski
Showing with 442 additions and 2 deletions

Manifest.py platform/xilinx/Manifest.py +2 -2

wr_xilinx_pkg.vhd platform/xilinx/wr_xilinx_pkg.vhd +88 -0

xwrc_platform_xilinx.vhd platform/xilinx/xwrc_platform_xilinx.vhd +352 -0

No files found.
--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
-files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd" ]
-modules = {"local" : ["wr_gtp_phy"]}
\ No newline at end of file
+files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd", "xwrc_platform_xilinx.vhd" ]
+modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -9,6 +9,94 @@ use work.wr_fabric_pkg.all;

 package wr_xilinx_pkg is

+  -------------------------------------------------------------------------------------------
+  -- records used as interface between WRPC and platform-specific module xwrc_platform_xilinx
+  -------------------------------------------------------------------------------------------
+  type t_sfp_from_wrc is record
+    scl  : std_logic;
+    sda  : std_logic;
+  end record;
+
+  type t_sfp_to_wrc is record
+    scl      : std_logic;
+    sda      : std_logic;
+    det      : std_logic;
+  end record;
+
+  type t_dacs_from_wrc is record
+    hpll_load_p1   : std_logic;
+    hpll_data      : std_logic_vector(15 downto 0);
+    dpll_load_p1   : std_logic;
+    dpll_data      : std_logic_vector(15 downto 0);
+  end record;
+
+  type t_phy_8bits_to_wrc is record
+    ref_clk        : std_logic;
+    tx_disparity   : std_logic;
+    tx_enc_err     : std_logic;
+    rx_data        : std_logic_vector(7 downto 0);
+    rx_rbclk       : std_logic;
+    rx_k           : std_logic_vector(0 downto 0);
+    rx_enc_err     : std_logic;
+    rx_bitslide    : std_logic_vector(3 downto 0);
+    rdy            : std_logic;
+    sfp_tx_fault   : std_logic;
+    sfp_los        : std_logic;
+  end record;
+  type t_phy_8bits_from_wrc is record
+    tx_data        : std_logic_vector(7 downto 0);
+    tx_k           : std_logic_vector(0 downto 0);
+    rst            : std_logic;
+    loopen         : std_logic;
+    loopen_vec     : std_logic_vector(2 downto 0);
+    tx_prbs_sel    : std_logic_vector(2 downto 0);
+    sfp_tx_disable : std_logic;
+  end record;
+
+  -------------------------------------------------------------------------------------------
+  component xwrc_platform_xilinx
+    generic
+    (
+      g_simulation         :       integer := 0;
+      g_family             :       string  := "spartan6"
+    );
+    port (
+      local_reset_n_i      : in    std_logic;
+      clk_20m_vcxo_i       : in    std_logic;                     -- 20MHz VCXO clock
+      clk_125m_pllref_p_i  : in    std_logic;                     -- 125 MHz PLL reference
+      clk_125m_pllref_n_i  : in    std_logic;
+      clk_125m_gtp_n_i     : in    std_logic;                     -- 125 MHz GTP reference
+      clk_125m_gtp_p_i     : in    std_logic;                     -- 125 MHz GTP reference
+      dac_sclk_o           : out   std_logic;                      -- Serial Clock Line
+      dac_din_o            : out   std_logic;                      -- Serial Data Line
+      dac_clr_n_o          : out   std_logic;                      -- ?
+      dac_cs1_n_o          : out   std_logic;                      -- Chip Select
+      dac_cs2_n_o          : out   std_logic;                      -- Chip Select
+      carrier_onewire_b    : inout std_logic := '1';               -- read temperature sensor
+      sfp_txp_o            : out   std_logic;
+      sfp_txn_o            : out   std_logic;
+      sfp_rxp_i            : in    std_logic;
+      sfp_rxn_i            : in    std_logic;
+      sfp_mod_def0_i       : in    std_logic;                      -- sfp detect
+      sfp_mod_def1_b       : inout std_logic;                      -- Config-I2C: Clk  Line
+      sfp_mod_def2_b       : inout std_logic;                      -- Config-I2C: Data Line
+      sfp_rate_select_b    : inout std_logic;
+      sfp_tx_fault_i       : in    std_logic;
+      sfp_tx_disable_o     : out   std_logic;
+      sfp_los_i            : in    std_logic;
+      clk_62m5_sys_o       : out std_logic;
+      clk_125m_pllref_o    : out std_logic;
+      clk_62m5_dmtd_o      : out std_logic;
+      dacs_i               : in  t_dacs_from_wrc;
+      phy_o                : out t_phy_8bits_to_wrc;
+      phy_i                : in  t_phy_8bits_from_wrc;
+      owr_en_i             : in  std_logic_vector(1 downto 0);
+      owr_o                : out std_logic_vector(1 downto 0);
+      sfp_config_o         : out t_sfp_to_wrc;
+      sfp_config_i         : in  t_sfp_from_wrc
+      );
+  end component;
+
  component wr_gtp_phy_spartan6
    generic (
      g_enable_ch0 : integer := 1;

--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd