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White Rabbit core collection
Commit 13565ccf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_core: addig aux input/output for snmp diagnostics

parent 817b17f1
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Showing with 407 additions and 42 deletions
modules/wrc_core/wr_core.vhd
View file @ 13565ccf
......@@ -97,7 +97,11 @@ entity wr_core is
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false);
g_pcs_16bit : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port(
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -286,7 +290,13 @@ entity wr_core is
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic
link_ok_o : out std_logic;
-------------------------------------
-- DIAG to/from external modules
-------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
end wr_core;
......@@ -774,7 +784,11 @@ begin
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_mem_words => g_dpram_size,
g_vuart_fifo_size => g_vuart_fifo_size)
g_vuart_fifo_size => g_vuart_fifo_size,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -808,7 +822,10 @@ begin
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i
owr_i => owr_i,
diag_array_in => aux_diag_i,
diag_array_out => aux_diag_o
);
U_Adapter : wb_slave_adapter
......
modules/wrc_core/wrc_periph.vhd
View file @ 13565ccf
......@@ -37,7 +37,11 @@ entity wrc_periph is
g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500;
g_mem_words : integer := 16384; --in 32-bit words
g_vuart_fifo_size : integer := 1024
g_vuart_fifo_size : integer := 1024;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port(
clk_sys_i : in std_logic;
......@@ -74,7 +78,11 @@ entity wrc_periph is
-- 1-Wire
owr_pwren_o: out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0)
owr_i : in std_logic_vector(1 downto 0);
-- optional diagnostics from external HDL modules
diag_array_in : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
end wrc_periph;
......@@ -96,6 +104,10 @@ architecture struct of wrc_periph is
signal cntr_overflow : std_logic;
signal rst_wrc_n_o_reg : std_logic := '1';
signal diag_adr : unsigned(15 downto 0);
signal diag_dat : std_logic_vector(31 downto 0);
signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
signal diag_in : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
begin
......@@ -279,6 +291,69 @@ begin
sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
-------------------------------------
-- DIAG to/from external modules
-------------------------------------
-- first, provide all the constants
sysc_regs_i.diag_info_id_i <= std_logic_vector(to_unsigned(g_diag_id, 16));
sysc_regs_i.diag_info_ver_i <= std_logic_vector(to_unsigned(g_diag_ver, 16));
sysc_regs_i.diag_nw_ro_i <= std_logic_vector(to_unsigned(g_diag_ro_size, 16));
sysc_regs_i.diag_nw_rw_i <= std_logic_vector(to_unsigned(g_diag_rw_size, 16));
diag_array_out <= diag_out_regs;
-- r/w registers can be also read
diag_in(g_diag_rw_size - 1 downto 0) <= diag_out_regs;
-- r/o array after r/w registers for reading
diag_in(g_diag_ro_size + g_diag_rw_size-1 downto g_diag_rw_size) <= diag_array_in;
p_diag_rw: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
diag_adr <= (others=>'0');
diag_dat <= (others=>'0');
else
if sysc_regs_o.diag_cr_adr_load_o = '1' then
diag_adr <= unsigned(sysc_regs_o.diag_cr_adr_o);
end if;
if sysc_regs_o.diag_dat_load_o = '1' then
diag_dat <= sysc_regs_o.diag_dat_o;
end if;
end if;
end if;
end process;
sysc_regs_i.diag_cr_adr_i <= std_logic_vector(diag_adr);
GEN_DIAG_NODAT: if g_diag_rw_size = 0 and g_diag_ro_size = 0 generate
sysc_regs_i.diag_dat_i <= (others=>'0');
end generate;
GEN_DIAG_DAT: if g_diag_rw_size /= 0 or g_diag_ro_size /= 0 generate
sysc_regs_i.diag_dat_i <= diag_in(to_integer(diag_adr));
end generate;
-- Write request for each r/w register
GEN_DIAG_W: if g_diag_rw_size > 0 generate
GEN_LOOP: for I in 0 to g_diag_rw_size-1 generate
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
diag_out_regs(I) <= (others=>'0');
elsif sysc_regs_o.diag_cr_adr_load_o = '1' and sysc_regs_o.diag_cr_rw_o = '1' and
to_integer(unsigned(sysc_regs_o.diag_cr_adr_o)) = I then
diag_out_regs(I) <= diag_dat;
end if;
end if;
end process;
end generate;
end generate;
GEN_NODIAG_W: if g_diag_rw_size = 0 generate
diag_array_out <= (others=>(others=>'0'));
end generate;
----------------------------------------
-- SYSCON
----------------------------------------
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 13565ccf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Thu Aug 6 16:05:38 2015
-- Created : Mon Jul 11 14:59:51 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -34,6 +34,12 @@ package sysc_wbgen2_pkg is
hwfr_memsize_i : std_logic_vector(3 downto 0);
tcr_tdiv_i : std_logic_vector(11 downto 0);
tvr_i : std_logic_vector(31 downto 0);
diag_info_ver_i : std_logic_vector(15 downto 0);
diag_info_id_i : std_logic_vector(15 downto 0);
diag_nw_rw_i : std_logic_vector(15 downto 0);
diag_nw_ro_i : std_logic_vector(15 downto 0);
diag_cr_adr_i : std_logic_vector(15 downto 0);
diag_dat_i : std_logic_vector(31 downto 0);
end record;
constant c_sysc_in_registers_init_value: t_sysc_in_registers := (
......@@ -50,7 +56,13 @@ package sysc_wbgen2_pkg is
gpsr_spi_miso_i => '0',
hwfr_memsize_i => (others => '0'),
tcr_tdiv_i => (others => '0'),
tvr_i => (others => '0')
tvr_i => (others => '0'),
diag_info_ver_i => (others => '0'),
diag_info_id_i => (others => '0'),
diag_nw_rw_i => (others => '0'),
diag_nw_ro_i => (others => '0'),
diag_cr_adr_i => (others => '0'),
diag_dat_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -86,6 +98,11 @@ package sysc_wbgen2_pkg is
gpcr_spi_cs_o : std_logic;
gpcr_spi_mosi_o : std_logic;
tcr_enable_o : std_logic;
diag_cr_adr_o : std_logic_vector(15 downto 0);
diag_cr_adr_load_o : std_logic;
diag_cr_rw_o : std_logic;
diag_dat_o : std_logic_vector(31 downto 0);
diag_dat_load_o : std_logic;
end record;
constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
......@@ -118,7 +135,12 @@ package sysc_wbgen2_pkg is
gpcr_spi_sclk_o => '0',
gpcr_spi_cs_o => '0',
gpcr_spi_mosi_o => '0',
tcr_enable_o => '0'
tcr_enable_o => '0',
diag_cr_adr_o => (others => '0'),
diag_cr_adr_load_o => '0',
diag_cr_rw_o => '0',
diag_dat_o => (others => '0'),
diag_dat_load_o => '0'
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -163,6 +185,12 @@ tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gp
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i);
tmp.diag_info_id_i := f_x_to_zero(left.diag_info_id_i) or f_x_to_zero(right.diag_info_id_i);
tmp.diag_nw_rw_i := f_x_to_zero(left.diag_nw_rw_i) or f_x_to_zero(right.diag_nw_rw_i);
tmp.diag_nw_ro_i := f_x_to_zero(left.diag_nw_ro_i) or f_x_to_zero(right.diag_nw_ro_i);
tmp.diag_cr_adr_i := f_x_to_zero(left.diag_cr_adr_i) or f_x_to_zero(right.diag_cr_adr_i);
tmp.diag_dat_i := f_x_to_zero(left.diag_dat_i) or f_x_to_zero(right.diag_dat_i);
return tmp;
end function;
end package body;
modules/wrc_core/wrc_syscon_regs.h
View file @ 13565ccf
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Thu Aug 6 16:05:39 2015
* Created : Mon Jul 11 14:59:51 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -135,6 +135,47 @@
#define SYSC_TCR_ENABLE WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Timer Counter Value Register */
/* definitions for register: User Diag: version register */
/* definitions for field: Ver in reg: User Diag: version register */
#define SYSC_DIAG_INFO_VER_MASK WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_INFO_VER_SHIFT 0
#define SYSC_DIAG_INFO_VER_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_INFO_VER_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Id in reg: User Diag: version register */
#define SYSC_DIAG_INFO_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define SYSC_DIAG_INFO_ID_SHIFT 16
#define SYSC_DIAG_INFO_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_DIAG_INFO_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: User Diag: number of words */
/* definitions for field: Read/write words in reg: User Diag: number of words */
#define SYSC_DIAG_NW_RW_MASK WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_NW_RW_SHIFT 0
#define SYSC_DIAG_NW_RW_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_NW_RW_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Read-only words in reg: User Diag: number of words */
#define SYSC_DIAG_NW_RO_MASK WBGEN2_GEN_MASK(16, 16)
#define SYSC_DIAG_NW_RO_SHIFT 16
#define SYSC_DIAG_NW_RO_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_DIAG_NW_RO_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: User Diag: Control Register */
/* definitions for field: Address in reg: User Diag: Control Register */
#define SYSC_DIAG_CR_ADR_MASK WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_CR_ADR_SHIFT 0
#define SYSC_DIAG_CR_ADR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_CR_ADR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: R/W in reg: User Diag: Control Register */
#define SYSC_DIAG_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: User Diag: data to read/write */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
......@@ -147,4 +188,12 @@
#define SYSC_REG_TCR 0x00000010
/* [0x14]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x00000014
/* [0x18]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x00000018
/* [0x1c]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x0000001c
/* [0x20]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000020
/* [0x24]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x00000024
#endif
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 13565ccf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Thu Aug 6 16:05:38 2015
-- Created : Mon Jul 11 14:59:51 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -21,7 +21,7 @@ entity wrc_syscon_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -63,11 +63,12 @@ signal sysc_gpcr_spi_cs_int : std_logic ;
signal sysc_gpcr_spi_mosi_dly0 : std_logic ;
signal sysc_gpcr_spi_mosi_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
signal sysc_diag_cr_rw_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -112,6 +113,9 @@ begin
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
sysc_tcr_enable_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
sysc_diag_cr_rw_int <= '0';
regs_o.diag_dat_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -138,6 +142,8 @@ begin
sysc_gpcr_spi_sclk_int <= '0';
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
regs_o.diag_cr_adr_load_o <= '0';
regs_o.diag_dat_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.rstr_trig_wr_o <= '0';
......@@ -148,11 +154,13 @@ begin
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
regs_o.diag_cr_adr_load_o <= '0';
regs_o.diag_dat_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
regs_o.rstr_trig_wr_o <= '1';
sysc_rstr_rst_int <= wrdata_reg(28);
......@@ -191,7 +199,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
when "0001" =>
if (wb_we_i = '1') then
sysc_gpsr_led_stat_int <= wrdata_reg(0);
sysc_gpsr_led_link_int <= wrdata_reg(1);
......@@ -238,7 +246,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "010" =>
when "0010" =>
if (wb_we_i = '1') then
sysc_gpcr_led_stat_int <= wrdata_reg(0);
sysc_gpcr_led_link_int <= wrdata_reg(1);
......@@ -293,7 +301,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "011" =>
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.hwfr_memsize_i;
......@@ -327,7 +335,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "0100" =>
if (wb_we_i = '1') then
sysc_tcr_enable_int <= wrdata_reg(31);
end if;
......@@ -354,12 +362,57 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tvr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i;
rddata_reg(31 downto 16) <= regs_i.diag_info_id_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i;
rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
regs_o.diag_cr_adr_load_o <= '1';
sysc_diag_cr_rw_int <= wrdata_reg(31);
end if;
rddata_reg(15 downto 0) <= regs_i.diag_cr_adr_i;
rddata_reg(31) <= sysc_diag_cr_rw_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
regs_o.diag_dat_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.diag_dat_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -557,6 +610,16 @@ begin
-- Timer Enable
regs_o.tcr_enable_o <= sysc_tcr_enable_int;
-- Timer Counter Value
-- Ver
-- Id
-- Read/write words
-- Read-only words
-- Address
regs_o.diag_cr_adr_o <= wrdata_reg(15 downto 0);
-- R/W
regs_o.diag_cr_rw_o <= sysc_diag_cr_rw_int;
-- Data
regs_o.diag_dat_o <= wrdata_reg(31 downto 0);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 13565ccf
......@@ -311,4 +311,88 @@ peripheral {
};
reg {
name = "User Diag: version register";
prefix = "DIAG_INFO";
field {
name = "Ver";
prefix = "VER";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Id";
prefix = "ID";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "User Diag: number of words";
prefix = "DIAG_NW";
field {
name = "Read/write words";
prefix = "RW";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Read-only words";
prefix = "RO";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "User Diag: Control Register";
prefix = "DIAG_CR";
field {
name = "Address";
prefix = "ADR";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "R/W";
prefix = "RW";
size = 1;
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "User Diag: data to read/write";
prefix = "DIAG_DAT";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
modules/wrc_core/wrcore_pkg.vhd
View file @ 13565ccf
......@@ -13,6 +13,8 @@ package wrcore_pkg is
function f_refclk_rate(pcs_16 : boolean) return integer;
type t_generic_word_array is array (natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
......@@ -195,7 +197,11 @@ package wrcore_pkg is
g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500;
g_mem_words : integer := 16384;
g_vuart_fifo_size : integer := 1024
g_vuart_fifo_size : integer := 1024;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port(
clk_sys_i : in std_logic;
......@@ -226,7 +232,9 @@ package wrcore_pkg is
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0)
owr_i : in std_logic_vector(1 downto 0);
diag_array_in : in t_generic_word_array(g_diag_ro_size-1 downto 0);
diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
end component;
......@@ -292,7 +300,6 @@ package wrcore_pkg is
constant cc_unused_master_in : t_wishbone_master_in :=
('1', '0', '0', '0', '0', cc_dummy_data);
type t_generic_word_array is array (natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------
-- Public WR component definitions
-----------------------------------------------------------------------------
......@@ -314,7 +321,11 @@ package wrcore_pkg is
g_vuart_fifo_size : integer := 1024;
g_snmp_array_in : integer := 0;
g_snmp_array_out : integer := 0;
g_pcs_16bit : boolean := false);
g_pcs_16bit : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0';
......@@ -409,10 +420,10 @@ package wrcore_pkg is
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
snmp_word_array_i : in t_generic_word_array(g_snmp_array_in-1 downto 0) := (others =>(others=>'0'));
snmp_word_array_o : out t_generic_word_array(g_snmp_array_out-1 downto 0);
link_ok_o : out std_logic;
link_ok_o : out std_logic
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
end component;
......@@ -435,7 +446,11 @@ package wrcore_pkg is
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false);
g_pcs_16bit : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port(
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -622,7 +637,13 @@ package wrcore_pkg is
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic
link_ok_o : out std_logic;
-------------------------------------
-- DIAG to/from external modules
-------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
end component;
......
modules/wrc_core/xwr_core.vhd
View file @ 13565ccf
......@@ -83,7 +83,11 @@ entity xwr_core is
g_vuart_fifo_size : integer := 1024;
g_snmp_array_in : integer := 0;
g_snmp_array_out : integer := 0;
g_pcs_16bit : boolean := false);
g_pcs_16bit : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port(
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -233,8 +237,8 @@ entity xwr_core is
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
snmp_word_array_i : in t_generic_word_array(g_snmp_array_in-1 downto 0) := (others =>(others=>'0'));
snmp_word_array_o : out t_generic_word_array(g_snmp_array_out-1 downto 0);
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
link_ok_o : out std_logic
);
......@@ -259,7 +263,12 @@ begin
g_aux_sdb => g_aux_sdb,
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit)
g_pcs_16bit => g_pcs_16bit,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size
)
port map(
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -388,7 +397,10 @@ begin
dio_o => dio_o,
rst_aux_n_o => rst_aux_n_o,
link_ok_o => link_ok_o
link_ok_o => link_ok_o,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o
);
timestamps_o.port_id(5) <= '0';
......
modules/wrc_core/xwr_syscon_wb.vhd
View file @ 13565ccf
......@@ -50,7 +50,7 @@ architecture syn of xwr_syscon_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -96,7 +96,7 @@ begin
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_adr_i => wb_in.adr(3 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......
sim/wrc_syscon_regs.vh
View file @ 13565ccf
`define ADDR_SYSC_RSTR 5'h0
`define ADDR_SYSC_RSTR 6'h0
`define SYSC_RSTR_TRIG_OFFSET 0
`define SYSC_RSTR_TRIG 32'h0fffffff
`define SYSC_RSTR_RST_OFFSET 28
`define SYSC_RSTR_RST 32'h10000000
`define ADDR_SYSC_GPSR 5'h4
`define ADDR_SYSC_GPSR 6'h4
`define SYSC_GPSR_LED_STAT_OFFSET 0
`define SYSC_GPSR_LED_STAT 32'h00000001
`define SYSC_GPSR_LED_LINK_OFFSET 1
......@@ -32,7 +32,7 @@
`define SYSC_GPSR_SPI_MOSI 32'h00001000
`define SYSC_GPSR_SPI_MISO_OFFSET 13
`define SYSC_GPSR_SPI_MISO 32'h00002000
`define ADDR_SYSC_GPCR 5'h8
`define ADDR_SYSC_GPCR 6'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
`define SYSC_GPCR_LED_LINK_OFFSET 1
......@@ -51,12 +51,28 @@
`define SYSC_GPCR_SPI_CS 32'h00000800
`define SYSC_GPCR_SPI_MOSI_OFFSET 12
`define SYSC_GPCR_SPI_MOSI 32'h00001000
`define ADDR_SYSC_HWFR 5'hc
`define ADDR_SYSC_HWFR 6'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
`define ADDR_SYSC_TCR 5'h10
`define ADDR_SYSC_TCR 6'h10
`define SYSC_TCR_TDIV_OFFSET 0
`define SYSC_TCR_TDIV 32'h00000fff
`define SYSC_TCR_ENABLE_OFFSET 31
`define SYSC_TCR_ENABLE 32'h80000000
`define ADDR_SYSC_TVR 5'h14
`define ADDR_SYSC_TVR 6'h14
`define ADDR_SYSC_DIAG_INFO 6'h18
`define SYSC_DIAG_INFO_VER_OFFSET 0
`define SYSC_DIAG_INFO_VER 32'h0000ffff
`define SYSC_DIAG_INFO_ID_OFFSET 16
`define SYSC_DIAG_INFO_ID 32'hffff0000
`define ADDR_SYSC_DIAG_NW 6'h1c
`define SYSC_DIAG_NW_RW_OFFSET 0
`define SYSC_DIAG_NW_RW 32'h0000ffff
`define SYSC_DIAG_NW_RO_OFFSET 16
`define SYSC_DIAG_NW_RO 32'hffff0000
`define ADDR_SYSC_DIAG_CR 6'h20
`define SYSC_DIAG_CR_ADR_OFFSET 0
`define SYSC_DIAG_CR_ADR 32'h0000ffff
`define SYSC_DIAG_CR_RW_OFFSET 31
`define SYSC_DIAG_CR_RW 32'h80000000
`define ADDR_SYSC_DIAG_DAT 6'h24
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