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White Rabbit core collection
Commit 15976b4b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbenches: updates for wrc_core, wr_minic_with_ep

parent d824935e
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Showing with 46 additions and 116 deletions
testbench/wr_minic_with_ep/ep2ep_wrapper.svh
View file @ 15976b4b
......@@ -191,7 +191,7 @@ module ep2ep_wrapper
.phy_rx_enc_err_i (1'b0),
.phy_rx_bitslide_i (5'b0),
.src_dat_o (src_b.dat_i),
.src_dat_o (src_b.dat_o),
.src_adr_o (src_b.adr),
.src_sel_o (src_b.sel),
.src_cyc_o (src_b.cyc),
......@@ -199,7 +199,8 @@ module ep2ep_wrapper
.src_we_o (src_b.we),
.src_stall_i (src_b.stall),
.src_ack_i (src_b.ack),
.src_err_i (src_b.err),
.snk_dat_i (snk_b.dat_i[15:0]),
.snk_adr_i (snk_b.adr[1:0]),
.snk_sel_i (snk_b.sel[1:0]),
......@@ -230,6 +231,9 @@ module ep2ep_wrapper
.wb_ack_o (sys_b.ack)
);
task ep_init(CWishboneAccessor acc);
acc.set_mode(CLASSIC);
acc.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
......
testbench/wr_minic_with_ep/main.sv
View file @ 15976b4b
......@@ -8,6 +8,7 @@
`include "ep2ep_wrapper.svh"
module main;
reg clk_ref = 1'b0;
......@@ -15,8 +16,8 @@ module main;
reg rst_n = 1'b0;
always #4ns clk_ref <= ~clk_ref;
always@(posedge clk_ref) clk_sys <= ~clk_sys;
always #3900ps clk_ref <= ~clk_ref;
always #8ns clk_sys <= ~clk_sys;
initial begin
......@@ -113,15 +114,15 @@ module main;
.src_err_i (minic2ep.slave.err),
.src_ack_i (minic2ep.slave.ack),
.snk_dat_i (ep2minic.master.dat_o),
.snk_adr_i (ep2minic.master.adr),
.snk_sel_i (ep2minic.master.sel),
.snk_cyc_i (ep2minic.master.cyc),
.snk_stb_i (ep2minic.master.stb),
.snk_we_i (ep2minic.master.we),
.snk_stall_o (ep2minic.master.stall),
.snk_err_o (ep2minic.master.err),
.snk_ack_o (ep2minic.master.ack),
.snk_dat_i (ep2minic.dat_o),
.snk_adr_i (ep2minic.adr),
.snk_sel_i (ep2minic.sel),
.snk_cyc_i (ep2minic.cyc),
.snk_stb_i (ep2minic.stb),
.snk_we_i (ep2minic.we),
.snk_stall_o (ep2minic.stall),
.snk_err_o (ep2minic.err),
.snk_ack_o (ep2minic.ack),
.txtsu_port_id_i (5'b0),
.txtsu_frame_id_i (16'b0),
......@@ -129,6 +130,7 @@ module main;
.txtsu_valid_i (1'b0),
.txtsu_ack_o (),
.wb_cyc_i (U_sys_bus_master.cyc),
.wb_stb_i (U_sys_bus_master.stb),
......@@ -180,7 +182,7 @@ module main;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE | EthPacketGenerator::TX_OOB | EthPacketGenerator::EVEN_LENGTH) ;
gen.set_template(tmpl);
gen.set_size(60,1500);
gen.set_size(100,200);
for(i=0;i<n_packets;i++)
begin
......@@ -225,7 +227,7 @@ module main;
EthPacketGenerator gen = new;
EthPacket pkt, tmpl;
EthPacket txed[$];
int i;
int i, cnt;
......@@ -245,10 +247,9 @@ module main;
minic.init();
test_tx_path(10000, minic, sink);
// test_tx_path(3000, minic, sink);
/* -----\/----- EXCLUDED -----\/-----
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
......@@ -256,11 +257,15 @@ module main;
tmpl.has_smac = 1;
tmpl.is_q = 0;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /-*| EthPacketGenerator::RX_OOB*-/) ;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(60,1500);
gen.set_size(60,150);
#10us;
cnt = 0;
fork
forever
begin
......@@ -272,6 +277,8 @@ module main;
EthPacket rxp, sent;
minic.recv(rxp);
sent = txed.pop_front();
cnt ++;
if(!sent.equal(rxp, EthPacket::CMP_OOB))
begin
sent.dump();
......@@ -279,6 +286,10 @@ module main;
$stop;
end
else
$display("Rx: %x cnt %d", rxp.ethertype, cnt);
end
......@@ -287,7 +298,7 @@ module main;
// forever
begin
for(i=0;i<100;i++)
for(i=0;i<205;i++)
begin
pkt = gen.gen();
src.send(pkt);
......@@ -312,7 +323,6 @@ module main;
-----/\----- EXCLUDED -----/\----- */
end // initial begin
......
testbench/wr_minic_with_ep/wave.do
View file @ 15976b4b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/minic2ep/g_data_width
add wave -noupdate /main/minic2ep/g_addr_width
add wave -noupdate /main/minic2ep/adr
add wave -noupdate /main/minic2ep/dat_o
add wave -noupdate /main/minic2ep/dat_i
add wave -noupdate /main/minic2ep/sel
add wave -noupdate /main/minic2ep/ack
add wave -noupdate /main/minic2ep/stall
add wave -noupdate /main/minic2ep/err
add wave -noupdate /main/minic2ep/rty
add wave -noupdate /main/minic2ep/cyc
add wave -noupdate /main/minic2ep/stb
add wave -noupdate /main/minic2ep/we
add wave -noupdate -divider sink
add wave -noupdate /main/U_wrf_sink/g_addr_width
add wave -noupdate /main/U_wrf_sink/g_data_width
add wave -noupdate /main/U_wrf_sink/clk_i
add wave -noupdate /main/U_wrf_sink/rst_n_i
add wave -noupdate /main/U_wrf_sink/adr
add wave -noupdate /main/U_wrf_sink/dat_i
add wave -noupdate /main/U_wrf_sink/sel
add wave -noupdate /main/U_wrf_sink/dat_o
add wave -noupdate /main/U_wrf_sink/ack
add wave -noupdate /main/U_wrf_sink/stall
add wave -noupdate /main/U_wrf_sink/err
add wave -noupdate /main/U_wrf_sink/rty
add wave -noupdate /main/U_wrf_sink/cyc
add wave -noupdate /main/U_wrf_sink/stb
add wave -noupdate /main/U_wrf_sink/we
add wave -noupdate /main/U_wrf_sink/last_access_t
add wave -noupdate /main/U_wrf_sink/cyc_prev
add wave -noupdate /main/U_wrf_sink/trans_index
add wave -noupdate /main/U_wrf_sink/first_transaction
add wave -noupdate /main/U_wrf_sink/settings
add wave -noupdate /main/U_wrf_sink/cyc_start
add wave -noupdate /main/U_wrf_sink/cyc_end
add wave -noupdate /main/U_wrf_sink/clk_i
add wave -noupdate /main/U_wrf_sink/rst_n_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_vlans
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_dpi_classifier
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rtu
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rx_buffer
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_rx_buffer_size
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_sys_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_rx_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_sys_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_rx_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fab_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_busy_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_p_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_delay_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_buffer_occupation_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rmon_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/regs_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_full_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_valid_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/state
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/gap_cntr
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/counter
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rxdata_saved
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/next_hdr
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/is_pause
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/data_firstword
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/flush_stall
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/stb_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ack_count
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_out_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_sel
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_dat
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_pipe
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_pipe
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_hp
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_pause
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_pause_quanta
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_pclass
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_drop
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tclass
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_vid
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tag_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull
add wave -noupdate /main/DUT/mem_data_o
add wave -noupdate /main/DUT/mem_addr_o
add wave -noupdate /main/DUT/mem_data_i
add wave -noupdate /main/DUT/mem_wr_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {62482422150 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {70088000000 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -104,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {54279296390 fs} {70685547910 fs}
WaveRestoreZoom {0 fs} {1050 us}
testbench/wrc_core/main_tb/main.sv
View file @ 15976b4b
......@@ -90,9 +90,8 @@ module main;
.phy_rx_enc_err_i(phy_rx_enc_err),
.phy_rx_bitslide_i(phy_rx_bitslide),
.phy_rst_o(phy_rst),
.phy_loopen_o(phy_lo),
.phy_loopen_o(phy_lo)
.genrest_n ()
);
assign phy_rx_data = phy_tx_data;
......@@ -110,7 +109,8 @@ module main;
acc = WB.get_accessor();
acc.write('h62000, 'hffffffff);
acc.write('h62000, 'h1);
#3us;
acc.write('h62000, 0);
......
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