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White Rabbit core collection
Commit 1cb9d610 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'switch-v4-merge'

parents 15fd89fd a85a7e00
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Showing with 407 additions and 515 deletions
modules/wrsw_nic/nic_buffer.vhd
View file @ 1cb9d610
......@@ -76,9 +76,10 @@ begin -- syn
RAM : generic_dpram
generic map (
g_data_width => 32,
g_size => 2**g_memsize_log2,
g_dual_clock => false)
g_data_width => 32,
g_size => 2**g_memsize_log2,
g_dual_clock => false,
g_with_byte_enable => false)
port map (
-- host port
rst_n_i => rst_n_i,
......
modules/wrsw_nic/nic_descriptor_manager.vhd
View file @ 1cb9d610
......@@ -28,13 +28,12 @@ library work;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
entity nic_descriptor_manager is
generic (
g_desc_mode : string := "tx";
g_num_descriptors : integer;
g_num_descriptors_log2 : integer);
g_num_descriptors_log2 : integer;
g_port_mask_bits : integer := 32); --worth using only in TX mode
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -77,7 +76,7 @@ end nic_descriptor_manager;
architecture behavioral of nic_descriptor_manager is
type t_desc_arb_state is (ARB_DISABLED, ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
type t_desc_arb_state is (ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
signal state : t_desc_arb_state;
......@@ -85,15 +84,8 @@ architecture behavioral of nic_descriptor_manager is
signal granted_desc_tx : t_tx_descriptor;
signal granted_desc_rx : t_rx_descriptor;
signal granted_desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx_d0 : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_subreg : unsigned(1 downto 0);
signal cntr : unsigned(1 downto 0);
signal check_count : unsigned(g_num_descriptors_log2 downto 0);
signal stupid_hack : std_logic;
impure function f_write_marshalling(index : integer)
return std_logic_vector is
......@@ -112,6 +104,15 @@ begin -- behavioral
cur_desc_idx_o <= std_logic_vector(desc_idx);
--GD can do that, those outputs are validated by desc_grant_o
--and nic_rx_fsm stores it in internal register too
GEN_TXDESC_CUR: if g_desc_mode = "tx" generate
txdesc_current_o <= granted_desc_tx;
end generate;
GEN_RXDESC_CUR: if g_desc_mode = "rx" generate
rxdesc_current_o <= granted_desc_rx;
end generate;
p_rxdesc_arbiter : process(clk_sys_i, rst_n_i)
variable tmp_desc_rx : t_rx_descriptor;
variable tmp_desc_tx : t_tx_descriptor;
......@@ -121,7 +122,7 @@ begin -- behavioral
if(rst_n_i = '0') then
desc_write_done_o <= '0';
desc_grant_o <= '0';
state <= ARB_DISABLED;
state <= ARB_START_SCAN;
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
dtbl_wr_o <= '0';
......@@ -130,36 +131,24 @@ begin -- behavioral
else
case state is
when ARB_DISABLED =>
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
if(enable_i = '1') then
-- dtbl_rd_o <= '1';
state <= ARB_START_SCAN;
desc_idx <= (others => '0');
check_count <= (others => '0');
end if;
when ARB_START_SCAN =>
if(enable_i = '0') then
state <= ARB_DISABLED;
desc_subreg <= (others => '0');
dtbl_wr_o <= '0';
if(enable_i = '1') then
state <= ARB_CHECK_EMPTY;
else
-- wait until the current descriptor is read from the memorry
state <= ARB_CHECK_EMPTY;
-- dtbl_rd_o <='1';
dtbl_wr_o <= '0';
desc_idx <= (others => '0');
end if;
when ARB_CHECK_EMPTY =>
p_unmarshall_rx_descriptor(dtbl_data_i, 1, tmp_desc_rx);
p_unmarshall_tx_descriptor(dtbl_data_i, 1, tmp_desc_tx);
dtbl_wr_o <= '0';
tmp_desc_rx := f_unmarshall_rx_descriptor(dtbl_data_i, 1);
tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 1);
granted_desc_tx <= tmp_desc_tx;
granted_desc_rx <= tmp_desc_rx;
if((tmp_desc_rx.empty = '1' and g_desc_mode = "rx") or (tmp_desc_tx.ready = '1' and g_desc_mode = "tx")) then
granted_desc_tx <= tmp_desc_tx;
granted_desc_rx <= tmp_desc_rx;
desc_subreg <= "01";
state <= ARB_FETCH;
bna_o <= '0';
......@@ -168,21 +157,22 @@ begin -- behavioral
end if;
when ARB_FETCH =>
dtbl_wr_o <= '0';
case desc_subreg is
when "10" => -- ignore the timestamps for RX
-- descriptors (they're
-- write-only by the NIC)
p_unmarshall_tx_descriptor(dtbl_data_i, 2, tmp_desc_tx);
tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 2);
granted_desc_tx.len <= tmp_desc_tx.len;
granted_desc_tx.offset <= tmp_desc_tx.offset;
when "11" =>
p_unmarshall_tx_descriptor(dtbl_data_i, 3, tmp_desc_tx); -- TX
granted_desc_tx.dpm <= tmp_desc_tx.dpm;
tmp_desc_tx := f_unmarshall_tx_descriptor(dtbl_data_i, 3); -- TX
granted_desc_tx.dpm(g_port_mask_bits-1 downto 0) <= tmp_desc_tx.dpm(g_port_mask_bits-1 downto 0);
p_unmarshall_rx_descriptor(dtbl_data_i, 3, tmp_desc_rx); -- RX
tmp_desc_rx := f_unmarshall_rx_descriptor(dtbl_data_i, 3); -- RX
granted_desc_rx.len <= tmp_desc_rx.len;
granted_desc_rx.offset <= tmp_desc_rx.offset;
......@@ -193,67 +183,46 @@ begin -- behavioral
desc_subreg <= desc_subreg + 1;
when ARB_GRANT =>
dtbl_wr_o <= '0';
desc_subreg <= "11";
if(desc_request_next_i = '1') then
desc_grant_o <= '1';
if(g_desc_mode = "tx") then
txdesc_current_o <= granted_desc_tx;
elsif (g_desc_mode = "rx") then
rxdesc_current_o <= granted_desc_rx;
end if;
state <= ARB_UPDATE;
end if;
desc_write_done_o <= '0';
when ARB_UPDATE =>
dtbl_wr_o <= '0';
desc_grant_o <= '0';
desc_subreg <= "11";
if(desc_write_i = '1') then
if(g_desc_mode = "rx") then
granted_desc_rx <= rxdesc_new_i;
elsif(g_desc_mode = "tx") then
granted_desc_tx <= txdesc_new_i;
end if;
desc_subreg <= (others => '0');
-- dtbl_rd_o <= '0';
state <= ARB_WRITE_DESC;
cntr <= "00";
end if;
when ARB_WRITE_DESC =>
cntr <= cntr + 1;
-- fprint(output,l, "WriteDesc %b %b\n",fo(cntr),fo(f_write_marshalling(1)));
case cntr is
when "00" =>
desc_subreg <= "00";
dtbl_data_o <= f_write_marshalling(1);
dtbl_wr_o <= '1';
when "01" =>
desc_subreg <= "01";
dtbl_data_o <= f_write_marshalling(2);
dtbl_wr_o <= '1';
when "10" =>
desc_subreg <= "10";
dtbl_data_o <= f_write_marshalling(3);
dtbl_wr_o <= '1';
when "11" =>
dtbl_wr_o <= '0';
desc_subreg <= (others => '0');
state <= ARB_START_SCAN;
if(desc_reload_current_i = '0') then
desc_idx <= desc_idx + 1;
end if;
desc_write_done_o <= '1';
when others => null;
end case;
dtbl_data_o <= f_write_marshalling(to_integer(desc_subreg));
if(desc_subreg = "10") then
dtbl_wr_o <= '0';
desc_subreg <= "00";
state <= ARB_START_SCAN;
if(desc_reload_current_i = '0') then
desc_idx <= desc_idx + 1;
end if;
desc_write_done_o <= '1';
else
dtbl_wr_o <= '1';
desc_subreg <= desc_subreg + 1;
end if;
when others => null;
end case;
......
modules/wrsw_nic/nic_descriptors_pkg.vhd
View file @ 1cb9d610
......@@ -65,13 +65,11 @@ package nic_descriptors_pkg is
function f_marshall_rx_descriptor(desc : t_rx_descriptor;
regnum : integer) return std_logic_vector;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor);
function f_unmarshall_tx_descriptor(mem_input : std_logic_vector(31 downto 0);
regnum : integer) return t_tx_descriptor;
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor);
function f_unmarshall_rx_descriptor(mem_input : std_logic_vector(31 downto 0);
regnum : integer) return t_rx_descriptor;
function f_resize_slv(x : std_logic_vector;
newsize : integer) return std_logic_vector;
......@@ -95,9 +93,9 @@ package body NIC_descriptors_pkg is
begin
case regnum is
when 1 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
when 2 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when 3 => tmp := desc.dpm;
when 3 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
when 0 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when 1 => tmp := desc.dpm;
when others => null;
end case;
......@@ -108,9 +106,9 @@ package body NIC_descriptors_pkg is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
when 1 => tmp := "0000000000000000" & desc.ts_incorrect & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
when 2 => tmp := desc.ts_f & desc.ts_r;
when 3 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when 3 => tmp := "0000000000000000" & desc.ts_incorrect & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
when 0 => tmp := desc.ts_f & desc.ts_r;
when 1 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when others => null;
end case;
......@@ -119,11 +117,10 @@ package body NIC_descriptors_pkg is
end f_marshall_rx_descriptor;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor) is
function f_unmarshall_tx_descriptor(mem_input : std_logic_vector(31 downto 0); regnum : integer)
return t_tx_descriptor is
variable desc : t_tx_descriptor;
begin
case regnum is
when 1 =>
desc.ts_id := mem_input(31 downto 16);
......@@ -138,13 +135,13 @@ package body NIC_descriptors_pkg is
desc.dpm := mem_input;
when others => null;
end case;
end p_unmarshall_tx_descriptor;
return desc;
end f_unmarshall_tx_descriptor;
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor) is
function f_unmarshall_rx_descriptor(mem_input : std_logic_vector(31 downto 0); regnum : integer)
return t_rx_descriptor is
variable desc : t_rx_descriptor;
begin
case regnum is
when 1 =>
desc.empty := mem_input(0);
......@@ -162,7 +159,8 @@ package body NIC_descriptors_pkg is
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when others => null;
end case;
end p_unmarshall_rx_descriptor;
return desc;
end f_unmarshall_rx_descriptor;
end package body;
modules/wrsw_nic/nic_elastic_buffer.vhd
View file @ 1cb9d610
......@@ -48,7 +48,8 @@ architecture rtl of nic_elastic_buffer is
signal fifo_out_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_usedw : std_logic_vector(log2(g_depth)-1 downto 0);
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal output_valid : std_logic;
signal got_empty : std_logic;
......@@ -105,14 +106,10 @@ begin -- rtl
p_gen_stall : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
if rst_n_i = '0' or fifo_almost_empty = '1' then
stall_int <= '0';
else
if (unsigned(fifo_usedw) < g_depth/2) then
stall_int <= '0';
elsif (unsigned(fifo_usedw) > g_depth-5) then
stall_int <= '1';
end if;
elsif fifo_almost_full = '1' then
stall_int <= '1';
end if;
end if;
end process;
......@@ -135,7 +132,11 @@ begin -- rtl
generic map (
g_data_width => c_fifo_width,
g_size => g_depth,
g_with_count => true)
g_with_almost_empty => true,
g_with_almost_full => true,
g_almost_empty_threshold => g_depth/2,
g_almost_full_threshold => g_depth-5,
g_with_count => false)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
......@@ -145,7 +146,8 @@ begin -- rtl
q_o => fifo_out_ser,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_usedw
almost_empty_o => fifo_almost_empty,
almost_full_o => fifo_almost_full
);
fab_o.data <= fifo_out_ser(15 downto 0);
......
modules/wrsw_nic/nic_rx_fsm.vhd
View file @ 1cb9d610
This diff is collapsed.
modules/wrsw_nic/nic_tx_fsm.vhd
View file @ 1cb9d610
This diff is collapsed.
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @ 1cb9d610
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Fri Jul 5 14:53:50 2013
-- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
......@@ -43,27 +43,25 @@ package nic_wbgen2_pkg is
type t_nic_out_registers is record
cr_rx_en_o : std_logic;
cr_tx_en_o : std_logic;
cr_sw_rst_o : std_logic;
sr_rec_o : std_logic;
sr_rec_load_o : std_logic;
sr_tx_done_o : std_logic;
sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic;
reset_o : std_logic_vector(31 downto 0);
reset_wr_o : std_logic;
end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := (
cr_rx_en_o => '0',
cr_tx_en_o => '0',
cr_sw_rst_o => '0',
sr_rec_o => '0',
sr_rec_load_o => '0',
sr_tx_done_o => '0',
sr_tx_done_load_o => '0',
sr_tx_error_o => '0',
sr_tx_error_load_o => '0',
reset_o => (others => '0'),
reset_wr_o => '0'
sr_tx_error_load_o => '0'
);
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @ 1cb9d610
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Fri Jul 5 14:53:50 2013
-- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
......@@ -69,6 +69,8 @@ architecture syn of nic_wishbone_slave is
signal nic_cr_rx_en_int : std_logic ;
signal nic_cr_tx_en_int : std_logic ;
signal nic_cr_sw_rst_dly0 : std_logic ;
signal nic_cr_sw_rst_int : std_logic ;
signal nic_dtx_rddata_int : std_logic_vector(31 downto 0);
signal nic_dtx_rd_int : std_logic ;
signal nic_dtx_wr_int : std_logic ;
......@@ -114,10 +116,10 @@ begin
rddata_reg <= "00000000000000000000000000000000";
nic_cr_rx_en_int <= '0';
nic_cr_tx_en_int <= '0';
nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -127,10 +129,10 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -139,7 +141,6 @@ begin
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -150,9 +151,11 @@ begin
if (wb_we_i = '1') then
nic_cr_rx_en_int <= wrdata_reg(0);
nic_cr_tx_en_int <= wrdata_reg(1);
nic_cr_sw_rst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= nic_cr_rx_en_int;
rddata_reg(1) <= nic_cr_tx_en_int;
rddata_reg(31) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -182,8 +185,7 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
......@@ -221,44 +223,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
regs_o.reset_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -474,6 +438,19 @@ begin
regs_o.cr_rx_en_o <= nic_cr_rx_en_int;
-- Transmit enable
regs_o.cr_tx_en_o <= nic_cr_tx_en_int;
-- Software Reset
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
nic_cr_sw_rst_dly0 <= '0';
regs_o.cr_sw_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
nic_cr_sw_rst_dly0 <= nic_cr_sw_rst_int;
regs_o.cr_sw_rst_o <= nic_cr_sw_rst_int and (not nic_cr_sw_rst_dly0);
end if;
end process;
-- Buffer Not Available
-- Frame Received
regs_o.sr_rec_o <= wrdata_reg(1);
......@@ -483,9 +460,6 @@ begin
regs_o.sr_tx_error_o <= wrdata_reg(3);
-- Current TX descriptor
-- Current RX descriptor
-- Software reset
-- pass-through field: Software reset in register: SW_Reset
regs_o.reset_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst : wbgen2_dpssram
......
modules/wrsw_nic/wr_nic.wb
View file @ 1cb9d610
......@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
......@@ -66,6 +63,16 @@ top = peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect";
prefix = "sw_rst";
size = 1;
align = 31;
type = MONOSTABLE;
};
};
reg {
......@@ -145,18 +152,6 @@ top = peripheral {
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
......
modules/wrsw_nic/wrsw_nic.vhd
View file @ 1cb9d610
......@@ -11,8 +11,8 @@ entity wrsw_nic is
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_src_cyc_on_stall : boolean := false
);
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -47,7 +47,7 @@ entity wrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
......@@ -66,7 +66,7 @@ entity wrsw_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic
wb_int_o : out std_logic
);
......@@ -78,7 +78,8 @@ architecture rtl of wrsw_nic is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean);
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -86,7 +87,7 @@ architecture rtl of wrsw_nic is
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
......@@ -111,7 +112,8 @@ begin
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_src_cyc_on_stall => g_src_cyc_on_stall)
g_src_cyc_on_stall => g_src_cyc_on_stall,
g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -158,6 +160,6 @@ begin
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_irq_o <= wb_out.int;
wb_int_o <= wb_out.int;
end rtl;
modules/wrsw_nic/xwrsw_nic.vhd
View file @ 1cb9d610
......@@ -17,8 +17,8 @@ entity xwrsw_nic is
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_src_cyc_on_stall : boolean := false
);
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -37,7 +37,7 @@ entity xwrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
......@@ -59,7 +59,8 @@ architecture rtl of xwrsw_nic is
generic (
g_desc_mode : string;
g_num_descriptors : integer;
g_num_descriptors_log2 : integer);
g_num_descriptors_log2 : integer;
g_port_mask_bits : integer := 32);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -129,9 +130,9 @@ architecture rtl of xwrsw_nic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -162,14 +163,15 @@ architecture rtl of xwrsw_nic is
end component;
component nic_tx_fsm
generic (
g_cyc_on_stall : boolean);
generic(
g_port_mask_bits : integer := 32;
g_cyc_on_stall : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
......@@ -287,7 +289,7 @@ begin -- rtl
wb_out.err <= '0';
wb_out.rty <= '0';
nic_reset_n <= rst_n_i and (not regs_fromwb.reset_wr_o);
nic_reset_n <= rst_n_i and (not regs_fromwb.cr_sw_rst_o);
regs_towb <= regs_towb_tx or regs_towb_rx or regs_towb_main;
......@@ -295,15 +297,15 @@ begin -- rtl
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(6 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_rdata_slave,
wb_adr_i => wb_in.adr(6 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_rdata_slave,
wb_cyc_i => wb_cyc_slave,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_ack_slave,
wb_stall_o => wb_out.stall,
wb_stall_o=> wb_out.stall,
wb_int_o => wb_out.int,
......@@ -399,8 +401,8 @@ begin -- rtl
generic map (
g_desc_mode => "rx",
g_num_descriptors => c_nic_num_rx_descriptors,
g_num_descriptors_log2 => c_nic_num_rx_descriptors_log2)
g_num_descriptors_log2 => c_nic_num_rx_descriptors_log2,
g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
......@@ -465,7 +467,8 @@ begin -- rtl
generic map (
g_desc_mode => "tx",
g_num_descriptors => c_nic_num_tx_descriptors,
g_num_descriptors_log2 => c_nic_num_tx_descriptors_log2)
g_num_descriptors_log2 => c_nic_num_tx_descriptors_log2,
g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
......@@ -494,7 +497,8 @@ begin -- rtl
U_TX_FSM : nic_tx_fsm
generic map(
g_cyc_on_stall => g_src_cyc_on_stall)
g_cyc_on_stall => g_src_cyc_on_stall,
g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
......
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