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White Rabbit core collection
Commit 1d310331 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_pps_gen: re-generated WB slave using new wbgen2

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modules/wr_pps_gen/pps_gen_wb.vhd
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modules/wr_pps_gen/wr_pps_gen.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2012-04-23
-- Last update: 2012-04-24
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -79,10 +79,10 @@ architecture behavioral of wr_pps_gen is
component pps_gen_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -498,10 +498,10 @@ begin -- behavioral
Uwb_slave : pps_gen_wb
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
......
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