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White Rabbit core collection
Commit 1d68a41b authored by Maciej Lipinski's avatar Maciej Lipinski
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[board/spec] updated spec board to allow connection of user-defined aux_diag

parent 170aaec4
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Showing with 103 additions and 9 deletions
board/common/wr_board_pkg.vhd
View file @ 1d68a41b
......@@ -33,6 +33,16 @@ package wr_board_pkg is
application_size : integer
) return integer;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
return std_logic_vector;
function f_de_vectorize_diag (
diag_in : std_logic_vector;
diag_vector_size : integer)
return t_generic_word_array;
component xwrc_board_common is
generic (
g_simulation : integer;
......@@ -211,4 +221,34 @@ package body wr_board_pkg is
end if;
end f_pick_diag_size;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
return std_logic_vector is
variable result : std_logic_vector(diag_vector_size-1 downto 0);
begin
assert (diag_vector_size mod 32 = 0) report
"g_diag_ro/w_vector_width must have value that is a mutiple of 32"
severity error;
for i in 0 to diag_vector_size/32-1 loop
result(i*32-31 downto i*32) := diag_in(i);
end loop;
return result;
end function f_vectorize_diag;
function f_de_vectorize_diag (
diag_in : std_logic_vector;
diag_vector_size : integer)
return t_generic_word_array is
variable result : t_generic_word_array(diag_vector_size/32-1 downto 0);
begin
assert (diag_vector_size mod 32 = 0) report
"g_diag_ro/w_vector_width must have value that is a mutiple of 32"
severity error;
for i in 0 to diag_vector_size/32-1 loop
result(i) := diag_in(i*32-31 downto i*32);
end loop;
return result;
end function f_de_vectorize_diag;
end package body wr_board_pkg;
board/spec/wr_spec_pkg.vhd
View file @ 1d68a41b
......@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_board_pkg.all;
......@@ -14,7 +15,11 @@ package wr_spec_pkg is
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic;
......@@ -81,6 +86,8 @@ package wr_spec_pkg is
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
led_act_o : out std_logic);
end component xwrc_board_spec;
......@@ -90,7 +97,11 @@ package wr_spec_pkg is
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic;
......@@ -193,6 +204,8 @@ package wr_spec_pkg is
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
led_act_o : out std_logic);
end component wrc_board_spec;
......
board/spec/wrc_board_spec.vhd
View file @ 1d68a41b
......@@ -66,7 +66,13 @@ entity wrc_board_spec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram"
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
);
port (
---------------------------------------------------------------------------
......@@ -242,6 +248,8 @@ entity wrc_board_spec is
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
led_act_o : out std_logic);
end entity wrc_board_spec;
......@@ -267,6 +275,14 @@ architecture std_wrapper of wrc_board_spec is
signal wb_eth_master_out : t_wishbone_master_out;
signal wb_eth_master_in : t_wishbone_master_in;
-- Aux diagnostics
constant c_diag_ro_size : integer:= g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer:= g_diag_rw_vector_width/32;
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
begin -- architecture struct
-- Map top-level signals to internal records
......@@ -321,6 +337,10 @@ begin -- architecture struct
wb_eth_master_in.rty <= wb_eth_rty_i;
wb_eth_master_in.stall <= wb_eth_stall_i;
-- auxiliary diagnostics
aux_diag_in <= f_de_vectorize_diag(aux_diag_i,g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
-- Instantiate the records-based module
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
......@@ -328,7 +348,11 @@ begin -- architecture struct
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamer_width => g_streamer_width,
g_dpram_initf => g_dpram_initf)
g_dpram_initf => g_dpram_initf,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
......@@ -395,6 +419,8 @@ begin -- architecture struct
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_link_o => led_link_o,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
led_act_o => led_act_o);
end architecture std_wrapper;
board/spec/xwrc_board_spec.vhd
View file @ 1d68a41b
......@@ -67,7 +67,13 @@ entity xwrc_board_spec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram"
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port (
---------------------------------------------------------------------------
......@@ -196,6 +202,13 @@ entity xwrc_board_spec is
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- WRPC timing interface and status
---------------------------------------------------------------------------
......@@ -374,10 +387,10 @@ begin -- architecture struct
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => FALSE,
g_diag_id => 0,
g_diag_ver => 0,
g_diag_ro_size => c_WR_TRANS_ARR_SIZE_OUT,
g_diag_rw_size => c_WR_TRANS_ARR_SIZE_IN,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamer_width => g_streamer_width,
g_fabric_iface => g_fabric_iface
)
......@@ -454,6 +467,8 @@ begin -- architecture struct
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
link_ok_o => open);
sfp_rate_select_o <= '1';
......
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