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White Rabbit core collection
Commit 22e54748 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_core: cleanup, match signals names with wrpc hdl spec

parent ff2c2fab
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Showing with 164 additions and 165 deletions
modules/wrc_core/wr_core.vhd
View file @ 22e54748
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-07-09
-- Last update: 2013-02-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -61,20 +61,20 @@ entity wr_core is
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
--
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 20480; --in 32-bit words
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
port(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
......@@ -99,8 +99,6 @@ entity wr_core is
rst_n_i : in std_logic;
-----------------------------------------
--Timing system
-----------------------------------------
......@@ -130,8 +128,8 @@ entity wr_core is
-----------------------------------------
--GPIO
-----------------------------------------
led_red_o : out std_logic;
led_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic := '1';
sda_o : out std_logic;
......@@ -155,7 +153,7 @@ entity wr_core is
-----------------------------------------
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
-----------------------------------------
--External WB interface
......@@ -232,13 +230,12 @@ entity wr_core is
tm_clk_aux_locked_o : out std_logic;
-- Timecode output
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
......@@ -467,7 +464,7 @@ begin
pps_led_o => pps_led_o,
pps_valid_o => pps_valid,
tm_utc_o => tm_utc_o,
tm_utc_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o
);
......@@ -534,7 +531,7 @@ begin
out_enable(g_aux_clks downto 1) <= (others => tm_clk_aux_lock_en_i);
dac_dpll_data_o <= dac_dpll_data;
dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel= x"0") else '0';
dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
tm_dac_value_o <= x"00" & dac_dpll_data;
tm_dac_wr_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"1") else '0';
......@@ -602,10 +599,10 @@ begin
wb_i => ep_wb_in,
wb_o => ep_wb_out,
led_link_o => ep_led_link,
led_act_o => led_red_o);
led_act_o => led_act_o);
ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
led_green_o <= ep_led_link;
led_link_o <= ep_led_link;
link_ok_o <= ep_led_link;
tm_link_up_o <= ep_led_link;
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 22e54748
......@@ -350,8 +350,8 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
......@@ -391,7 +391,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
pps_led_o : out std_logic;
......
modules/wrc_core/xwr_core.vhd
View file @ 22e54748
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-07-09
-- Last update: 2013-02-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -47,15 +47,16 @@ entity xwr_core is
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
--
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
......@@ -83,6 +84,7 @@ entity xwr_core is
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
-----------------------------------------
--Timing system
-----------------------------------------
......@@ -112,32 +114,32 @@ entity xwr_core is
-----------------------------------------
--GPIO
-----------------------------------------
led_red_o : out std_logic;
led_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
scl_i : in std_logic := '1';
sda_o : out std_logic;
sda_i : in std_logic;
sda_i : in std_logic := '1';
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_i : in std_logic := '1';
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_sda_i : in std_logic := '1';
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-----------------------------------------
--UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_rxd_i : in std_logic := '0';
uart_txd_o : out std_logic;
-----------------------------------------
-- 1-wire
-----------------------------------------
owr_pwren_o: out std_logic_vector(1 downto 0);
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
-----------------------------------------
--External WB interface
......@@ -171,12 +173,12 @@ entity xwr_core is
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_lock_en_i : in std_logic := '0';
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic;
-- Timecode output
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- 1PPS output
pps_p_o : out std_logic;
......@@ -232,8 +234,8 @@ architecture struct of xwr_core is
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
......@@ -249,7 +251,7 @@ architecture struct of xwr_core is
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_pwren_o: out std_logic_vector(1 downto 0);
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
......@@ -309,7 +311,7 @@ architecture struct of xwr_core is
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
pps_led_o : out std_logic;
......@@ -364,8 +366,8 @@ begin
phy_rst_o => phy_rst_o,
phy_loopen_o => phy_loopen_o,
led_red_o => led_red_o,
led_green_o => led_green_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
scl_o => scl_o,
scl_i => scl_i,
sda_o => sda_o,
......@@ -439,7 +441,7 @@ begin
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
tm_time_valid_o => tm_time_valid_o,
tm_utc_o => tm_utc_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
......
top/spec_1_1/wr_core_demo/spec_top.ucf
View file @ 22e54748
......@@ -629,7 +629,6 @@ TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HI
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
iles
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 22e54748
......@@ -619,9 +619,10 @@ begin
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
g_with_external_clock_input => true,
--
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
......@@ -655,8 +656,8 @@ begin
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
led_red_o => LED_RED,
led_green_o => LED_GREEN,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
......@@ -691,7 +692,7 @@ begin
tm_clk_aux_lock_en_i => '0',
tm_clk_aux_locked_o => open,
tm_time_valid_o => open,
tm_utc_o => open,
tm_tai_o => open,
tm_cycles_o => open,
pps_p_o => pps,
pps_led_o => pps_led,
......
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