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White Rabbit core collection
Commit 22ef4e53 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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wr_streamers: added software controlled reset (not yet in WB interface)

parent d0f0258d
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Showing with 55 additions and 67 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ 22ef4e53
...@@ -139,6 +139,8 @@ package streamers_pkg is ...@@ -139,6 +139,8 @@ package streamers_pkg is
filter_remote : std_logic; filter_remote : std_logic;
-- value in cycles of fixed-latency enforced on data -- value in cycles of fixed-latency enforced on data
fixed_latency : std_logic_vector(27 downto 0); fixed_latency : std_logic_vector(27 downto 0);
-- software controlled reset
sw_reset : std_logic;
end record; end record;
type t_tx_streamer_cfg is record type t_tx_streamer_cfg is record
...@@ -156,6 +158,8 @@ package streamers_pkg is ...@@ -156,6 +158,8 @@ package streamers_pkg is
qtag_vid : std_logic_vector(11 downto 0); qtag_vid : std_logic_vector(11 downto 0);
-- priority used to tag -- priority used to tag
qtag_prio : std_logic_vector(2 downto 0); qtag_prio : std_logic_vector(2 downto 0);
-- software controlled reset
sw_reset : std_logic;
end record; end record;
constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=( constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=(
...@@ -164,7 +168,8 @@ package streamers_pkg is ...@@ -164,7 +168,8 @@ package streamers_pkg is
ethertype => x"dbff", ethertype => x"dbff",
accept_broadcasts => '1', accept_broadcasts => '1',
filter_remote => '0', filter_remote => '0',
fixed_latency => x"0000000"); fixed_latency => x"0000000",
sw_reset => '0');
constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=( constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
mac_local => x"000000000000", mac_local => x"000000000000",
...@@ -172,7 +177,8 @@ package streamers_pkg is ...@@ -172,7 +177,8 @@ package streamers_pkg is
ethertype => x"dbff", ethertype => x"dbff",
qtag_ena => '0', qtag_ena => '0',
qtag_vid => x"000", qtag_vid => x"000",
qtag_prio => "000"); qtag_prio => "000",
sw_reset => '0');
component xtx_streamer component xtx_streamer
generic ( generic (
......
modules/wr_streamers/xrx_streamer.vhd
View file @ 22ef4e53
...@@ -78,6 +78,10 @@ entity xrx_streamer is ...@@ -78,6 +78,10 @@ entity xrx_streamer is
-- in the future, more frequences might be supported.. -- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000; g_clk_ref_rate : integer := 125000000;
g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000000;
g_use_ref_clock_for_data : integer := 0 g_use_ref_clock_for_data : integer := 0
); );
...@@ -189,9 +193,22 @@ architecture rtl of xrx_streamer is ...@@ -189,9 +193,22 @@ architecture rtl of xrx_streamer is
constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles
signal fifo_last_int : std_logic; signal fifo_last_int : std_logic;
signal rst_int_n : std_logic;
begin -- rtl begin -- rtl
p_software_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rst_int_n <= '0';
else
rst_int_n <= not rx_streamer_cfg_i.sw_reset;
end if;
end if;
end process;
U_rx_crc_generator : gc_crc_gen U_rx_crc_generator : gc_crc_gen
generic map ( generic map (
g_polynomial => x"1021", g_polynomial => x"1021",
...@@ -215,7 +232,7 @@ begin -- rtl ...@@ -215,7 +232,7 @@ begin -- rtl
U_Fabric_Sink : xwb_fabric_sink U_Fabric_Sink : xwb_fabric_sink
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
snk_i => snk_i, snk_i => snk_i,
snk_o => snk_o, snk_o => snk_o,
addr_o => fab.addr, addr_o => fab.addr,
...@@ -235,7 +252,7 @@ begin -- rtl ...@@ -235,7 +252,7 @@ begin -- rtl
g_escape_code => x"cafe") g_escape_code => x"cafe")
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
d_i => fab.data, d_i => fab.data,
d_detect_enable_i => detect_escapes, d_detect_enable_i => detect_escapes,
d_valid_i => fab.dvalid, d_valid_i => fab.dvalid,
...@@ -260,7 +277,7 @@ begin -- rtl ...@@ -260,7 +277,7 @@ begin -- rtl
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
pulse_a_i => fsm_in.sof, pulse_a_i => fsm_in.sof,
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i, tm_tai_i => tm_tai_i,
...@@ -279,7 +296,7 @@ begin -- rtl ...@@ -279,7 +296,7 @@ begin -- rtl
g_sim_cycle_counter_range => g_sim_cycle_counter_range, g_sim_cycle_counter_range => g_sim_cycle_counter_range,
g_simulation => g_simulation) g_simulation => g_simulation)
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
...@@ -301,59 +318,11 @@ begin -- rtl ...@@ -301,59 +318,11 @@ begin -- rtl
rx_dreq_i => rx_dreq_i, rx_dreq_i => rx_dreq_i,
rx_streamer_cfg_i => rx_streamer_cfg_i); rx_streamer_cfg_i => rx_streamer_cfg_i);
-- introduce fixed latency, if configured to do so
-- p_fixed_latency_fsm : process(clk_sys_i)
-- begin
-- if rising_edge(clk_sys_i) then
-- if rst_n_i = '0' then
-- delay_state <= DISABLED;
-- rx_latency_stored <= (others => '0');
-- rx_dreq_allow <= '1';
-- delay_cnt <= c_timestamper_delay;
-- else
-- case delay_state is
-- when DISABLED =>
-- if unsigned(rx_streamer_cfg_i.fixed_latency) /= c_fixed_latency_zero then
-- delay_state <= ALLOW;
-- end if;
-- rx_latency_stored <= (others => '0');
-- delay_cnt <= c_timestamper_delay;
-- rx_dreq_allow <= '1';
-- when ALLOW =>
-- if unsigned(rx_streamer_cfg_i.fixed_latency) = c_fixed_latency_zero then
-- delay_state <= DISABLED;
-- elsif(rx_latency_valid = '1') then
-- rx_dreq_allow <= '0';
-- rx_latency_stored <= rx_latency;
-- delay_state <= DELAY;
-- end if;
-- if(timestamped = '1') then
-- if(rx_tag_valid= '1') then
-- delay_cnt <= c_timestamper_delay;
-- else
-- delay_cnt <= delay_cnt + 2;
-- end if;
-- when DELAY =>
-- if unsigned(rx_streamer_cfg_i.fixed_latency) <= delay_cnt + rx_latency_stored then
-- rx_latency_stored <= (others => '0');
-- rx_dreq_allow <= '1';
-- delay_state <= ALLOW;
-- else
-- delay_cnt <= delay_cnt + 2;
-- end if;
-- end case;
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------------------
-- end of fixed latency implementation
-- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
p_fsm : process(clk_sys_i) p_fsm : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_n_i = '0' then if rst_int_n = '0' then
state <= IDLE; state <= IDLE;
count <= (others => '0'); count <= (others => '0');
seq_no <= (others => '1'); seq_no <= (others => '1');
...@@ -696,6 +665,6 @@ begin -- rtl ...@@ -696,6 +665,6 @@ begin -- rtl
rx_lost_frames_p1_o <= frames_lost; rx_lost_frames_p1_o <= frames_lost;
rx_latency_o <= std_logic_vector(rx_latency); rx_latency_o <= std_logic_vector(rx_latency);
rx_latency_valid_o <= rx_latency_valid; rx_latency_valid_o <= rx_latency_valid;
crc_restart <= '1' when (state = FRAME_SEQ_ID or (is_escape = '1' and fsm_in.data(15) = '1')) else not rst_n_i; crc_restart <= '1' when (state = FRAME_SEQ_ID or (is_escape = '1' and fsm_in.data(15) = '1')) else not rst_int_n;
end rtl; end rtl;
modules/wr_streamers/xtx_streamer.vhd
View file @ 22ef4e53
...@@ -213,8 +213,21 @@ architecture rtl of xtx_streamer is ...@@ -213,8 +213,21 @@ architecture rtl of xtx_streamer is
constant c_link_ok_rst_delay : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s constant c_link_ok_rst_delay : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s
constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(g_sim_startup_cnt, 26); constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(g_sim_startup_cnt, 26);
signal rst_int_n : std_logic;
begin -- rtl begin -- rtl
p_software_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rst_int_n <= '0';
else
rst_int_n <= not tx_streamer_cfg_i.sw_reset;
end if;
end if;
end process;
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
-- check sanity of input generics -- check sanity of input generics
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
...@@ -251,7 +264,7 @@ begin -- rtl ...@@ -251,7 +264,7 @@ begin -- rtl
U_Fab_Source : xwb_fabric_source U_Fab_Source : xwb_fabric_source
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
src_i => src_i, src_i => src_i,
src_o => src_o, src_o => src_o,
addr_i => c_WRF_DATA, addr_i => c_WRF_DATA,
...@@ -274,7 +287,7 @@ begin -- rtl ...@@ -274,7 +287,7 @@ begin -- rtl
g_escape_code => x"cafe") g_escape_code => x"cafe")
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
d_i => fsm_out.data, d_i => fsm_out.data,
d_insert_enable_i => fsm_escape_enable, d_insert_enable_i => fsm_escape_enable,
d_escape_i => fsm_escape, d_escape_i => fsm_escape,
...@@ -306,7 +319,7 @@ begin -- rtl ...@@ -306,7 +319,7 @@ begin -- rtl
g_almost_full_threshold => g_tx_buffer_size - 2, g_almost_full_threshold => g_tx_buffer_size - 2,
g_show_ahead => true) g_show_ahead => true)
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
clk_i => clk_sys_i, clk_i => clk_sys_i,
d_i => tx_fifo_d, d_i => tx_fifo_d,
we_i => tx_fifo_we, we_i => tx_fifo_we,
...@@ -337,7 +350,7 @@ begin -- rtl ...@@ -337,7 +350,7 @@ begin -- rtl
g_almost_full_threshold => g_tx_buffer_size - 2, g_almost_full_threshold => g_tx_buffer_size - 2,
g_show_ahead => false) g_show_ahead => false)
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
clk_wr_i => clk_ref_i, clk_wr_i => clk_ref_i,
clk_rd_i => clk_sys_i, clk_rd_i => clk_sys_i,
d_i => tx_fifo_d, d_i => tx_fifo_d,
...@@ -358,7 +371,7 @@ begin -- rtl ...@@ -358,7 +371,7 @@ begin -- rtl
g_width => g_data_width + 1) g_width => g_data_width + 1)
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
fifo_q_i => tx_fifo_q_int, fifo_q_i => tx_fifo_q_int,
fifo_empty_i => tx_fifo_empty_int, fifo_empty_i => tx_fifo_empty_int,
fifo_rd_o => tx_fifo_rd_int, fifo_rd_o => tx_fifo_rd_int,
...@@ -406,7 +419,7 @@ begin -- rtl ...@@ -406,7 +419,7 @@ begin -- rtl
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
pulse_a_i => stamper_pulse_a, pulse_a_i => stamper_pulse_a,
tm_time_valid_i => tm_time_valid_i, tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i, tm_tai_i => tm_tai_i,
...@@ -423,7 +436,7 @@ begin -- rtl ...@@ -423,7 +436,7 @@ begin -- rtl
g_bits => 5, g_bits => 5,
g_output_clock => "dec") g_output_clock => "dec")
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_int_n,
clk_inc_i => clk_data, clk_inc_i => clk_data,
clk_dec_i => clk_sys_i, clk_dec_i => clk_sys_i,
inc_i => buf_frame_count_inc_ref, inc_i => buf_frame_count_inc_ref,
...@@ -434,7 +447,7 @@ begin -- rtl ...@@ -434,7 +447,7 @@ begin -- rtl
p_tx_timeout : process(clk_sys_i) p_tx_timeout : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_n_i = '0' then if rst_int_n = '0' then
timeout_counter <= (others => '0'); timeout_counter <= (others => '0');
tx_timeout_hit <= '0'; tx_timeout_hit <= '0';
else else
...@@ -456,7 +469,7 @@ begin -- rtl ...@@ -456,7 +469,7 @@ begin -- rtl
p_latch_timestamp : process(clk_sys_i) p_latch_timestamp : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_n_i = '0' or state = IDLE then if rst_int_n = '0' or state = IDLE then
tag_valid_latched <= '0'; tag_valid_latched <= '0';
elsif tag_valid = '1' then elsif tag_valid = '1' then
tag_valid_latched <= '1'; tag_valid_latched <= '1';
...@@ -468,7 +481,7 @@ begin -- rtl ...@@ -468,7 +481,7 @@ begin -- rtl
p_fsm : process(clk_sys_i) p_fsm : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_n_i = '0' then if rst_int_n = '0' then
state <= IDLE; state <= IDLE;
fsm_out.sof <= '0'; fsm_out.sof <= '0';
fsm_out.eof <= '0'; fsm_out.eof <= '0';
...@@ -740,7 +753,7 @@ begin -- rtl ...@@ -740,7 +753,7 @@ begin -- rtl
port map ( port map (
clk_i => clk_ref_i, clk_i => clk_ref_i,
rst_n_i => '1', rst_n_i => '1',
data_i => rst_n_i, data_i => rst_int_n,
synced_o => rst_n_ref); synced_o => rst_n_ref);
U_SyncLinkOK_to_RefClk : gc_sync_ffs U_SyncLinkOK_to_RefClk : gc_sync_ffs
......
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