wr endpoint: removed unnecessary code + updated file headers

29f7ca73 · Tomasz Wlostowski · b53a746a · 29f7ca73 · 29f7ca73 · 29f7ca73
Commit 29f7ca73 authored Oct 18, 2011 by Tomasz Wlostowski
11 changed files
--- a/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_private_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Private constants/types/functions package
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : endpoint_private_pkg.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Endpoint private definitions:
+-- - 8B10B codes
+-- - VLAN control registers
+-- - Data types: internal fabric, RMON, RTU
+-- - 18-bit FIFO fabric packing/unpacking functions
+-- - Endpoint subcomponents declarations
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -7,9 +47,6 @@ use work.wr_fabric_pkg.all;

 package endpoint_private_pkg is
  
-  constant c_endpoint_rx_buffer_size      : integer := 4096;
-  constant c_endpoint_rx_buffer_size_log2 : integer := 12;
-
  -- special/control characters
  constant c_k28_5 : std_logic_vector(7 downto 0) := "10111100";  -- bc
  constant c_k23_7 : std_logic_vector(7 downto 0) := "11110111";  -- f7

--- a/modules/wr_endpoint/ep_autonegotiation.vhd
+++ b/modules/wr_endpoint/ep_autonegotiation.vhd
 -------------------------------------------------------------------------------
-- Title      : 1000BaseT/X MAC Endpoint - 1000BaseX autonegotiation 
-- Project    : White Rabbit Switch
+-- Title      : 1000Base-X Autonegotiation 
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
 -- File       : ep_autonegotiation.vhd
-- Author     : Tomasz Wlostowski
+-- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2011-08-22
+-- Last update: 2011-10-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -14,7 +14,7 @@
 -- defined in IEEE802.3.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   
@@ -30,7 +30,7 @@
 --
 -- You should have received a copy of the GNU Lesser General    
 -- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
 --
 -------------------------------------------------------------------------------
 -- Revisions  :
@@ -39,8 +39,6 @@
 -- 2011-02-07  0.5      twlostow  Tested on Spartan6 GTP
 -------------------------------------------------------------------------------

-
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+++ b/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+-------------------------------------------------------------------------------
+-- Title      : RX Clock Alignment FIFO
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_clock_alignment_fifo.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Asynchronous FIFO with internal fabric (t_ep_internal_fabric)
+-- interface used to pass packet data between the RX clock->system clock
+-- domains. 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -9,18 +46,14 @@ entity ep_clock_alignment_fifo is

  generic(
    g_size                 : integer := 64;
-    g_almostfull_threshold : integer := 56;
-    g_early_eof            : boolean := false
-    );
+    g_almostfull_threshold : integer := 56);

  port(
    rst_n_rd_i : in std_logic;
-
    clk_wr_i : in std_logic;
    clk_rd_i : in std_logic;

    dreq_i : in std_logic;
-
    fab_i : in  t_ep_internal_fabric;
    fab_o : out t_ep_internal_fabric;

@@ -28,6 +61,8 @@ entity ep_clock_alignment_fifo is
    empty_o      : out std_logic;
    almostfull_o : out std_logic;

+    -- number of data words which enables the output. Used
+    -- to control the minimum latency
    pass_threshold_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0)
    );
 end ep_clock_alignment_fifo;
@@ -50,9 +85,7 @@ architecture structural of ep_clock_alignment_fifo is
  signal s_dummy : std_logic;
 begin

-  f_pack_fifo_contents (fab_i, fifo_in, fifo_we, g_early_eof);
-
--  fifo_we <= fab_i.dvalid or fab_i.sof or fab_i.eof or fab_i.error;
+  f_pack_fifo_contents (fab_i, fifo_in, fifo_we, false);

 -- Clock adjustment FIFO
  U_FIFO : generic_async_fifo
@@ -118,7 +151,7 @@ begin
  end process;

  -- FIFO output data formatting
-  f_unpack_fifo_contents(fifo_out, valid_int, fab_int, g_early_eof);
+  f_unpack_fifo_contents(fifo_out, valid_int, fab_int, false);

  fab_o   <= fab_int;
  empty_o <= empty_int;

--- a/modules/wr_endpoint/ep_flow_control.vhd
+++ b/modules/wr_endpoint/ep_flow_control.vhd
 -------------------------------------------------------------------------------
-- Title      : 1000BaseT/X MAC Endpoint - flow control unit
-- Project    : White Rabbit Switch
+-- Title      : Ethernet Flow Control Unit
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
 -- File       : ep_flow_control.vhd
-- Author     : Tomasz Wlostowski
+-- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2011-05-27
+-- Last update: 2011-10-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -14,7 +14,7 @@
 -- TX and RX path of the MAC. 
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 - 2011 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_packet_filter.vhd
+++ b/modules/wr_endpoint/ep_packet_filter.vhd
+-------------------------------------------------------------------------------
+-- Title      : Programmable Packet Filter/Inspector
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_packet_filter.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A simple packet inspection CPU, capable of classifying incoming
+-- packets to 8 different packet classes. The microcode format and programming
+-- constaints are described in detail in the Endpoint's manual.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wr_endpoint/ep_rmon_counters.vhd
+++ b/modules/wr_endpoint/ep_rmon_counters.vhd
 -------------------------------------------------------------------------------
-- Title      : 1000BaseT/X MAC Endpoint - Statistic Counters (RMON)
-- Project    : White Rabbit Switch
+-- Title      : Programmable Statistics Counters (RMON)
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
 -- File       : ep_rmon_counters.vhd
-- Author     : Tomasz Wlostowski
+-- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2011-05-27
+-- Last update: 2011-10-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Module implements a configurable counter block for gathering
-- RMON statistics. The block is RAM-based to reduce the FPGA footprint
+-- RMON statistics. The block is RAM-based to reduce the FPGA footprint and hence
+-- has some limitations on the maximum frequency of the incoming triggers.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_rx_buffer.vhd
+++ b/modules/wr_endpoint/ep_rx_buffer.vhd
 -------------------------------------------------------------------------------
-- Title      : WR Endpoint - RX Buffer
-- Project    : White Rabbit 
+-- Title      : RX Packet Buffer
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
 -- File       : ep_rx_buffer.vhd
-- Author     : Tomasz Wlostowski
-- Company    : CERN BE-Co-HT
-- Created    : 2010-04-26
-- Last update: 2011-10-16
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
 -- Platform   : FPGA-generic
-- Standard   : VHDL
+-- Standard   : VHDL'93
 -------------------------------------------------------------------------------
-- Description: A simple synchronous packet buffer of programmable size.
+-- Description: A simple RX packet buffer, optimized for 18-bit Block RAM-based
+-- FIFOs.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
 -------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2010-04-26  0.2      twlostow        Created
-------------------------------------------------------------------------------
-

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+++ b/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+-------------------------------------------------------------------------------
+-- Title      : RX Bypass queue
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : ep_rx_bypass_queue.vhd
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2011-08-10
+-- Last update: 2011-10-18
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: A small, LUT/SRL based FIFO keeping constant latency. Used to
+-- strip off the CRC of the frame.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wr_endpoint/ep_rx_path.vhd
+++ b/modules/wr_endpoint/ep_rx_path.vhd
 -------------------------------------------------------------------------------
-- Title      : 1000base-X MAC/Endpoint 
-- Project    : White Rabbit Switch 
+-- Title      : Gigabit Ethernet reception pipeline
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
-- File       : ep_rx_deframer.vhd
+-- File       : ep_rx_path.vhd
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2009-06-22
-- Last update: 2011-10-14
+-- Last update: 2011-10-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
-- Description: RX deframing module:
-- - checks frame CRC
-- - inserts 802.1q headers when necessary
+-- Description: RX path unit:
+-- - provides elastic buffering between RX and system clock
+-- - checks frame CRC and size
+-- - inserts/removes 802.1q headers when necessary 
 -- - parses packet headers and generates RTU requests
+-- - performs programmable packet inspection and classifying
+-- - distinguishes between HP and non-HP frames
+-- - issues RTU requests
 -- - embeds RX OOB block with timestamp information
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+--
+-- Copyright (c) 2009-2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
 -------------------------------------------------------------------------------
 -- Revisions  :
-- Date        Version  Author  Description
-- 2009-06-22  0.1      twlostow  Created
+-- Date        Version  Author          Description
+-- 2009-06-22  0.1      twlostow        Created
+-- 2011-10-18  0.5      twlostow        WB rev B4 - compatible data path
 ------------------------------------------------------------------------------


@@ -38,7 +61,9 @@ entity ep_rx_path is
  generic (
    g_with_vlans          : boolean := true;
    g_with_dpi_classifier : boolean := true;
-    g_with_rtu            : boolean := true);
+    g_with_rtu            : boolean := true;
+    g_with_rx_buffer      : boolean := true;
+    g_rx_buffer_size      : integer := 1024);
  port (
    clk_sys_i   : in std_logic;
    clk_rx_i    : in std_logic;
@@ -50,11 +75,7 @@ entity ep_rx_path is
    pcs_fifo_almostfull_o : out std_logic;
    pcs_busy_i            : in  std_logic;

-- OOB frame tag value and strobing signal
-    oob_data_i  : in  std_logic_vector(47 downto 0);
-    oob_valid_i : in  std_logic;
-    oob_ack_o   : out std_logic;
-
+-- Wishbone I/O
    src_wb_o : out t_wrf_source_out;
    src_wb_i : in  t_wrf_source_in;

@@ -68,7 +89,6 @@ entity ep_rx_path is
    regs_i : in    t_ep_out_registers;
 --    regs_o : out   t_ep_in_registers;

-
 -------------------------------------------------------------------------------
 -- RTU interface
 -------------------------------------------------------------------------------
@@ -77,7 +97,6 @@ entity ep_rx_path is
    rtu_full_i     : in  std_logic;
    rtu_rq_valid_o : out std_logic
    );
-
 end ep_rx_path;

 architecture behavioral of ep_rx_path is
@@ -103,8 +122,7 @@ architecture behavioral of ep_rx_path is
  component ep_clock_alignment_fifo
    generic (
      g_size                 : integer;
-      g_almostfull_threshold : integer;
-      g_early_eof            : boolean);
+      g_almostfull_threshold : integer);
    port (
      rst_n_rd_i       : in  std_logic;
      clk_wr_i         : in  std_logic;
@@ -196,6 +214,21 @@ architecture behavioral of ep_rx_path is
      ematch_is_pause_i : in  std_logic;
      rmon_o            : out t_rmon_triggers);
  end component;
+  
+  component ep_rx_buffer
+    generic (
+      g_size : integer);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      snk_fab_i  : in  t_ep_internal_fabric;
+      snk_dreq_o : out std_logic;
+      src_fab_o  : out t_ep_internal_fabric;
+      src_dreq_i : in  std_logic;
+      level_o    : out std_logic_vector(7 downto 0);
+      regs_i     : in  t_ep_out_registers;
+      rmon_o     : out    t_rmon_triggers);
+  end component;

  type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);

@@ -228,8 +261,8 @@ architecture behavioral of ep_rx_path is

  type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;

-  signal fab_pipe  : t_fab_pipe(0 to 7);
-  signal dreq_pipe : std_logic_vector(7 downto 0);
+  signal fab_pipe  : t_fab_pipe(0 to 8);
+  signal dreq_pipe : std_logic_vector(8 downto 0);

  signal ematch_done         : std_logic;
  signal ematch_is_hp        : std_logic;
@@ -293,8 +326,7 @@ begin  -- behavioral
  U_Rx_Clock_Align_FIFO : ep_clock_alignment_fifo
    generic map (
      g_size                 => 64,
-      g_almostfull_threshold => 52,
-      g_early_eof            => false)
+      g_almostfull_threshold => 52)
    port map (
      rst_n_rd_i       => rst_n_sys_i,
      clk_wr_i         => clk_rx_i,
@@ -305,10 +337,8 @@ begin  -- behavioral
      full_o           => open,
      empty_o          => open,
      almostfull_o     => pcs_fifo_almostfull_o,
-      pass_threshold_i => std_logic_vector(to_unsigned(12, 6)));
-
-
-
+      pass_threshold_i => std_logic_vector(to_unsigned(12, 6)));  -- fixme: add
+                                                                  -- register

  U_Insert_OOB : ep_rx_oob_insert
    port map (
@@ -320,8 +350,6 @@ begin  -- behavioral
      src_fab_o  => fab_pipe(4),
      regs_i     => regs_i);

-  
-
  U_crc_size_checker : ep_rx_crc_size_check
    port map (
      clk_sys_i  => clk_sys_i,
@@ -349,6 +377,11 @@ begin  -- behavioral
        regs_i     => regs_i);
  end generate gen_with_vlan_unit;

+  gen_without_vlan_unit:  if(not g_with_vlans) generate
+    fab_pipe(6) <= fab_pipe(5);
+    dreq_pipe(5) <= dreq_pipe(6);
+  end generate gen_without_vlan_unit;
+
  U_Gen_Status : ep_rx_status_reg_insert
    port map (
      clk_sys_i         => clk_sys_i,
@@ -365,13 +398,33 @@ begin  -- behavioral
      ematch_is_pause_i => ematch_is_pause,
      rmon_o            => open);

-
+  gen_with_rx_buffer: if g_with_rx_buffer generate
+    U_Rx_Buffer: ep_rx_buffer
+      generic map (
+        g_size => g_rx_buffer_size)
+      port map (
+        clk_sys_i  => clk_sys_i,
+        rst_n_i    => rst_n_sys_i,
+        snk_fab_i  => fab_pipe(7),
+        snk_dreq_o => dreq_pipe(7),
+        src_fab_o  => fab_pipe(8),
+        src_dreq_i => dreq_pipe(8),
+        level_o    => fc_buffer_occupation_o,
+        regs_i     => regs_i,
+        rmon_o     => open);
+  end generate gen_with_rx_buffer;
+
+  gen_without_rx_buffer: if (not g_with_rx_buffer) generate
+    fab_pipe(8) <= fab_pipe(7);
+    dreq_pipe(7) <= dreq_pipe(8);
+  end generate gen_without_rx_buffer;
+  
  U_RX_Wishbone_Master : ep_rx_wb_master
    port map (
      clk_sys_i  => clk_sys_i,
      rst_n_i    => rst_n_sys_i,
-      snk_fab_i  => fab_pipe(7),
-      snk_dreq_o => dreq_pipe(7),
+      snk_fab_i  => fab_pipe(8),
+      snk_dreq_o => dreq_pipe(8),
      src_wb_i   => src_wb_i,
      src_wb_o   => src_wb_o
      );

--- a/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
 -------------------------------------------------------------------------------
-- Title      : 1000BaseT/X MAC Endpoint - receive path PCS for 1000BaseX
-- Project    : White Rabbit Switch
+-- Title      : 16-bit transmit path for 1000Base-X PCS
+-- Project    : White Rabbit MAC/Endpoint
 -------------------------------------------------------------------------------
 -- File       : ep_tx_pcs_16bit.vhd
-- Author     : Tomasz Wlostowski
+-- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT section
 -- Created    : 2009-06-16
 -- Last update: 2011-10-05
@@ -21,7 +21,7 @@
 -- exchange between these clock domains is done using an async FIFO.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011 Tomasz Wlostowski / CERN
+-- Copyright (c) 2011 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   
@@ -45,12 +45,10 @@
 -- 2011-10-15  0.2      twlostow 16-bit version for Virtex 6 GTX
 -------------------------------------------------------------------------------

-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

-
 library work;
 use work.gencores_pkg.all;
 use work.genram_pkg.all;

--- a/modules/wr_endpoint/pcs_regs.wb
+++ b/modules/wr_endpoint/pcs_regs.wb
 -- -*- Mode: LUA; tab-width: 2 -*-

+-------------------------------------------------------------------------------
+-- Title      : 802.3 PCS Register Block (slave)
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : pcs_regs.wb
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
+-------------------------------------------------------------------------------
+-- Description: Standard PCS register block + WR-specific PCS fields: 
+-- RX bitslide and calibration pattern control.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
 peripheral {
 	 name = "WR Endpoint 1000base-X TBI PCS register block";
 	 hdl_entity = "ep_pcs_tbi_mdio_wb";