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White Rabbit core collection
Commit 2a8606f0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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SPLL oversampling rebase wip

parent cf848e66
Pipeline #4402 failed with stage
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    Showing with 1114 additions and 1057 deletions
    modules/timing/Manifest.py
    View file @ 2a8606f0
    ......@@ -6,4 +6,4 @@ files = ["dmtd_phase_meas.vhd",
    "pulse_gen.vhd",
    "pulse_stamper.vhd",
    "pulse_stamper_sync.vhd",
    ]
    "dmtd_sampler.vhd" ]
    modules/timing/dmtd_sampler.vhd
    View file @ 2a8606f0
    ......@@ -49,7 +49,13 @@ entity dmtd_sampler is
    g_divide_input_by_2 : boolean := false;
    -- reversed mode: samples clk_dmtd with clk_in.
    g_reverse : boolean := false
    g_reverse : boolean := false;
    g_oversample : boolean := false;
    g_oversample_factor : integer := 1;
    g_is_ref : boolean := false
    );
    port (
    -- input clock
    ......@@ -57,6 +63,11 @@ entity dmtd_sampler is
    -- DMTD sampling clock
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    sync_p1_i : in std_logic;
    --pps_ref_p1_i : in std_logic;
    clk_sampled_o : out std_logic
    );
    ......@@ -76,10 +87,66 @@ architecture rtl of dmtd_sampler is
    attribute keep of clk_i_d2 : signal is "true";
    attribute keep of clk_i_d3 : signal is "true";
    signal div_sreg : std_logic_vector(g_oversample_factor-1 downto 0) :=
    std_logic_vector(to_unsigned(1, g_oversample_factor));
    signal sync_p1_over_p : std_logic;
    begin -- rtl
    gen_oversampled : if(g_oversample) generate
    gen_input_div2 : if(g_divide_input_by_2 = true) generate
    p_divide_input_clock : process(clk_in_i)
    begin
    if rising_edge(clk_in_i) then
    clk_in <= not clk_in;
    end if;
    end process;
    end generate gen_input_div2;
    gen_input_straight : if(g_divide_input_by_2 = false) generate
    clk_in <= clk_in_i;
    end generate gen_input_straight;
    gc_sync_ffs_1: entity work.gc_sync_ffs
    port map (
    clk_i => clk_dmtd_over_i,
    rst_n_i => '1',
    data_i => sync_p1_i,
    synced_o => open,
    npulse_o => open,
    ppulse_o => sync_p1_over_p);
    process(clk_dmtd_over_i)
    begin
    if rising_edge(clk_dmtd_over_i) then
    if (sync_p1_over_p = '1') then
    div_sreg(0) <= '1';
    div_sreg(g_oversample_factor-1 downto 1) <= (others => '0');
    else
    div_sreg <= div_sreg(0) & div_sreg(div_sreg'length-1 downto 1);
    end if;
    clk_i_d0 <= clk_in;
    if div_sreg(0) = '1' then
    clk_i_d1 <= clk_i_d0;
    end if;
    end if;
    end process;
    p_the_dmtd_itself : process(clk_dmtd_i)
    begin
    if rising_edge(clk_dmtd_i) then
    clk_i_d2 <= clk_i_d1;
    clk_i_d3 <= clk_i_d2;
    end if;
    end process;
    end generate gen_oversampled;
    gen_straight : if(g_reverse = false) generate
    gen_straight : if(g_reverse = false anD g_oversample = false ) generate
    gen_input_div2 : if(g_divide_input_by_2 = true) generate
    p_divide_input_clock : process(clk_in_i)
    ......@@ -106,7 +173,7 @@ begin -- rtl
    end generate gen_straight;
    gen_reverse : if(g_reverse = true) generate
    gen_reverse : if(g_reverse = true and g_oversample = false) generate
    assert (not g_divide_input_by_2) report "dmtd_with_deglitcher: g_reverse implies g_divide_input_by_2 == false" severity failure;
    ......
    modules/timing/dmtd_with_deglitcher.vhd
    View file @ 2a8606f0
    ......@@ -63,6 +63,9 @@ entity dmtd_with_deglitcher is
    -- (at the cost of detector bandwidth)
    g_divide_input_by_2 : boolean := false;
    g_oversample : boolean := false;
    g_oversample_factor : integer := 1;
    -- reversed mode: samples clk_dmtd with clk_in.
    g_reverse : boolean := false;
    ......@@ -78,6 +81,7 @@ entity dmtd_with_deglitcher is
    -- DMTD sampling clock
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    -- system clock
    clk_sys_i : in std_logic;
    ......@@ -131,15 +135,6 @@ end dmtd_with_deglitcher;
    architecture rtl of dmtd_with_deglitcher is
    component dmtd_sampler is
    generic (
    g_divide_input_by_2 : boolean;
    g_reverse : boolean);
    port (
    clk_in_i : in std_logic;
    clk_dmtd_i : in std_logic;
    clk_sampled_o : out std_logic);
    end component dmtd_sampler;
    type t_state is (WAIT_STABLE_0, WAIT_EDGE, GOT_EDGE);
    ......@@ -192,12 +187,16 @@ begin -- rtl
    gen_builtin : if(g_use_sampled_clock = false )generate
    U_Sampler: dmtd_sampler
    U_Sampler: entity work.dmtd_sampler
    generic map (
    g_divide_input_by_2 => g_divide_input_by_2,
    g_reverse => g_reverse)
    g_reverse => g_reverse,
    g_oversample_factor => g_oversample_factor,
    g_oversample => g_oversample)
    port map (
    clk_in_i => clk_in_i,
    sync_p1_i => '0',
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_sampled_o => clk_sampled);
    ......
    modules/wr_softpll_ng/softpll_pkg.vhd
    View file @ 2a8606f0
    ......@@ -7,11 +7,18 @@ package softpll_pkg is
    constant c_softpll_max_aux_clocks : integer := 8;
    type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
    type t_softpll_channel_config is record
    oversample : boolean;
    divider : integer;
    end record;
    type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
    constant c_softpll_default_channel_config : t_softpll_channel_config :=
    ( oversample => false,
    divider => 1 );
    constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
    type t_softpll_channels_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_channel_config;
    constant c_softpll_default_channels_config : t_softpll_channels_config_array := (others => c_softpll_default_channel_config);
    -- External 10 MHz input divider parameters.
    constant c_softpll_ext_div_ref : integer := 8;
    ......
    modules/wr_softpll_ng/spll_wb_slave.vhd
    View file @ 2a8606f0
    This diff is collapsed.
    modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
    View file @ 2a8606f0
    This diff is collapsed.
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ 2a8606f0
    ......@@ -86,6 +86,8 @@ entity wr_softpll_ng is
    g_use_sampled_ref_clocks : boolean := false;
    g_aux_config : t_softpll_channels_config_array := c_softpll_default_channels_config;
    g_interface_mode : t_wishbone_interface_mode := PIPELINED;
    g_address_granularity : t_wishbone_address_granularity := WORD
    );
    ......@@ -111,6 +113,7 @@ entity wr_softpll_ng is
    -- DMTD Offset clock
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic;
    -- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
    -- g_num_exts > 0
    ......@@ -128,12 +131,12 @@ entity wr_softpll_ng is
    pps_ext_a_i : in std_logic;
    -- DMTD oscillator drive
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    -- When HI, load the data from dac_dmtd_data_o to the DAC.
    dac_dmtd_load_o : out std_logic;
    -- Output channel DAC value
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_out_data_o : out std_logic_vector(15 downto 0);
    -- Output channel select (0 = Output channel 0, 1 == OC 1, etc...)
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    ......@@ -173,33 +176,7 @@ architecture rtl of wr_softpll_ng is
    constant c_DBG_FIFO_COALESCE : integer := 100;
    constant c_BB_ERROR_BITS : integer := 16;
    component dmtd_with_deglitcher is
    generic (
    g_counter_bits : natural;
    g_chipscope : boolean := false;
    g_divide_input_by_2 : boolean;
    g_reverse : boolean;
    g_use_sampled_clock : boolean);
    port (
    rst_n_dmtdclk_i : in std_logic;
    rst_n_sysclk_i : in std_logic;
    clk_in_i : in std_logic;
    clk_dmtd_i : in std_logic;
    clk_sys_i : in std_logic;
    clk_sampled_a_i : in std_logic := '0';
    resync_p_a_i : in std_logic := '0';
    resync_p_o : out std_logic;
    resync_start_p_i : in std_logic := '0';
    resync_done_o : out std_logic;
    shift_en_i : in std_logic := '0';
    shift_dir_i : in std_logic := '0';
    clk_dmtd_en_i : in std_logic := '1';
    deglitch_threshold_i : in std_logic_vector(15 downto 0);
    dbg_dmtdout_o : out std_logic;
    tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
    tag_stb_p1_o : out std_logic;
    dbg_clk_d3_o : out std_logic);
    end component dmtd_with_deglitcher;
    component spll_wb_slave
    generic (
    ......@@ -403,7 +380,7 @@ begin -- rtl
    gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
    DMTD_REF : dmtd_with_deglitcher
    DMTD_REF : entity work.dmtd_with_deglitcher
    generic map (
    g_counter_bits => g_tag_bits,
    g_divide_input_by_2 => g_divide_input_by_2,
    ......@@ -437,18 +414,21 @@ begin -- rtl
    gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
    DMTD_FB : dmtd_with_deglitcher
    DMTD_FB : entity work.dmtd_with_deglitcher
    generic map (
    g_counter_bits => g_tag_bits,
    g_divide_input_by_2 => g_divide_input_by_2,
    g_reverse => g_reverse_dmtds,
    g_use_sampled_clock => false)
    g_use_sampled_clock => false,
    g_oversample => g_aux_config(i).oversample,
    g_oversample_factor => g_aux_config(i).divider)
    port map (
    rst_n_dmtdclk_i => rst_dmtd_n_i,
    rst_n_sysclk_i => rst_n_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_dmtd_en_i => '1',
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_sys_i => clk_sys_i,
    clk_in_i => clk_fb_i(i),
    ......@@ -465,7 +445,7 @@ begin -- rtl
    deglitch_threshold_i => deglitch_thr_slv,
    dbg_dmtdout_o => open,
    dbg_clk_d3_o => open); --debug_o(4));
    dbg_clk_d3_o => debug_o(i)); --debug_o(4));
    end generate gen_feedback_dmtds;
    ......@@ -475,7 +455,7 @@ begin -- rtl
    gen_ext_dmtds: for I in 0 to g_num_exts-1 generate
    U_DMTD_EXT_internal : dmtd_with_deglitcher
    U_DMTD_EXT_internal : entity work.dmtd_with_deglitcher
    generic map (
    g_counter_bits => g_tag_bits,
    g_divide_input_by_2 => g_divide_input_by_2,
    ......
    modules/wr_softpll_ng/xwr_softpll_ng.vhd
    View file @ 2a8606f0
    ......@@ -79,6 +79,8 @@ entity xwr_softpll_ng is
    g_use_sampled_ref_clocks : boolean := false;
    g_aux_config : t_softpll_channels_config_array := c_softpll_default_channels_config;
    g_interface_mode : t_wishbone_interface_mode := PIPELINED;
    g_address_granularity : t_wishbone_address_granularity := BYTE
    );
    ......@@ -100,7 +102,7 @@ entity xwr_softpll_ng is
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    -- DMTD Offset clock
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    -- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
    -- g_num_exts > 0
    clk_ext_i : in std_logic;
    ......@@ -118,11 +120,11 @@ entity xwr_softpll_ng is
    pps_ext_a_i : in std_logic;
    -- DMTD oscillator drive
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    dac_dmtd_load_o : out std_logic;
    -- Output channel DAC value
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_out_data_o : out std_logic_vector(15 downto 0);
    -- Output channel select (0 = channel 0, etc. )
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    ......@@ -142,63 +144,10 @@ entity xwr_softpll_ng is
    end xwr_softpll_ng;
    architecture wrapper of xwr_softpll_ng is
    component wr_softpll_ng
    generic (
    g_tag_bits : integer;
    g_dac_bits : integer;
    g_num_ref_inputs : integer;
    g_num_outputs : integer;
    g_num_exts : integer;
    g_with_debug_fifo : boolean;
    g_reverse_dmtds : boolean;
    g_divide_input_by_2 : boolean;
    g_ref_clock_rate : integer;
    g_ext_clock_rate : integer;
    g_use_sampled_ref_clocks : boolean;
    g_interface_mode : t_wishbone_interface_mode;
    g_address_granularity : t_wishbone_address_granularity);
    port (
    clk_sys_i : in std_logic;
    rst_sys_n_i : in std_logic;
    rst_ref_n_i : in std_logic;
    rst_ext_n_i : in std_logic;
    rst_dmtd_n_i : in std_logic;
    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    clk_dmtd_i : in std_logic;
    clk_ext_i : in std_logic;
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic;
    clk_ext_stopped_i : in std_logic;
    clk_ext_rst_o : out std_logic;
    pps_csync_p1_i : in std_logic;
    pps_ext_a_i : in std_logic;
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_load_o : out std_logic;
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
    out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
    wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
    wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_cyc_i : in std_logic;
    wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
    wb_stb_i : in std_logic;
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_stall_o : out std_logic;
    irq_o : out std_logic;
    debug_o : out std_logic_vector(5 downto 0);
    dbg_fifo_irq_o : out std_logic);
    end component;
    begin -- behavioral
    U_Wrapped_Softpll : wr_softpll_ng
    U_Wrapped_Softpll : entity work.wr_softpll_ng
    generic map (
    g_tag_bits => g_tag_bits,
    g_dac_bits => g_dac_bits,
    ......@@ -211,6 +160,7 @@ begin -- behavioral
    g_reverse_dmtds => g_reverse_dmtds,
    g_divide_input_by_2 => g_divide_input_by_2,
    g_use_sampled_ref_clocks => g_use_sampled_ref_clocks,
    g_aux_config => g_aux_config,
    g_ref_clock_rate => g_ref_clock_rate,
    g_ext_clock_rate => g_ext_clock_rate
    )
    ......@@ -224,6 +174,7 @@ begin -- behavioral
    clk_ref_sampled_i => clk_ref_sampled_i,
    clk_fb_i => clk_fb_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_ext_i => clk_ext_i,
    clk_ext_mul_i => clk_ext_mul_i,
    clk_ext_mul_locked_i => clk_ext_mul_locked_i,
    ......
    modules/wrc_core/wr_core.vhd
    View file @ 2a8606f0
    ......@@ -105,7 +105,9 @@ entity wr_core is
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    g_dac_bits : integer := 16;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config
    );
    port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -116,6 +118,7 @@ entity wr_core is
    -- DDMTD offset clock (125.x MHz)
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    -- Timing reference (125 MHz)
    clk_ref_i : in std_logic;
    ......@@ -326,7 +329,9 @@ entity wr_core is
    -- DIAG to/from external modules
    -------------------------------------
    aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
    spll_debug_o : out std_logic_vector(5 downto 0)
    );
    end wr_core;
    ......@@ -607,7 +612,7 @@ begin
    -----------------------------------------------------------------------------
    -- Software PLL
    -----------------------------------------------------------------------------
    U_SOFTPLL : xwr_softpll_ng
    U_SOFTPLL : entity work.xwr_softpll_ng
    generic map(
    g_reverse_dmtds => false,
    g_divide_input_by_2 => not g_pcs_16bit,
    ......@@ -621,7 +626,8 @@ begin
    g_num_exts => f_num_ext_clks,
    g_ref_clock_rate => f_refclk_rate(g_pcs_16bit),
    g_use_sampled_ref_clocks => g_softpll_use_sampled_ref_clocks,
    g_ext_clock_rate => 10000000)
    g_ext_clock_rate => 10000000,
    g_aux_config => g_softpll_aux_channel_config)
    port map(
    clk_sys_i => clk_sys_i,
    rst_sys_n_i => rst_net_n,
    ......@@ -636,6 +642,7 @@ begin
    clk_fb_i => clk_fb,
    -- DMTD Offset clock
    clk_dmtd_i => clk_dmtd_i,
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_ext_i => clk_ext_i,
    clk_ext_mul_i(0) => clk_ext_mul_i,
    ......@@ -665,7 +672,7 @@ begin
    int_o => softpll_irq,
    debug_o => open);
    debug_o => spll_debug_o);
    clk_fb(0) <= clk_ref_i;
    clk_fb(g_aux_clks downto 1) <= clk_aux_i;
    ......
    modules/wrc_core/xwr_core.vhd
    View file @ 2a8606f0
    ......@@ -105,7 +105,8 @@ entity xwr_core is
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    g_dac_bits : integer := 16;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config);
    port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -115,7 +116,8 @@ entity xwr_core is
    clk_sys_i : in std_logic;
    -- DDMTD offset clock (125.x MHz)
    clk_dmtd_i : in std_logic;
    clk_dmtd_i : in std_logic := '0';
    clk_dmtd_over_i : in std_logic ;
    -- Timing reference (125 MHz)
    clk_ref_i : in std_logic;
    ......@@ -157,7 +159,7 @@ entity xwr_core is
    phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
    phy_rx_rbclk_i : in std_logic;
    phy_rx_rbclk_sampled_i : in std_logic;
    phy_rx_rbclk_sampled_i : in std_logic := '0';
    phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
    phy_rx_enc_err_i : in std_logic;
    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
    ......@@ -279,14 +281,17 @@ entity xwr_core is
    aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
    link_ok_o : out std_logic
    link_ok_o : out std_logic;
    spll_debug_o : out std_logic_vector(5 downto 0)
    );
    end xwr_core;
    architecture struct of xwr_core is
    begin
    WRPC : wr_core
    WRPC : entity work.wr_core
    generic map(
    g_simulation => g_simulation,
    g_verbose => g_verbose,
    ......@@ -318,11 +323,13 @@ begin
    g_diag_ro_size => g_diag_ro_size,
    g_diag_rw_size => g_diag_rw_size,
    g_dac_bits => g_dac_bits,
    g_use_platform_specific_dpram => g_use_platform_specific_dpram
    g_use_platform_specific_dpram => g_use_platform_specific_dpram,
    g_softpll_aux_channel_config => g_softpll_aux_channel_config
    )
    port map(
    clk_sys_i => clk_sys_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_ref_i => clk_ref_i,
    clk_aux_i => clk_aux_i,
    clk_ext_i => clk_ext_i,
    ......@@ -471,7 +478,8 @@ begin
    link_ok_o => link_ok_o,
    aux_diag_i => aux_diag_i,
    aux_diag_o => aux_diag_o
    aux_diag_o => aux_diag_o,
    spll_debug_o => spll_debug_o
    );
    timestamps_o.port_id(5) <= '0';
    ......
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