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W
White Rabbit core collection
Commit 2ce72bf5 authored by Pascal Bos's avatar Pascal Bos
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Initial commit 


changed pci_rst_n to perst_n, linked to wrc.bin

linked to wrc.bin

linked to wrc.bin

corrected .bram file

corrected .bram file

corrected .bram file

moved axi related files to general-cores (branch: pascal-axi)



Fixed some bugs


updated general cores with right manifest


Updated tcl, added wrapper
parent 54245d3c
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Showing with 448 additions and 179 deletions
.gitmodules
View file @ 2ce72bf5
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
branch = pascal_axi
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = https://ohwr.org/project/etherbone-core.git
......
board/spec7/wr_spec7_pkg.vhd
View file @ 2ce72bf5
......@@ -4,13 +4,13 @@
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_spec7_pkg.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>, Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Last update: 2020-02-12
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-- Copyright (c) 2020 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -110,6 +110,8 @@ package wr_spec7_pkg is
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -152,166 +154,51 @@ package wr_spec7_pkg is
link_ok_o : out std_logic);
end component xwrc_board_spec7;
-- component wrc_board_spec7 is
-- generic (
-- g_simulation : integer := 0;
-- g_with_external_clock_input : integer := 1;
-- g_aux_clks : integer := 0;
-- g_fabric_iface : string := "PLAINFBRC";
-- g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
-- g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
-- g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- g_dpram_initf : string := "default_xilinx";
-- g_diag_id : integer := 0;
-- g_diag_ver : integer := 0;
-- g_diag_ro_vector_width : integer := 0;
-- g_diag_rw_vector_width : integer := 0);
-- port (
-- areset_n_i : in std_logic;
-- areset_edge_n_i : in std_logic := '1';
-- clk_125m_dmtd_n_i : in std_logic;
-- clk_125m_dmtd_p_i : in std_logic;
-- clk_125m_gtx_n_i : in std_logic;
-- clk_125m_gtx_p_i : in std_logic;
-- clk_10m_ext_i : in std_logic := '0';
-- pps_ext_i : in std_logic := '0';
-- clk_sys_62m5_o : out std_logic;
-- clk_ref_62m5_o : out std_logic;
-- rst_sys_62m5_n_o : out std_logic;
-- rst_ref_62m5_n_o : out std_logic;
-- dac_refclk_cs_n_o : out std_logic;
-- dac_refclk_sclk_o : out std_logic;
-- dac_refclk_din_o : out std_logic;
-- dac_dmtd_cs_n_o : out std_logic;
-- dac_dmtd_sclk_o : out std_logic;
-- dac_dmtd_din_o : out std_logic;
-- sfp_txp_o : out std_logic;
-- sfp_txn_o : out std_logic;
-- sfp_rxp_i : in std_logic;
-- sfp_rxn_i : in std_logic;
-- sfp_det_i : in std_logic := '1';
-- sfp_sda_i : in std_logic;
-- sfp_sda_o : out std_logic;
-- sfp_scl_i : in std_logic;
-- sfp_scl_o : out std_logic;
-- sfp_rate_select_o : out std_logic;
-- sfp_tx_fault_i : in std_logic := '0';
-- sfp_tx_disable_o : out std_logic;
-- sfp_los_i : in std_logic := '0';
-- eeprom_sda_i : in std_logic;
-- eeprom_sda_o : out std_logic;
-- eeprom_scl_i : in std_logic;
-- eeprom_scl_o : out std_logic;
-- onewire_i : in std_logic;
-- onewire_oen_o : out std_logic;
-- uart_rxd_i : in std_logic;
-- uart_txd_o : out std_logic;
-- flash_sclk_o : out std_logic;
-- flash_ncs_o : out std_logic;
-- flash_mosi_o : out std_logic;
-- flash_miso_i : in std_logic;
-- wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
-- wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
-- wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
-- wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
-- wb_we_i : in std_logic := '0';
-- wb_cyc_i : in std_logic := '0';
-- wb_stb_i : in std_logic := '0';
-- wb_ack_o : out std_logic;
-- wb_int_o : out std_logic;
-- wb_err_o : out std_logic;
-- wb_rty_o : out std_logic;
-- wb_stall_o : out std_logic;
-- aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
-- aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
-- aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
-- aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
-- aux_master_we_o : out std_logic;
-- aux_master_cyc_o : out std_logic;
-- aux_master_stb_o : out std_logic;
-- aux_master_ack_i : in std_logic := '0';
-- aux_master_int_i : in std_logic := '0';
-- aux_master_err_i : in std_logic := '0';
-- aux_master_rty_i : in std_logic := '0';
-- aux_master_stall_i : in std_logic := '0';
-- wrf_src_adr_o : out std_logic_vector(1 downto 0);
-- wrf_src_dat_o : out std_logic_vector(15 downto 0);
-- wrf_src_cyc_o : out std_logic;
-- wrf_src_stb_o : out std_logic;
-- wrf_src_we_o : out std_logic;
-- wrf_src_sel_o : out std_logic_vector(1 downto 0);
-- wrf_src_ack_i : in std_logic;
-- wrf_src_stall_i : in std_logic;
-- wrf_src_err_i : in std_logic;
-- wrf_src_rty_i : in std_logic;
-- wrf_snk_adr_i : in std_logic_vector(1 downto 0);
-- wrf_snk_dat_i : in std_logic_vector(15 downto 0);
-- wrf_snk_cyc_i : in std_logic;
-- wrf_snk_stb_i : in std_logic;
-- wrf_snk_we_i : in std_logic;
-- wrf_snk_sel_i : in std_logic_vector(1 downto 0);
-- wrf_snk_ack_o : out std_logic;
-- wrf_snk_stall_o : out std_logic;
-- wrf_snk_err_o : out std_logic;
-- wrf_snk_rty_o : out std_logic;
-- wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
-- wrs_tx_valid_i : in std_logic := '0';
-- wrs_tx_dreq_o : out std_logic;
-- wrs_tx_last_i : in std_logic := '1';
-- wrs_tx_flush_i : in std_logic := '0';
-- wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
-- wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
-- wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
-- wrs_rx_first_o : out std_logic;
-- wrs_rx_last_o : out std_logic;
-- wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
-- wrs_rx_valid_o : out std_logic;
-- wrs_rx_dreq_i : in std_logic := '0';
-- wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
-- wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
-- wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
-- wrs_rx_cfg_acc_b_i : in std_logic := '1';
-- wrs_rx_cfg_flt_r_i : in std_logic := '0';
-- wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
-- wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
-- wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
-- wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
-- wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
-- wb_eth_we_o : out std_logic;
-- wb_eth_cyc_o : out std_logic;
-- wb_eth_stb_o : out std_logic;
-- wb_eth_ack_i : in std_logic := '0';
-- wb_eth_int_i : in std_logic := '0';
-- wb_eth_err_i : in std_logic := '0';
-- wb_eth_rty_i : in std_logic := '0';
-- wb_eth_stall_i : in std_logic := '0';
-- aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
-- aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
-- tm_dac_value_o : out std_logic_vector(23 downto 0);
-- tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- tstamps_stb_o : out std_logic;
-- tstamps_tsval_o : out std_logic_vector(31 downto 0);
-- tstamps_port_id_o : out std_logic_vector(5 downto 0);
-- tstamps_frame_id_o : out std_logic_vector(15 downto 0);
-- tstamps_incorrect_o : out std_logic;
-- tstamps_ack_i : in std_logic := '1';
-- fc_tx_pause_req_i : in std_logic := '0';
-- fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
-- fc_tx_pause_ready_o : out std_logic;
-- tm_link_up_o : out std_logic;
-- tm_time_valid_o : out std_logic;
-- tm_tai_o : out std_logic_vector(39 downto 0);
-- tm_cycles_o : out std_logic_vector(27 downto 0);
-- led_act_o : out std_logic;
-- led_link_o : out std_logic;
-- btn1_i : in std_logic := '1';
-- btn2_i : in std_logic := '1';
-- pps_p_o : out std_logic;
-- pps_led_o : out std_logic;
-- link_ok_o : out std_logic);
-- end component wrc_board_spec7;
component Pcie_wrapper is
port (
aclk1_0 : in STD_LOGIC;
pcie_clk : in STD_LOGIC;
pcie_rst_n : in STD_LOGIC;
user_lnk_up_0 : out STD_LOGIC;
usr_irq_ack_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
usr_irq_req_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awvalid : out STD_LOGIC;
M00_AXI_0_awready : in STD_LOGIC;
M00_AXI_0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_wlast : out STD_LOGIC;
M00_AXI_0_wvalid : out STD_LOGIC;
M00_AXI_0_wready : in STD_LOGIC;
M00_AXI_0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_bvalid : in STD_LOGIC;
M00_AXI_0_bready : out STD_LOGIC;
M00_AXI_0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arvalid : out STD_LOGIC;
M00_AXI_0_arready : in STD_LOGIC;
M00_AXI_0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_rlast : in STD_LOGIC;
M00_AXI_0_rvalid : in STD_LOGIC;
M00_AXI_0_rready : out STD_LOGIC;
pcie_mgt_0_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component Pcie_wrapper;
end wr_spec7_pkg;
board/spec7/xwrc_board_spec7.vhd
View file @ 2ce72bf5
......@@ -175,9 +175,10 @@ entity xwrc_board_spec7 is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- No External WB interface
--External WB interface
---------------------------------------------------------------------------
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
......@@ -359,6 +360,7 @@ begin -- architecture struct
-- Avoid a deadlock. The clk_dmtd is always present and is first used to bring alive
-- the LM32 that exectutes a PLL initialisation before switching to clk_pll_62m5.
cmp_bufgmux: BUFGMUX
port map (
O => clk_sys_62m5,
......@@ -530,6 +532,8 @@ begin -- architecture struct
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
general-cores @ 7f67f492
Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
Subproject commit 7f67f492467247481763cfff326709f2bc1b3754
platform/xilinx/Manifest.py
View file @ 2ce72bf5
files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
modules = {"local" : ["wr_gtp_phy", "chipscope", "wr_pcie"]}
platform/xilinx/wr_pcie/Pcie.tcl 0 → 100644
View file @ 2ce72bf5
################################################################
# This is a generated script based on design: Pcie
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source Pcie_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z035fbg676-1
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name Pcie
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:xdma:4.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M00_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI_0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {62500000} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4} \
] $M00_AXI_0
set pcie_mgt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt_0 ]
# Create ports
set aclk1_0 [ create_bd_port -dir I -type clk -freq_hz 62500000 aclk1_0 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M00_AXI_0} \
] $aclk1_0
set pcie_clk [ create_bd_port -dir I -type clk pcie_clk ]
set pcie_rst_n [ create_bd_port -dir I -type rst pcie_rst_n ]
set user_lnk_up_0 [ create_bd_port -dir O user_lnk_up_0 ]
set usr_irq_ack_0 [ create_bd_port -dir O -from 0 -to 0 usr_irq_ack_0 ]
set usr_irq_req_0 [ create_bd_port -dir I -from 0 -to 0 usr_irq_req_0 ]
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_CLKS {2} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
# Create instance: xdma_0, and set properties
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
set_property -dict [ list \
CONFIG.PF0_DEVICE_ID_mqdma {9022} \
CONFIG.PF2_DEVICE_ID_mqdma {9022} \
CONFIG.PF3_DEVICE_ID_mqdma {9022} \
CONFIG.axilite_master_en {true} \
CONFIG.axilite_master_scale {Kilobytes} \
CONFIG.axilite_master_size {256} \
CONFIG.axisten_freq {125} \
CONFIG.cfg_mgmt_if {false} \
CONFIG.pcie_extended_tag {false} \
CONFIG.pf0_device_id {7022} \
CONFIG.pf0_link_status_slot_clock_config {false} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
CONFIG.pf0_msix_cap_table_bir {BAR_1} \
CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \
CONFIG.pl_link_cap_max_link_width {X2} \
CONFIG.plltype {QPLL1} \
CONFIG.xdma_axi_intf_mm {AXI_Stream} \
] $xdma_0
# Create interface connections
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports M00_AXI_0] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net xdma_0_M_AXIS_H2C_0 [get_bd_intf_pins xdma_0/M_AXIS_H2C_0] [get_bd_intf_pins xdma_0/S_AXIS_C2H_0]
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pcie_mgt_0] [get_bd_intf_pins xdma_0/pcie_mgt]
# Create port connections
connect_bd_net -net aclk1_0_1 [get_bd_ports aclk1_0] [get_bd_pins smartconnect_0/aclk1]
connect_bd_net -net sys_clk_0_1 [get_bd_ports pcie_clk] [get_bd_pins xdma_0/sys_clk]
connect_bd_net -net sys_rst_n_0_1 [get_bd_ports pcie_rst_n] [get_bd_pins xdma_0/sys_rst_n]
connect_bd_net -net usr_irq_req_0_1 [get_bd_ports usr_irq_req_0] [get_bd_pins xdma_0/usr_irq_req]
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins smartconnect_0/aresetn] [get_bd_pins xdma_0/axi_aresetn]
connect_bd_net -net xdma_0_user_lnk_up [get_bd_ports user_lnk_up_0] [get_bd_pins xdma_0/user_lnk_up]
connect_bd_net -net xdma_0_usr_irq_ack [get_bd_ports usr_irq_ack_0] [get_bd_pins xdma_0/usr_irq_ack]
# Create address segments
assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs M00_AXI_0/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
set dir [get_property DIRECTORY [current_project]]
close_bd_design $design_name
make_wrapper -files [get_files $dir/${proj_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top
add_files -norecurse $dir/${proj_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.vhd
top/spec7_write_design/spec7_write_top.vhd
View file @ 2ce72bf5
......@@ -57,6 +57,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec7_pkg.all;
use work.axi4_pkg.all;
library unisim;
use unisim.vcomponents.all;
......@@ -182,7 +183,19 @@ entity spec7_write_top is
-- EEPROM (24AA64 Addr 1010.000x) and
-- Unique ID (24AA025EU48, Addr 1010.001x).
scl_b : inout std_logic;
sda_b : inout std_logic
sda_b : inout std_logic;
---------------------------------------------------------------------------
-- PCIe interface
---------------------------------------------------------------------------
pci_clk_n : in std_logic;
pci_clk_p : in std_logic;
perst_n : in std_logic;
rxn : in std_logic_vector(1 downto 0);
rxp : in std_logic_vector(1 downto 0);
txn : out std_logic_vector(1 downto 0);
txp : out std_logic_vector(1 downto 0)
);
end entity spec7_write_top;
......@@ -256,6 +269,19 @@ architecture top of spec7_write_top is
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
--Axi4
signal m_axil_i : t_axi4_lite_master_in_32;
signal m_axil_o : t_axi4_lite_master_out_32;
signal axi_h2c_fifo_64, axi_c2h_fifo_64 : t_axis_64;
--Wishbone
signal wb_master_i : t_wishbone_master_in;
signal wb_master_o : t_wishbone_master_out;
--PCIe
signal pci_clk : std_logic;
component pll_62m5_500m is
port (
......@@ -283,6 +309,71 @@ begin -- architecture top
wdog_n_o <= '1';
-- prsnt_m2c_l_i isn't used but must be defined as input.
pci_clk_buf : IBUFDS_GTE2
port map(
I => pci_clk_p,
IB => pci_clk_n,
O => pci_clk,
ODIV2 => open,
CEB => '0'
);
Pcie: Pcie_wrapper
port map (
M00_AXI_0_araddr => m_axil_o.araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_clk => pci_clk,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
AXI2WB : xwb_axi4lite_bridge
port map(
clk_sys_i => clk_sys_62m5,
rst_n_i => reset_n_i,
axi4_slave_i => m_axil_o,
axi4_slave_o => m_axil_i,
wb_master_o => wb_master_o,
wb_master_i => wb_master_i
);
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
......@@ -305,7 +396,6 @@ begin -- architecture top
clk_ref_62m5_o => clk_ref_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
......@@ -347,6 +437,9 @@ begin -- architecture top
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- Wishbone
wb_slave_i => wb_master_o,
wb_slave_o => wb_master_i,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => open,
......
top/spec7_write_design/spec7_write_top.xdc
View file @ 2ce72bf5
......@@ -94,6 +94,27 @@ set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[0]}]
set_property PACKAGE_PIN C12 [get_ports {pll_wr_mode_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
set_property PACKAGE_PIN D13 [get_ports perst_n]
set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
......@@ -123,14 +144,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports sfp_tx_disable_o]
set_property PACKAGE_PIN K13 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- PCIe PERST#
# ---------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN D13 [get_ports perst_n]
#set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
......
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